| INST_RETIRED.ANY |
Fixed Counter: Counts the number of instructions retired. |
IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Architectural Fixed AtRetirement |
| CPU_CLK_UNHALTED.CORE |
Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD] |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| CPU_CLK_UNHALTED.THREAD |
Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE] |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| CPU_CLK_UNHALTED.REF_TSC |
Fixed Counter: Counts the number of unhalted reference clock cycles. |
IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| BR_INST_RETIRED.ALL_BRANCHES |
Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. |
EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] Architectural AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES |
Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. |
EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] Architectural AtRetirement |
| CPU_CLK_UNHALTED.CORE_P |
Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P] |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural Speculative |
| CPU_CLK_UNHALTED.REF_TSC_P |
Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. |
EventSel=3CH UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural Speculative |
| CPU_CLK_UNHALTED.THREAD_P |
Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P] |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural Speculative |
| INST_RETIRED.ANY_P |
Counts the number of instructions retired. |
EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] Architectural AtRetirement |
| LONGEST_LAT_CACHE.MISS |
Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural Speculative |
| LONGEST_LAT_CACHE.REFERENCE |
Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural Speculative |
| ARITH.DIV_ACTIVE |
Counts the number of cycles when any of the floating point or integer dividers are active. |
EventSel=CDH UMask=03H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_ACTIVE |
Counts the number of cycles when any of the floating point dividers are active. |
EventSel=CDH UMask=02H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_OCCUPANCY |
Counts the number of floating point dividers per cycle in the loop stage. |
EventSel=CDH UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_UOPS |
Counts the number of floating point divider uops executed per cycle. |
EventSel=CDH UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.IDIV_ACTIVE |
Counts the number of cycles when any of the integer dividers are active. |
EventSel=CDH UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.IDIV_OCCUPANCY |
Counts number of active integer dividers per cycle. |
EventSel=CDH UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.IDIV_UOPS |
Counts the number of integer divider uops executed per cycle. |
EventSel=CDH UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.ANY |
Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. |
EventSel=E6H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.COND |
Counts the number of BACLEARS due to a conditional jump. |
EventSel=E6H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.INDIRECT |
Counts the number of BACLEARS due to an indirect branch. |
EventSel=E6H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.RETURN |
Counts the number of BACLEARS due to a return branch. |
EventSel=E6H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.UNCOND |
Counts the number of BACLEARS due to a direct, unconditional jump. |
EventSel=E6H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BR_INST_RETIRED.COND |
Counts the number of conditional branch instructions retired. |
EventSel=C4H UMask=07H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_NTAKEN |
Counts the number of not taken conditional branch instructions retired. |
EventSel=C4H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN |
Counts the number of taken conditional branch instructions retired. |
EventSel=C4H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN_BWD |
Counts the number of taken backward conditional branch instructions retired. |
EventSel=C4H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN_FWD |
Counts the number of taken forward conditional branch instructions retired. |
EventSel=C4H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL |
Counts the number of near CALL branch instructions retired. |
EventSel=C4H UMask=30H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_DIRECT_CALL |
Counts the number of near direct CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_CALL] |
EventSel=C4H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_DIRECT_JMP |
Counts the number of near direct JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_DIR_JMP] |
EventSel=C4H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_INDIRECT |
Counts the number of near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND] |
EventSel=C4H UMask=50H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_INDIRECT_CALL |
Counts the number of near indirect CALL branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_CALL] |
EventSel=C4H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_INDIRECT_JMP |
Counts the number of near indirect JMP branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_IND_JMP] |
EventSel=C4H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN |
Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired. [This event is alias to BR_INST_RETIRED.ALL_NEAR_IND_OR_RET] |
EventSel=C4H UMask=58H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_JMP |
Counts the number of near JMP branch instructions retired. |
EventSel=C4H UMask=C0H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN |
Counts the number of near RET branch instructions retired. [This event is alias to BR_INST_RETIRED.NEAR_RET] |
EventSel=C4H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN |
Counts the number of near taken branch instructions retired. |
EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_NTAKEN |
Counts the number of mispredicted not taken conditional branch instructions retired. |
EventSel=C5H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN |
Counts the number of mispredicted taken conditional branch instructions retired. |
EventSel=C5H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.NEAR_INDIRECT |
Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. [This event is alias to BR_MISP_RETIRED.ALL_NEAR_IND] |
EventSel=C5H UMask=50H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.NEAR_RETURN |
Counts the number of mispredicted near RET branch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET] |
EventSel=C5H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| CORE_REJECT_L2Q.ANY |
Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core's dirty eviction when the address conflicts with incoming external snoops. Note that L2 prefetcher requests that are dropped are not counted by this event. Counts on a per core basis. |
EventSel=31H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.MISS_CAUSED_WALK |
Counts the number of page walks initiated by a demand load that missed the first and second level TLBs. |
EventSel=08H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB. |
EventSel=08H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=08H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=08H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.MISS_CAUSED_WALK |
Counts the number of page walks initiated by a store that missed the first and second level TLBs. |
EventSel=49H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB. |
EventSel=49H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=49H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=49H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_FLOPS_RETIRED.ALL |
Counts the number of all types of floating point operations per uop with all default weighting |
EventSel=C8H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_FLOPS_RETIRED.FP32 |
Counts the number of floating point operations that produce 32 bit single precision results |
EventSel=C8H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_FLOPS_RETIRED.FP64 |
Counts the number of floating point operations that produce 64 bit double precision results |
EventSel=C8H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.128B_DP |
Counts the number of retired instructions whose sources are a packed 128 bit double precision floating point. This may be SSE or AVX.128 operations. |
EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.128B_SP |
Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. |
EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.256B_DP |
Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. |
EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.256B_SP |
Counts the number of retired instructions whose sources are a packed 256 bit single precision floating point. |
EventSel=C7H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.32B_SP |
Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. |
EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.64B_DP |
Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. |
EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_INST_RETIRED.ALL |
Counts the total number of floating point retired instructions. |
EventSel=C7H UMask=3FH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FP_VINT_UOPS_EXECUTED.ALL |
Counts the number of uops executed on all floating point ports. |
EventSel=B2H UMask=1FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.P0 |
Counts the number of uops executed on floating point and vector integer port 0. |
EventSel=B2H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.P1 |
Counts the number of uops executed on floating point and vector integer port 1. |
EventSel=B2H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.P2 |
Counts the number of uops executed on floating point and vector integer port 2. |
EventSel=B2H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.P3 |
Counts the number of uops executed on floating point and vector integer port 3. |
EventSel=B2H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.PRIMARY |
Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3. |
EventSel=B2H UMask=1EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_VINT_UOPS_EXECUTED.STD |
Counts the number of uops executed on floating point and vector integer store data port. |
EventSel=B2H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FRONTEND_RETIRED.ICACHE |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss |
EventSel=C6H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss |
EventSel=C6H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L2_HIT |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L2 cache. |
EventSel=C9H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L2_MISS |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 cache. |
EventSel=C9H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache. |
EventSel=C9H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_NO_SNOOP |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and did not have to snoop another core. |
EventSel=C9H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L3_HIT_WITH_SNOOP |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that hit in the L3 cache, and required a snoop (that resulted in a snoop miss, snoop hitm, snoop hit with fwd, or snoop hit with no fwd). |
EventSel=C9H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ICACHE_L3_MISS |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to Instruction L1 cache miss, that also missed in the L2 and L3 caches. |
EventSel=C9H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB. |
EventSel=C9H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that also missed the second level TLB. |
EventSel=C9H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| ICACHE.ACCESSES |
Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump. |
EventSel=80H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ICACHE.HIT |
Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present. |
EventSel=80H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ICACHE.MISSES |
Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - |
EventSel=80H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.2ND |
Counts the number of uops executed on secondary integer ports 0,1,2,3. |
EventSel=B3H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.ALL |
Counts the number of uops executed on all Integer ports. |
EventSel=B3H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.LD |
Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector |
EventSel=B3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.P0 |
Counts the number of uops executed on integer port 0. |
EventSel=B3H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.P1 |
Counts the number of uops executed on integer port 1. |
EventSel=B3H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.P2 |
Counts the number of uops executed on integer port 2. |
EventSel=B3H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.P3 |
Counts the number of uops executed on integer port 3. |
EventSel=B3H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.PRIMARY |
Counts the number of uops executed on integer port 0,1, 2, 3. |
EventSel=B3H UMask=78H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.STA |
Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector |
EventSel=B3H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_UOPS_EXECUTED.STD_JMP |
Counts the number of uops executed on an integer store data and jump port. |
EventSel=B3H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.MISS_CAUSED_WALK |
Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs. |
EventSel=85H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB. |
EventSel=85H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=85H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=85H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks. |
EventSel=85H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_IN.E |
Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis. |
EventSel=25H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REJECT_XQ.ANY |
Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The IDI link is a central on-die protocol for memory and coherence traffic between the core and the uncore. It is highly optimized for efficiency, bandwidth, and coherency, using multiple channels and flow control mechanisms to manage high-throughput, low-latency data and protocol communication within the chip. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims). |
EventSel=30H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.ALL |
Counts the number of L2 cache accesses from front door requests for Code Read, Data Read, RFO, ITOM, and L2 Prefetches. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_CODE_RD |
Counts the number of L2 cache accesses from front door Demand Code Read requests. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=C4H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_CODE_RD_HIT |
Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a hit. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=84H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_CODE_RD_MISS |
Counts the number of L2 cache accesses from front door Demand Code Read requests that resulted in a Miss. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=44H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_DATA_RD |
Counts the number of L2 cache accesses from front door Demand Data Read requests. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=C1H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_DATA_RD_HIT |
Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a hit. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_DATA_RD_MISS |
Counts the number of L2 cache accesses from front door Demand Data Read requests that resulted in a Miss. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_RFO |
Counts the number of L2 cache accesses from front door Demand RFO requests. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=C2H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_RFO_HIT |
Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a hit. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=82H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.DEMAND_RFO_MISS |
Counts the number of L2 cache accesses from front door Demand RFO requests that resulted in a Miss. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=42H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.HIT |
Counts the number of L2 cache accesses from front door requests that resulted in a Hit. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=BFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.HWPF |
Counts the number of L2 cache accesses from front door Hardware Prefetch requests. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=C8H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.HWPF_HIT |
Counts the number of L2 cache accesses from front door Hardware Prefetch requests that result in a hit. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=88H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.HWPF_MISS |
Counts the number of L2 cache accesses from front door Hardware Prefetch requests that result in a miss. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=48H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.MISS |
Counts the number of L2 cache accesses from front door requests that resulted in a Miss. Does not include rejects or recycles, per core event. |
EventSel=24H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LBR_INSERTS.ANY |
Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS] |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_BLOCKS.ADDRESS_ALIAS |
Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. |
EventSel=03H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_BLOCKS.ALL |
Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks). |
EventSel=03H UMask=1FH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_BLOCKS.DATA_UNKNOWN |
Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. |
EventSel=03H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_BLOCKS.DTLB_MISS |
Counts the number of retired loads that are blocked due to a first level TLB miss. |
EventSel=03H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_BLOCKS.STORE_FORWARD |
Counts the number of retired loads that are blocked because its address partially overlapped with an older store. |
EventSel=03H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| LD_HEAD.L1_BOUND_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. |
EventSel=05H UMask=F4H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_MISS |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss. |
EventSel=05H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_MISS_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss. |
EventSel=05H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.OTHER |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases such as pipeline conflicts, fences, etc. |
EventSel=05H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.OTHER_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc. |
EventSel=05H UMask=C0H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.WCB_FULL |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress. |
EventSel=05H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.WCB_FULL_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress. |
EventSel=05H UMask=82H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.ANY |
Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist. |
EventSel=C3H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.ANY_FAST |
Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode. |
EventSel=C3H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.DISAMBIGUATION |
Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. |
EventSel=C3H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.DISAMBIGUATION_FAST |
Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode. |
EventSel=C3H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.FPC_VIRTUAL_TRAP |
Counts the number of virtual traps taken. |
EventSel=C3H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.FP_ASSIST |
Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. |
EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING |
Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. |
EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING_FAST |
Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode. |
EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MRN_NUKE |
Counts the number of machine clears due to memory renaming. |
EventSel=C3H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MRN_NUKE_FAST |
Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode. |
EventSel=C3H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.PAGE_FAULT |
Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. |
EventSel=C3H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SMC |
Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. |
EventSel=C3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.XMC |
Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. |
EventSel=C3H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.ALL |
Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss. |
EventSel=34H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.L2_HIT |
Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache. |
EventSel=34H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.L2_MISS |
Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache. |
EventSel=34H UMask=7EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_HIT |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. |
EventSel=34H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_HIT_NOSNOOP |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, no snoop was required. LLC provided data. |
EventSel=34H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_HIT_SNOOP |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC, a snoop was required, the snoop misses or the snoop hits but no fwd. LLC provides the data. |
EventSel=34H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_MISS |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. |
EventSel=34H UMask=38H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_MISS_LOCALMEM |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches. DRAM, MMIO or other LOCAL memory type provides the data. |
EventSel=34H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_MISS_OTHERMOD |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the caches, a snoop was required, and hits in other core or module on same die. Another core provides the data with a fwd, no fwd, or hitM. |
EventSel=34H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.ALL |
Counts the total number of load ops retired that miss the L3 cache. |
EventSel=D3H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM |
Counts the number of load ops retired that miss the L3 cache and hit in DRAM |
EventSel=D3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.MEMSIDE_CACHE |
Counts the number of load ops retired that miss the L3 cache and hit in memside cache. |
EventSel=D3H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_HITM |
Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and modified data was forwarded. |
EventSel=D4H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_NO_FWD |
Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and no data was forwarded. |
EventSel=D4H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_WITH_FWD |
Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and non-modified data was forwarded. |
EventSel=D4H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_HIT |
Counts the number of load ops retired that hit the L1 data cache. |
EventSel=D1H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_MISS |
Counts the number of load ops retired that miss in the L1 data cache. |
EventSel=D1H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_HIT |
Counts the number of load ops retired that hit in the L2 cache. |
EventSel=D1H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_MISS |
Counts the number of load ops retired that miss in the L2 cache. |
EventSel=D1H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT |
Counts the number of load ops retired that hit in the L3 cache. |
EventSel=D1H UMask=1CH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT_NO_SNOOP |
Counts the number of load ops retired that hit in the L3 cache in which no snoop was required. |
EventSel=D1H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT_SNOOP_HIT |
Counts the number of load ops retired that hit in the L3 cache in which a snoop was required and it hit and forwarded data, it hit and did not forward data, or it hit and the forwarded data was modified. |
EventSel=D1H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_SCHEDULER_BLOCK.ALL |
Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. |
EventSel=04H UMask=07H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.LD_BUF |
Counts the number of cycles that uops are blocked due to a load buffer full condition. |
EventSel=04H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.RSV |
Counts the number of cycles that uops are blocked due to an RSV full condition. |
EventSel=04H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.ST_BUF |
Counts the number of cycles that uops are blocked due to a store buffer full condition. |
EventSel=04H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_UOPS_RETIRED.ALL |
Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST). |
EventSel=D0H UMask=83H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.ALL_LOADS |
Counts the number of load ops retired. |
EventSel=D0H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.ALL_STORES |
Counts the number of store ops retired. |
EventSel=D0H UMask=82H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY |
Counts the number of tagged load uops retired. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024 |
Counts the number of tagged load uops retired that exceed the latency threshold of 1024. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128 |
Counts the number of tagged load uops retired that exceed the latency threshold of 128. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16 |
Counts the number of tagged load uops retired that exceed the latency threshold of 16. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048 |
Counts the number of tagged load uops retired that exceed the latency threshold of 2048. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256 |
Counts the number of tagged load uops retired that exceed the latency threshold of 256. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32 |
Counts the number of tagged load uops retired that exceed the latency threshold of 32. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4 |
Counts the number of tagged load uops retired that exceed the latency threshold of 4. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512 |
Counts the number of tagged load uops retired that exceed the latency threshold of 512. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64 |
Counts the number of tagged load uops retired that exceed the latency threshold of 64. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8 |
Counts the number of tagged load uops retired that exceed the latency threshold of 8. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOCK_LOADS |
Counts the number of load uops retired that performed one or more locks |
EventSel=D0H UMask=21H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.MRN_LOADS |
Counts the number of load uops retired that were correctly predicated by the memory renaming (MRN) feature. MRN loads are a part of the memory renaming process that optimizes data forwarding between stores and loads, reducing latency and improving performance. This involves tagging stores that forward to loads and copying the physical source (the actual data) directly from the store to the load. The MRN'd load can complete without accessing the memory, thus reducing load-to-use latency. |
EventSel=D0H UMask=09H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.MRN_STORES |
Counts the number of store uops retired that were correctly tagged by the memory renaming (MRN) feature. MRN stores are a part of the memory renaming process that optimizes data forwarding between stores and loads, reducing latency and improving performance. This involves tagging stores that forward to loads and copying the physical source (the actual data) directly from the store to the load. The MRN store ensures that it's data is accurately forwarded to matching subsequent loads. |
EventSel=D0H UMask=0AH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT |
Counts the number of memory uops retired that were splits. |
EventSel=D0H UMask=43H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_LOADS |
Counts the number of retired split load uops. |
EventSel=D0H UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_STORES |
Counts the number of retired split store uops. |
EventSel=D0H UMask=42H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS |
Counts the number of memory uops retired that missed in the second level TLB. |
EventSel=D0H UMask=13H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS |
Counts the number of load uops retired that miss in the second Level TLB. |
EventSel=D0H UMask=11H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_STORES |
Counts the number of store uops retired that miss in the second level TLB. |
EventSel=D0H UMask=12H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.STORE_LATENCY |
Counts the number of stores uops retired. |
EventSel=D0H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISALIGN_MEM_REF.LOAD_PAGE_SPLIT |
Counts misaligned loads that are 4K page splits. |
EventSel=13H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISALIGN_MEM_REF.STORE_PAGE_SPLIT |
Counts misaligned stores that are 4K page splits. |
EventSel=13H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISC_RETIRED1.CL_INST |
Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. |
EventSel=E0H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISC_RETIRED1.LFENCE |
Counts the number of LFENCE instructions retired. |
EventSel=E0H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISC_RETIRED2.KEYLOCKER_ACCESS |
Counts the number of accesses to KeyLocker cache. |
EventSel=E1H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MISC_RETIRED2.KEYLOCKER_MISS |
Counts the number of misses to KeyLocker cache. |
EventSel=E1H UMask=11H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| MS_DECODED.MS_BUSY |
Counts the number of cycles that the micro-sequencer is busy. |
EventSel=E7H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MS_DECODED.MS_ENTRY |
Counts the number of times entered into a ucode flow in the FEC. Includes inserted flows due to front-end detected faults or assists. |
EventSel=E7H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| PREDICTION.BTCLEAR |
Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch. |
EventSel=E8H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| SERIALIZATION.C01_MS_SCB |
Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state). |
EventSel=75H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| SERIALIZATION.COLOR_STALLS |
Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use. |
EventSel=75H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| SERIALIZATION.IQ_JEU_SCB |
Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE. |
EventSel=75H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| SERIALIZATION.NON_C01_MS_SCB |
Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE. |
EventSel=75H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.ALL |
Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. |
IA32_FIXED_CTR4 PEBS:[NonPreciseEventingIP] Fixed Speculative |
| TOPDOWN_BAD_SPECULATION.ALL_P |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. |
EventSel=73H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.FASTNUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes |
EventSel=73H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.LSD_MISPREDICT |
Counts the number of issue slots every cycle that were not consumed by the backend due to a branch mispredict that resulted in LSD exit. |
EventSel=73H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. |
EventSel=73H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MISPREDICT |
Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict |
EventSel=73H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.NUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). |
EventSel=73H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALL |
Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P] |
EventSel=A4H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS |
Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions. |
EventSel=74H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALL_P |
Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL] |
EventSel=A4H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.LSD |
Counts the number of issue slots every cycle that were not consumed by the backend due to LSD entry. |
EventSel=74H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block. |
EventSel=74H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop). |
EventSel=74H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REGISTER |
Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST). |
EventSel=74H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REORDER_BUFFER |
Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full |
EventSel=74H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.SERIALIZATION |
Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb |
EventSel=74H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ALL |
Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls. |
IA32_FIXED_CTR5 PEBS:[NonPreciseEventingIP] Fixed Speculative |
| TOPDOWN_FE_BOUND.ALL_P |
Counts the number of retirement slots not consumed due to front end stalls. |
EventSel=9CH UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_DETECT |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear |
EventSel=71H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_RESTEER |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear |
EventSel=71H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.CISC |
Counts the number of issue slots every cycle that were not delivered by the frontend due to ms |
EventSel=71H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.DECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall |
EventSel=71H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH |
Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. |
EventSel=71H UMask=8DH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_LATENCY |
Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. |
EventSel=71H UMask=72H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ICACHE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss |
EventSel=71H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ITLB_MISS |
Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss |
EventSel=71H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.OTHER |
Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall |
EventSel=71H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.PREDECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong |
EventSel=71H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_RETIRING.ALL |
Fixed Counter: Counts the number of consumed retirement slots. |
IA32_FIXED_CTR6 PEBS:[PreciseEventingIP] Fixed AtRetirement |
| TOPDOWN_RETIRING.ALL_P |
Counts the number of consumed retirement slots. |
EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_ISSUED.ANY |
Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. |
EventSel=0EH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.ALL |
Counts the total number of uops retired. |
EventSel=C2H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.DUAL_DEST |
Counts the number of uops retired that were dual destination. Dual destination (dual dest) micro-operations require writing to two separate destination registers or memory addresses upon execution. These uops consume two entries in the ROB and tracked separately because they involve more complex operations that necessitate multiple results. |
EventSel=C2H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_RETIRED.EOM |
Counts the number of uops retired that are the last uop of a macro-instruction. EOM uops indicate the 'end of a macro-instruction' and play a crucial role in the processor's control flow and recovery mechanisms. |
EventSel=C2H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.FPDIV |
Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). |
EventSel=C2H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_RETIRED.IDIV |
Counts the number of integer divide uops retired. |
EventSel=C2H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_RETIRED.LSD |
Counts the number of uops retired that originated from a loop stream detector. |
EventSel=C2H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_RETIRED.MS |
Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. |
EventSel=C2H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.NANO_CODE |
UOPS_RETIRED.NANO_CODE |
EventSel=C2H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement |
| UOPS_RETIRED.X87 |
Counts the number of x87 uops retired, includes those in ms flows. |
EventSel=C2H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.ALL_NEAR_IND |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT] |
EventSel=C4H UMask=50H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.ALL_NEAR_IND_OR_RET |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN] |
EventSel=C4H UMask=58H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.NEAR_DIR_CALL |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_CALL] |
EventSel=C4H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.NEAR_DIR_JMP |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_DIRECT_JMP] |
EventSel=C4H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.NEAR_IND_CALL |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_CALL] |
EventSel=C4H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.NEAR_IND_JMP |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_INDIRECT_JMP] |
EventSel=C4H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_INST_RETIRED.NEAR_RET |
This event is deprecated. [This event is alias to BR_INST_RETIRED.NEAR_RETURN] |
EventSel=C4H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_MISP_RETIRED.ALL_NEAR_IND |
This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_INDIRECT] |
EventSel=C5H UMask=50H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| BR_MISP_RETIRED.NEAR_RET |
This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN] |
EventSel=C5H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |
| MISC_RETIRED.LBR_INSERTS |
This event is deprecated. [This event is alias to LBR_INSERTS.ANY] |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7, PDISTCounter=0,1] AtRetirement Deprecated |