| UNC_CLOCK.SOCKET |
This 48-bit fixed counter counts the UCLK cycles. |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_M_ACT_COUNT_RD |
ACT command for a read request sent to DRAM |
EventSel=24H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_TOTAL |
ACT command sent to DRAM |
EventSel=26H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_WR |
ACT command for a write request sent to DRAM |
EventSel=25H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_RD |
Read CAS command sent to DRAM |
EventSel=22H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_WR |
Write CAS command sent to DRAM |
EventSel=23H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PRE_COUNT_PAGE_MISS |
PRE command sent to DRAM for a read/write request |
EventSel=27H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_RD_DATA |
Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data. |
EventSel=3AH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_TOTAL_DATA |
Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending or receiving 32B chunk data. |
EventSel=3CH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_WR_DATA |
Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data. |
EventSel=3BH UMask=00H Counter=0,1,2,3,4 |