| UNC_CLOCK.SOCKET |
This 48-bit fixed counter counts the UCLK cycles. |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_ARB_COH_TRK_REQUESTS.ALL |
Number of entries allocated. Account for Any type: e.g. Snoop, etc. |
EventSel=84H UMask=01H Counter=0,1 |
| UNC_ARB_TRK_OCCUPANCY.ALL |
Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. |
EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_REQUESTS.ALL |
Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic. |
EventSel=81H UMask=01H Counter=0,1 |
| UNC_MC0_RDCAS_COUNT_FREERUN |
Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM. |
EventSel=00H UMask=00H Counter=1 |
| UNC_MC0_TOTAL_REQCOUNT_FREERUN |
Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. |
EventSel=00H UMask=00H Counter=0 |
| UNC_MC0_WRCAS_COUNT_FREERUN |
Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM. |
EventSel=00H UMask=00H Counter=2 |
| UNC_MC1_RDCAS_COUNT_FREERUN |
Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM. |
EventSel=00H UMask=00H Counter=4 |
| UNC_MC1_TOTAL_REQCOUNT_FREERUN |
Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM. |
EventSel=00H UMask=00H Counter=3 |
| UNC_MC1_WRCAS_COUNT_FREERUN |
Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM. |
EventSel=00H UMask=00H Counter=5 |