| UNC_CLOCK.SOCKET |
This 48-bit fixed counter counts the UCLK cycles. |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_HAC_ARB_REQ_TRK_REQUEST.DRD |
Number of all coherent Data Read entries. Doesn't include prefetches |
EventSel=81H UMask=02H Counter=0,1 |
| UNC_HAC_ARB_TRANSACTIONS.ALL |
Number of all CMI transactions |
EventSel=8AH UMask=01H Counter=0,1 |
| UNC_HAC_ARB_TRANSACTIONS.READS |
Number of all CMI reads |
EventSel=8AH UMask=02H Counter=0,1 |
| UNC_HAC_ARB_TRANSACTIONS.WRITES |
Number of all CMI writes not including "Mflush" |
EventSel=8AH UMask=04H Counter=0,1 |
| UNC_HAC_ARB_TRK_REQUESTS.ALL |
Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic. |
EventSel=81H UMask=01H Counter=0,1 |
| UNC_HAC_CBO_TOR_ALLOCATION.ALL |
Number of all entries allocated. Includes also retries. |
EventSel=35H UMask=08H Counter=0,1 |
| UNC_HAC_CBO_TOR_ALLOCATION.DRD |
Asserted on coherent DRD + DRdPref allocations into the queue. Cacheable only |
EventSel=35H UMask=01H Counter=0,1 |
| UNC_M_ACT_COUNT_RD |
ACT command for a read request sent to DRAM |
EventSel=24H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_TOTAL |
ACT command sent to DRAM |
EventSel=26H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_WR |
ACT command for a write request sent to DRAM |
EventSel=25H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_RD |
Read CAS command sent to DRAM |
EventSel=22H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_WR |
Write CAS command sent to DRAM |
EventSel=23H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PRE_COUNT_IDLE |
PRE command sent to DRAM due to page table idle timer expiration |
EventSel=28H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PRE_COUNT_PAGE_MISS |
PRE command sent to DRAM for a read/write request |
EventSel=27H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_RD_DATA |
Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data. |
EventSel=3AH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_TOTAL_DATA |
Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data. |
EventSel=3CH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_WR_DATA |
Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data. |
EventSel=3BH UMask=00H Counter=0,1,2,3,4 |
| UNC_MC0_RDCAS_COUNT_FREERUN |
Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. |
EventSel=00H UMask=00H Counter=0 |
| UNC_MC0_TOTAL_REQCOUNT_FREERUN |
Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW. |
EventSel=00H UMask=00H Counter=2 |
| UNC_MC0_WRCAS_COUNT_FREERUN |
Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. |
EventSel=00H UMask=00H Counter=1 |
| UNC_MC1_RDCAS_COUNT_FREERUN |
Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. |
EventSel=00H UMask=00H Counter=3 |
| UNC_MC1_TOTAL_REQCOUNT_FREERUN |
Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW. |
EventSel=00H UMask=00H Counter=5 |
| UNC_MC1_WRCAS_COUNT_FREERUN |
Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. |
EventSel=00H UMask=00H Counter=4 |