| UNC_CLOCK.SOCKET |
This 48-bit fixed counter counts the UCLK cycles. |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_ARB_COH_TRK_REQUESTS.ALL |
Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc. |
EventSel=84H UMask=01H Counter=0,1 |
| UNC_ARB_TRK_OCCUPANCY.ALL |
Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. |
EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST |
Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. |
EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT |
Each cycle count number of "valid" coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case. |
EventSel=80H UMask=02H Counter=0 |
| UNC_ARB_TRK_REQUESTS.ALL |
Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic. |
EventSel=81H UMask=01H Counter=0,1 |
| UNC_ARB_TRK_REQUESTS.DRD_DIRECT |
Number of Core coherent Data Read entries allocated in DirectData mode. |
EventSel=81H UMask=02H Counter=0,1 |
| UNC_ARB_TRK_REQUESTS.WRITES |
Number of Writes allocated - any write transactions: full/partials writes and evictions. |
EventSel=81H UMask=20H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_ES |
L3 Lookup any request that access cache and found line in E or S-state. |
EventSel=34H UMask=86H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_I |
L3 Lookup any request that access cache and found line in I-state. |
EventSel=34H UMask=88H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_M |
L3 Lookup any request that access cache and found line in M-state. |
EventSel=34H UMask=81H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_MESI |
L3 Lookup any request that access cache and found line in MESI-state. |
EventSel=34H UMask=8FH Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_ES |
L3 Lookup read request that access cache and found line in E or S-state. |
EventSel=34H UMask=16H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_I |
L3 Lookup read request that access cache and found line in I-state. |
EventSel=34H UMask=18H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_M |
L3 Lookup read request that access cache and found line in M-state. |
EventSel=34H UMask=11H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_MESI |
L3 Lookup read request that access cache and found line in any MESI-state. |
EventSel=34H UMask=1FH Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_ES |
L3 Lookup write request that access cache and found line in E or S-state. |
EventSel=34H UMask=26H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_M |
L3 Lookup write request that access cache and found line in M-state. |
EventSel=34H UMask=21H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_MESI |
L3 Lookup write request that access cache and found line in MESI-state. |
EventSel=34H UMask=2FH Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.HIT_XCORE |
A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core. |
EventSel=22H UMask=44H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.HITM_XCORE |
A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core. |
EventSel=22H UMask=48H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.MISS_EVICTION |
A cross-core snoop resulted from L3 Eviction which misses in some processor core. |
EventSel=22H UMask=81H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.MISS_XCORE |
A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core. |
EventSel=22H UMask=41H Counter=0,1 |