| OCR.DEMAND_CODE_RD.ANY_RESPONSE |
Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OCR.DEMAND_CODE_RD.DRAM |
Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H |
| OCR.DEMAND_CODE_RD.L3_HIT.ANY |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT |
Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C0004H |
| OCR.DEMAND_CODE_RD.L3_MISS |
Counts demand instruction fetches and L1 instruction cache prefetches that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00004H |
| OCR.DEMAND_CODE_RD.LOCAL_DRAM |
Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H |
| OCR.DEMAND_DATA_RD.ANY_RESPONSE |
Counts demand data reads that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_RD.DRAM |
Counts demand data reads that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_DATA_RD.L3_HIT.ANY |
Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM |
Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS |
Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT |
Counts demand data reads that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C0001H |
| OCR.DEMAND_DATA_RD.L3_MISS |
Counts demand data reads that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00001H |
| OCR.DEMAND_DATA_RD.LOCAL_DRAM |
Counts demand data reads that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_RFO.ANY_RESPONSE |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OCR.DEMAND_RFO.DRAM |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H |
| OCR.DEMAND_RFO.L3_HIT.ANY |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C0002H |
| OCR.DEMAND_RFO.L3_MISS |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00002H |
| OCR.DEMAND_RFO.LOCAL_DRAM |
Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H |
| OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H |
| OCR.HWPF_L1D_AND_SWPF.DRAM |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000400H |
| OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0400H |
| OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0400H |
| OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0400H |
| OCR.HWPF_L1D_AND_SWPF.L3_MISS |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00400H |
| OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM |
Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000400H |
| OCR.HWPF_L2_DATA_RD.ANY_RESPONSE |
Counts hardware prefetch data reads (which bring data to L2) that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H |
| OCR.HWPF_L2_DATA_RD.DRAM |
Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.ANY |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT |
Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_MISS |
Counts hardware prefetch data reads (which bring data to L2) that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00010H |
| OCR.HWPF_L2_DATA_RD.LOCAL_DRAM |
Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H |
| OCR.HWPF_L2_RFO.ANY_RESPONSE |
Counts hardware prefetch RFOs (which bring data to L2) that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H |
| OCR.HWPF_L2_RFO.DRAM |
Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H |
| OCR.HWPF_L2_RFO.L3_HIT.ANY |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT |
Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C0020H |
| OCR.HWPF_L2_RFO.L3_MISS |
Counts hardware prefetch RFOs (which bring data to L2) that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00020H |
| OCR.HWPF_L2_RFO.LOCAL_DRAM |
Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H |
| OCR.HWPF_L3.L3_HIT.ANY |
Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C2380H |
| OCR.OTHER.ANY_RESPONSE |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H |
| OCR.OTHER.DRAM |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184008000H |
| OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C8000H |
| OCR.OTHER.L3_HIT.SNOOP_MISS |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C8000H |
| OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C8000H |
| OCR.OTHER.L3_HIT.SNOOP_SENT |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1E003C8000H |
| OCR.OTHER.L3_MISS |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC08000H |
| OCR.OTHER.LOCAL_DRAM |
Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184008000H |
| OCR.STREAMING_WR.ANY_RESPONSE |
Counts streaming stores that have any type of response. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OCR.STREAMING_WR.DRAM |
Counts streaming stores that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000800H |
| OCR.STREAMING_WR.L3_HIT.ANY |
Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FC03C0800H |
| OCR.STREAMING_WR.L3_MISS |
Counts streaming stores that was not supplied by the L3 cache. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FFFC00800H |
| OCR.STREAMING_WR.LOCAL_DRAM |
Counts streaming stores that DRAM supplied the request. |
EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000800H |