| UNC_CLOCK.SOCKET |
This 48-bit fixed counter counts the UCLK cycles. |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_ARB_COH_TRK_REQUESTS.ALL |
Number of requests allocated in Coherency Tracker. |
EventSel=84H UMask=01H Counter=0,1 |
| UNC_ARB_REQ_TRK_REQUEST.DRD |
Number of all coherent Data Read entries. Doesn't include prefetches |
EventSel=81H UMask=02H Counter=0,1 |
| UNC_ARB_TRK_OCCUPANCY.ALL |
Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. |
EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_REQUESTS.ALL |
Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC. |
EventSel=81H UMask=01H Counter=0,1 |
| UNC_M_ACT_COUNT_RD |
ACT command for a read request sent to DRAM |
EventSel=24H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_TOTAL |
ACT command sent to DRAM |
EventSel=26H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_ACT_COUNT_WR |
ACT command for a write request sent to DRAM |
EventSel=25H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_RD |
Read CAS command sent to DRAM |
EventSel=22H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CAS_COUNT_WR |
Write CAS command sent to DRAM |
EventSel=23H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_CLOCKTICKS |
Number of clocks |
EventSel=01H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_EMPTY_RD |
incoming read request page status is "Page Empty" |
EventSel=1DH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_EMPTY_WR |
incoming write request page status is "Page Empty" |
EventSel=20H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_HIT_RD |
incoming read request page status is "Page Hit" |
EventSel=1CH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_HIT_WR |
incoming write request page status is "Page Hit" |
EventSel=1FH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_MISS_RD |
incoming read request page status is "Page Miss" |
EventSel=1EH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_PAGE_MISS_WR |
incoming write request page status is "Page Miss" |
EventSel=21H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_THERMAL_HOT |
Any Rank at Hot state |
EventSel=19H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_DRAM_THERMAL_WARM |
Any Rank at Warm state |
EventSel=1AH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PRE_COUNT_IDLE |
PRE command sent to DRAM due to page table idle timer expiration |
EventSel=28H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PRE_COUNT_PAGE_MISS |
PRE command sent to DRAM for a read/write request |
EventSel=27H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_PREFETCH_RD |
Incoming read prefetch request from IA. |
EventSel=0AH UMask=00H Counter=0,1,2,3,4 |
| UNC_M_VC0_REQUESTS_RD |
Incoming VC0 read request |
EventSel=02H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_VC0_REQUESTS_WR |
Incoming VC0 write request |
EventSel=03H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_VC1_REQUESTS_RD |
Incoming VC1 read request |
EventSel=04H UMask=00H Counter=0,1,2,3,4 |
| UNC_M_VC1_REQUESTS_WR |
Incoming VC1 write request |
EventSel=05H UMask=00H Counter=0,1,2,3,4 |
| UNC_MC0_RDCAS_COUNT_FREERUN |
Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels). |
EventSel=00H UMask=00H Counter=0 |
| UNC_MC0_WRCAS_COUNT_FREERUN |
Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). |
EventSel=00H UMask=00H Counter=1 |
| UNC_MC1_RDCAS_COUNT_FREERUN |
Counts every 64B read entering the Memory Controller 1 to DRAM (sum of all channels). |
EventSel=00H UMask=00H Counter=3 |
| UNC_MC1_WRCAS_COUNT_FREERUN |
Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). |
EventSel=00H UMask=00H Counter=4 |