| INST_RETIRED.ANY |
Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. |
IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Architectural, Fixed, AtRetirement |
| CPU_CLK_UNHALTED.CORE |
Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events. |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.THREAD |
Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events. |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.REF_TSC |
Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. |
IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| TOPDOWN.SLOTS |
Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). |
IA32_FIXED_CTR3 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| BR_INST_RETIRED.ALL_BRANCHES |
Counts all branch instructions retired. |
EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] Architectural, AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES |
Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. |
EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] Architectural, AtRetirement |
| CPU_CLK_UNHALTED.REF_TSC_P |
Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. |
EventSel=3CH UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| CPU_CLK_UNHALTED.THREAD_P |
This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| IDQ_BUBBLES.CORE |
This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method. |
EventSel=9CH UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| INST_RETIRED.ANY_P |
Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. |
EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] Architectural, AtRetirement |
| LONGEST_LAT_CACHE.MISS |
Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. |
EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| LONGEST_LAT_CACHE.REFERENCE |
Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. |
EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| MISC_RETIRED.LBR_INSERTS |
LBR record is inserted |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] Architectural, AtRetirement |
| TOPDOWN.BACKEND_BOUND_SLOTS |
This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units’ limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method. |
EventSel=A4H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| TOPDOWN.SLOTS_P |
Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. |
EventSel=A4H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, Speculative |
| UOPS_RETIRED.SLOTS |
This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance – for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method. |
EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Architectural, AtRetirement |
| ARITH.DIV_ACTIVE |
Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. |
EventSel=B0H UMask=09H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ARITH.FPDIV_ACTIVE |
Counts cycles when divide unit is busy executing divide or square root operations. Accounts for floating-point operations only. |
EventSel=B0H UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ARITH.IDIV_ACTIVE |
Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer operations only. |
EventSel=B0H UMask=08H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ASSISTS.ANY |
Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists. |
EventSel=C1H UMask=1FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ASSISTS.FP |
Counts all microcode Floating Point assists. |
EventSel=C1H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ASSISTS.HARDWARE |
Count all other "hardware assists" or traps that are not necessarily architecturally exposed (through a software handler) beyond FP; SSE-AVX mix and A/D assists who are counted by dedicated sub-events. This includes, but not limited to, assists at EXE or MEM uop writeback like AVX* load/store/gather/scatter (non-FP GSSE-assist ) , assists generated by ROB like PEBS and RTIT, Uncore trap, RAR (Remote Action Request) and CET (Control flow Enforcement Technology) assists. |
EventSel=C1H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ASSISTS.PAGE_FAULT |
ASSISTS.PAGE_FAULT |
EventSel=C1H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ASSISTS.SSE_AVX_MIX |
ASSISTS.SSE_AVX_MIX |
EventSel=C1H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| BACLEARS.ANY |
Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. |
EventSel=60H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| BE_STALLS.SCOREBOARD |
Counts cycles where the pipeline is stalled due to serializing operations. |
EventSel=A2H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| BR_INST_RETIRED.COND |
Counts conditional branch instructions retired. |
EventSel=C4H UMask=11H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_NTAKEN |
Counts not taken branch instructions retired. |
EventSel=C4H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN |
Counts taken conditional branch instructions retired. |
EventSel=C4H UMask=01H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN_BWD |
Counts taken backward conditional branch instructions retired. |
EventSel=C4H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN_FWD |
Counts taken forward conditional branch instructions retired. |
EventSel=C4H UMask=02H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH |
Counts far branch instructions retired. |
EventSel=C4H UMask=40H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.INDIRECT |
Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. |
EventSel=C4H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL |
Counts both direct and indirect near call instructions retired. |
EventSel=C4H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN |
Counts return instructions retired. |
EventSel=C4H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN |
Counts taken branch instructions retired. |
EventSel=C4H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES_COST |
All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=44H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND |
Counts mispredicted conditional branch instructions retired. |
EventSel=C5H UMask=11H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_COST |
Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=51H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_NTAKEN |
Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. |
EventSel=C5H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_NTAKEN_COST |
Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=50H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN |
Counts taken conditional mispredicted branch instructions retired. |
EventSel=C5H UMask=01H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN_BWD |
Counts taken backward conditional mispredicted branch instructions retired. |
EventSel=C5H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN_BWD_COST |
number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=01H UMaskExt=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN_COST |
Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=41H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN_FWD |
Counts taken forward conditional mispredicted branch instructions retired. |
EventSel=C5H UMask=00H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN_FWD_COST |
number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=02H UMaskExt=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.INDIRECT |
Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. |
EventSel=C5H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL |
Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. |
EventSel=C5H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL_COST |
Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=42H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_COST |
Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=C0H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN |
Counts number of near branch instructions retired that were mispredicted and taken. |
EventSel=C5H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN_COST |
Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=60H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.RET |
This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. |
EventSel=C5H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| BR_MISP_RETIRED.RET_COST |
Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. |
EventSel=C5H UMask=48H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| CPU_CLK_UNHALTED.C0_WAIT |
Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction. |
EventSel=ECH UMask=70H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CPU_CLK_UNHALTED.C01 |
Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. |
EventSel=ECH UMask=10H CMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CPU_CLK_UNHALTED.C02 |
Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. |
EventSel=ECH UMask=20H CMask=00H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CPU_CLK_UNHALTED.PAUSE |
Core clocks when a PAUSE is pending. |
EventSel=ECH UMask=40H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CPU_CLK_UNHALTED.PAUSE_INST |
Number of Pause instructions |
EventSel=ECH UMask=40H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CYCLE_ACTIVITY.CYCLES_MEM_ANY |
Cycles while memory subsystem has an outstanding load. |
EventSel=A3H UMask=10H CMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| CYCLE_ACTIVITY.STALLS_TOTAL |
Total execution stalls. |
EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DECODE.LCP |
Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. |
EventSel=87H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DECODE.MS_BUSY |
Cycles the Microcode Sequencer is busy. |
EventSel=87H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DEPENDENT_LOADS.ANY |
Count number of times a load is depending on another load that had just write back its data or in previous or 2 cycles back. This event supports in-direct dependency through a single uop. |
EventSel=02H UMask=07H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DSB2MITE_SWITCHES.PENALTY_CYCLES |
Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE. |
EventSel=61H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.STLB_HIT |
Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). |
EventSel=12H UMask=20H UMaskExt=03H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_ACTIVE |
Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. |
EventSel=12H UMask=10H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED |
Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=12H UMask=0EH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_1G |
Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=12H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M |
Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=12H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K |
Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=12H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_LOAD_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. |
EventSel=12H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.STLB_HIT |
Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). |
EventSel=13H UMask=20H UMaskExt=03H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_ACTIVE |
Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. |
EventSel=13H UMask=10H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED |
Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=13H UMask=0EH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_1G |
Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=13H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M |
Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=13H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K |
Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. |
EventSel=13H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| DTLB_STORE_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. |
EventSel=13H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.1_PORTS_UTIL |
Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty. |
EventSel=A6H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.2_3_PORTS_UTIL |
Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty. |
EventSel=A6H UMask=0CH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.2_PORTS_UTIL |
Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. |
EventSel=A6H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.3_PORTS_UTIL |
Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty. |
EventSel=A6H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.4_PORTS_UTIL |
Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty. |
EventSel=A6H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.BOUND_ON_LOADS |
Execution stalls while memory subsystem has an outstanding load. |
EventSel=A6H UMask=21H CMask=05H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.BOUND_ON_STORES |
Counts cycles where the Store Buffer was full and no loads caused an execution stall. |
EventSel=A6H UMask=40H CMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| EXE_ACTIVITY.EXE_BOUND_0_PORTS |
Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load. |
EventSel=A6H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_DISPATCHED.V0 |
Number of FP-arith-uops dispatched on 1st VEC port (port 0). FP-arith-uops are of type ADD / SUB / MUL / FMA* / DPP. |
EventSel=B3H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_DISPATCHED.V1 |
Number of FP-arith-uops dispatched on 2nd VEC port (port 1) |
EventSel=B3H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_DISPATCHED.V2 |
Number of FP-arith-uops dispatched on 3rd VEC port (port 5) |
EventSel=B3H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_DISPATCHED.V3 |
Number of FP-arith-uops dispatched on 4th VEC port |
EventSel=B3H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE |
Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE and AVX packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE |
Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE and AVX packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE |
Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE and AVX packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE |
Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE and AVX packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.4_FLOPS |
Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE and AVX packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=18H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.SCALAR |
Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE and AVX scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=03H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE |
Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE and AVX scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.SCALAR_SINGLE |
Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE and AVX scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.VECTOR |
Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. |
EventSel=C7H UMask=3CH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.VECTOR_128B |
FP_ARITH_OPS_RETIRED.VECTOR_128B |
EventSel=C7H UMask=0CH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FP_ARITH_OPS_RETIRED.VECTOR_256B |
FP_ARITH_OPS_RETIRED.VECTOR_256B |
EventSel=C7H UMask=30H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| FRONTEND_RETIRED.ANY_ANT |
Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=09H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.ANY_DSB_MISS |
Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.DSB_MISS |
Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=11H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS |
Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=14H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.L1I_MISS |
Counts retired Instructions who experienced Instruction L1 Cache true miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=12H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.L2_MISS |
Counts retired Instructions who experienced Instruction L2 Cache true miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=13H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_128 |
Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=608006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_16 |
Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=601006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2 |
Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600206H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 |
Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=100206H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_256 |
Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=610006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_32 |
Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=602006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_4 |
Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600406H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_512 |
Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=620006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_64 |
Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=604006H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_8 |
Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600806H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.MISP_ANT |
ANT retired branches that got just mispredicted |
EventSel=C6H UMask=02H MSR_PEBS_FRONTEND(3F7H)=09H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.MS_FLOWS |
Counts flows delivered by the Microcode Sequencer |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.STLB_MISS |
Counts retired Instructions that experienced STLB (2nd level TLB) true miss. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=15H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| FRONTEND_RETIRED.UNKNOWN_BRANCH |
Number retired branch instructions that caused the front-end to be resteered when it finds the instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. |
EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=17H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| ICACHE_DATA.STALL_PERIODS |
ICACHE_DATA.STALL_PERIODS |
EventSel=80H UMask=04H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ICACHE_DATA.STALLS |
Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity. |
EventSel=80H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ICACHE_TAG.STALLS |
Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. |
EventSel=83H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ICACHE_TAG.STALLS_INUSE |
Cycles where a code fetch is stalled due to L1 instruction cache In use-full |
EventSel=83H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ICACHE_TAG.STALLS_ISB |
Cycles where a code fetch is stalled due to L1 instruction cache ISB-full |
EventSel=83H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.DSB_CYCLES_ANY |
Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. |
EventSel=79H UMask=08H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.DSB_CYCLES_OK |
Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ. |
EventSel=79H UMask=08H CMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.DSB_UOPS |
Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. |
EventSel=79H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MITE_CYCLES_ANY |
Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). |
EventSel=79H UMask=04H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MITE_CYCLES_OK |
Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). |
EventSel=79H UMask=04H CMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MITE_UOPS |
Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). |
EventSel=79H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MS_CYCLES_ANY |
Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. |
EventSel=79H UMask=20H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MS_SWITCHES |
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. |
EventSel=79H UMask=20H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ.MS_UOPS |
Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. |
EventSel=79H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ_BUBBLES.CYCLES_FE_WAS_OK |
Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. |
EventSel=9CH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| IDQ_BUBBLES.FETCH_LATENCY |
Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls for 2 or more cycles - normally indicating a Fetch Latency issue. |
EventSel=9CH UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INST_DECODED.DECODERS |
Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions. |
EventSel=75H UMask=01H Counter=2 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=2] Speculative |
| INST_RETIRED.BR_FUSED |
retired macro-fused uops when there is a branch in the macro-fused pair (the two instructions that got macro-fused count once in this pmon) |
EventSel=C0H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| INST_RETIRED.MACRO_FUSED |
INST_RETIRED.MACRO_FUSED |
EventSel=C0H UMask=30H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| INST_RETIRED.NOP |
Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions |
EventSel=C0H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| INST_RETIRED.PREC_DIST |
A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0. |
IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Fixed, AtRetirement |
| INST_RETIRED.REP_ITERATION |
Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent. |
EventSel=C0H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| INT_MISC.BPCLEAR_CYCLES |
Bubble cycles of BPClear. |
EventSel=ADH UMask=40H MSR_PEBS_FRONTEND(3F7H)=0BH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_MISC.CLEAR_RESTEER_CYCLES |
Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. |
EventSel=ADH UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_MISC.CLEARS_COUNT |
Counts the number of speculative clears due to any type of branch misprediction or machine clears |
EventSel=ADH UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_MISC.RECOVERY_CYCLES |
Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event. |
EventSel=ADH UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_MISC.UNKNOWN_BRANCH_CYCLES |
Bubble cycles of BAClear (Unknown Branch). |
EventSel=ADH UMask=40H MSR_PEBS_FRONTEND(3F7H)=07H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_MISC.UOP_DROPPING |
Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons |
EventSel=ADH UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| INT_VEC_RETIRED.128BIT |
Number of vector integer instructions retired of 128-bit vector-width. |
EventSel=E7H UMask=13H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.256BIT |
Number of vector integer instructions retired of 256-bit vector-width. |
EventSel=E7H UMask=ACH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.ADD_128 |
Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions. |
EventSel=E7H UMask=03H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.ADD_256 |
Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions. |
EventSel=E7H UMask=0CH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.MUL_256 |
INT_VEC_RETIRED.MUL_256 |
EventSel=E7H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.SHUFFLES |
INT_VEC_RETIRED.SHUFFLES |
EventSel=E7H UMask=40H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.VNNI_128 |
INT_VEC_RETIRED.VNNI_128 |
EventSel=E7H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| INT_VEC_RETIRED.VNNI_256 |
INT_VEC_RETIRED.VNNI_256 |
EventSel=E7H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| ITLB_MISSES.STLB_HIT |
Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). |
EventSel=11H UMask=20H UMaskExt=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ITLB_MISSES.WALK_ACTIVE |
Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. |
EventSel=11H UMask=10H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ITLB_MISSES.WALK_COMPLETED |
Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. |
EventSel=11H UMask=0EH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ITLB_MISSES.WALK_COMPLETED_2M_4M |
Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. |
EventSel=11H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K |
Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. |
EventSel=11H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| ITLB_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. |
EventSel=11H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D.L0_REPLACEMENT |
Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. |
EventSel=51H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D.L1_REPLACEMENT |
Counts cachelines replaced into the L1 d-cache. |
EventSel=51H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D.REPLACEMENT |
Counts cachelines replaced into the L0 and L1 d-cache. |
EventSel=51H UMask=05H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D_MISS.FB_FULL |
Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. |
EventSel=49H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D_MISS.L2_STALLS |
Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. |
EventSel=49H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D_MISS.LOAD |
Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-port binary inc-bit the occupancy increases* (at FB alloc or promotion). |
EventSel=49H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L1D_PENDING.LOAD |
Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. |
EventSel=48H UMask=01H Counter=2 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=2] Speculative |
| L1D_PENDING.LOAD_CYCLES |
Counts duration of L1D miss outstanding in cycles. |
EventSel=48H UMask=01H CMask=01H Counter=2 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=2] Speculative |
| L2_LINES_IN.ALL |
Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. |
EventSel=25H UMask=1FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_LINES_OUT.NON_SILENT |
Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 |
EventSel=26H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_LINES_OUT.SILENT |
Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event. |
EventSel=26H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_LINES_OUT.USELESS_HWPF |
Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache |
EventSel=26H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.ALL_CODE_RD |
Counts the total number of L2 code requests. |
EventSel=24H UMask=E4H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.ALL_DEMAND_DATA_RD |
Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. |
EventSel=24H UMask=E1H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.CODE_RD_HIT |
Counts L2 cache hits when fetching instructions, code reads. |
EventSel=24H UMask=44H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.CODE_RD_MISS |
Counts L2 cache misses when fetching instructions. |
EventSel=24H UMask=24H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_HIT |
Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. |
EventSel=24H UMask=41H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_MISS |
Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. |
EventSel=24H UMask=21H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.MISS |
Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. |
EventSel=24H UMask=3FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.REFERENCES |
Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. |
EventSel=24H UMask=FFH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.RFO_HIT |
Counts the RFO (Read-for-Ownership) requests that hit L2 cache. |
EventSel=24H UMask=42H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| L2_RQSTS.RFO_MISS |
Counts the RFO (Read-for-Ownership) requests that miss L2 cache. |
EventSel=24H UMask=22H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LD_BLOCKS.ADDRESS_ALIAS |
Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address. |
EventSel=03H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LD_BLOCKS.NO_SR |
Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. |
EventSel=03H UMask=88H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LD_BLOCKS.STORE_EARLY |
Counts the number of times a load got early blocked due to preceding store operation with unknown address or unknown data. Excluding in-line (immediate) wakeups |
EventSel=03H UMask=A1H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LD_BLOCKS.STORE_FORWARD |
Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide. |
EventSel=03H UMask=82H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LOCK_CYCLES.CACHE_LOCK_DURATION |
This event counts the number of cycles when the L1D is locked. |
EventSel=42H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LSD.CYCLES_ACTIVE |
Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). |
EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LSD.CYCLES_OK |
Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). |
EventSel=A8H UMask=01H CMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| LSD.UOPS |
Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). |
EventSel=A8H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MACHINE_CLEARS.COUNT |
Counts the number of machine clears (nukes) of any type. |
EventSel=C3H UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING |
Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture |
EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MACHINE_CLEARS.SMC |
Counts self-modifying code (SMC) detected, which causes a machine clear. |
EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MEM_INST_RETIRED.ALL_LOADS |
Counts Instructions with at least one architecturally visible load retired. |
EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.ALL_STORES |
Counts all retired store instructions. |
EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.ALL_SWPF |
Counts all retired software prefetch instructions. |
EventSel=D0H UMask=84H Counter=0,1,2,3 PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.ANY |
Counts all retired memory instructions - loads and stores. |
EventSel=D0H UMask=87H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7,8,9, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.LOCK_LOADS |
Counts retired load instructions with locked access. |
EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.SPLIT_LOADS |
Counts retired load instructions that split across a cacheline boundary. |
EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.SPLIT_STORES |
Counts retired store instructions that split across a cacheline boundary. |
EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_HIT_ANY |
Number of retired instructions with a clean hit in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=0FH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_HIT_LOADS |
Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=09H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_HIT_STORES |
Number of retired store instructions that hit in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=0AH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_HIT_SWPF |
Number of retired SWPF instructions that hit in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=0CH Counter=0,1,2,3 PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_ANY |
Retired instructions that miss the STLB. |
EventSel=D0H UMask=17H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_LOADS |
Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_STORES |
Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_SWPF |
Number of retired SWPF instructions that (start a) miss in the 2nd-level TLB (STLB). |
EventSel=D0H UMask=14H Counter=0,1,2,3 PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD |
Counts retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$) |
EventSel=D2H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM |
Counts retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded. |
EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS |
Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. |
EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD |
Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. |
EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_MISC_RETIRED.UC |
Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). |
EventSel=D4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.FB_HIT |
Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. |
EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L1_HIT |
Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. |
EventSel=D1H UMask=01H UMaskExt=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L1_HIT_L0 |
Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. |
EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L1_HIT_L1 |
Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache. |
EventSel=D1H UMask=00H UMaskExt=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L1_MISS |
Counts retired load instructions with at least one uop that missed in the L1 cache. |
EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L2_HIT |
Counts retired load instructions with L2 cache hits as data sources. |
EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L2_MISS |
Counts retired load instructions missed L2 cache as data sources. |
EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L3_HIT |
Counts retired load instructions with at least one uop that hit in the L3 cache. |
EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_LOAD_RETIRED.L3_MISS |
Counts retired load instructions with at least one uop that missed in the L3 cache. |
EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0,1] AtRetirement |
| MEM_STORE_RETIRED.L2_HIT |
MEM_STORE_RETIRED.L2_HIT |
EventSel=44H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 |
Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=2,3,4,5,6,7,8,9 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=2,3,4,5,6,7,8,9] AtRetirement |
| MEM_TRANS_RETIRED.STORE_SAMPLE |
Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 |
EventSel=CDH UMask=02H Counter=0,1 CounterHTOff=0 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1, PDISTCounter=0,1] AtRetirement |
| MEM_UOP_RETIRED.ANY |
Number of retired micro-operations (uops) for load or store memory accesses |
EventSel=E5H UMask=0FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| MEMORY_STALLS.L1 |
Counts cycles where no execution is happening due to loads waiting for L1 cache (that is: no execution & load in flight & no load missed L1 cache) |
EventSel=46H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MEMORY_STALLS.L2 |
Counts cycles where no execution is happening due to loads waiting for L2 cache (that is: no execution & load in flight & load missed L1 & no load missed L2 cache) |
EventSel=46H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MEMORY_STALLS.L3 |
Counts cycles where no execution is happening due to loads waiting for L3 cache (that is: no execution & load in flight & load missed L1 & load missed L2 cache & no load missed L3 Cache) |
EventSel=46H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MEMORY_STALLS.MEM |
Counts cycles where no execution is happening due to loads waiting for Memory (that is: no execution & load in flight & a load missed L3 cache) |
EventSel=46H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| MISC2_RETIRED.LFENCE |
number of LFENCE retired instructions |
EventSel=E0H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.ALL_REQUESTS |
Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.. |
EventSel=21H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.DATA_RD |
Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. |
EventSel=21H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.DEMAND_CODE_RD |
Counts both cacheable and Non-Cacheable code read requests. |
EventSel=21H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.DEMAND_DATA_RD |
Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. |
EventSel=21H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.DEMAND_RFO |
Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. |
EventSel=21H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD |
Counts demand data read requests that miss the L3 cache. |
EventSel=21H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD |
Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. |
EventSel=20H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD |
Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. |
EventSel=20H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD |
Cycles where at least 1 outstanding demand data read request is pending. |
EventSel=20H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO |
Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. |
EventSel=20H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD |
Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ. |
EventSel=20H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DATA_RD |
Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. |
EventSel=20H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD |
Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. |
EventSel=20H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD |
For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. |
EventSel=20H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO |
Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion. |
EventSel=20H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD |
For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache. |
EventSel=20H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| RS.EMPTY |
Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) |
EventSel=A5H UMask=07H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| RS.EMPTY_COUNT |
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) |
EventSel=A5H UMask=07H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| RS.EMPTY_RESOURCE |
Cycles when RS was empty and a resource allocation stall is asserted |
EventSel=A5H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SQ_MISC.BUS_LOCK |
Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory. |
EventSel=2CH UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SW_PREFETCH_ACCESS.ANY |
Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed. |
EventSel=40H UMask=0FH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SW_PREFETCH_ACCESS.NTA |
Counts the number of PREFETCHNTA instructions executed. |
EventSel=40H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SW_PREFETCH_ACCESS.PREFETCHW |
Counts the number of PREFETCHW instructions executed. |
EventSel=40H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SW_PREFETCH_ACCESS.T0 |
Counts the number of PREFETCHT0 instructions executed. |
EventSel=40H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| SW_PREFETCH_ACCESS.T1_T2 |
Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. |
EventSel=40H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| TOPDOWN.BAD_SPEC_SLOTS |
Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations. |
EventSel=A4H UMask=04H Counter=0 CounterHTOff=0 PEBS:[NonPreciseEventingIP, Counter=0] Speculative |
| TOPDOWN.BR_MISPREDICT_SLOTS |
Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction. |
EventSel=A4H UMask=08H Counter=0 CounterHTOff=0 PEBS:[NonPreciseEventingIP, Counter=0] Speculative |
| TOPDOWN.MEMORY_BOUND_SLOTS |
TOPDOWN.MEMORY_BOUND_SLOTS |
EventSel=A4H UMask=10H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_DECODED.DEC0_UOPS |
This event counts the number of not dec-by-all uops decoded by decoder 0. |
EventSel=76H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.ALU |
Number of ALU integer uops dispatch to execution. |
EventSel=B2H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.INT_EU_ALL |
Number of integer uops dispatched to execution. |
EventSel=B2H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.JMP |
Number of jump uops dispatch to execution |
EventSel=B2H UMask=40H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.LOAD |
Number of Load uops dispatched to execution. |
EventSel=B2H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.SHIFT |
Number of SHIFT integer uops dispatch to execution |
EventSel=B2H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.SLOW |
Number of Slow integer uops dispatch to execution. |
EventSel=B2H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.STA |
Number of STA (Store Address) uops dispatch to execution |
EventSel=B2H UMask=80H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_DISPATCHED.STD |
Number of STD (Store Data) uops dispatch to execution |
EventSel=B2H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_EXECUTED.CYCLES_GE_1 |
Cycles where at least 1 uop was executed per-thread. |
EventSel=B1H UMask=01H CMask=01H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.CYCLES_GE_2 |
Cycles where at least 2 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=02H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.CYCLES_GE_3 |
Cycles where at least 3 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=03H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.CYCLES_GE_4 |
Cycles where at least 4 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=04H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.STALLS |
Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. |
EventSel=B1H UMask=01H Invert=1 CMask=01H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.THREAD |
Counts the number of uops to be executed per-thread each cycle. |
EventSel=B1H UMask=01H Counter=3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=3] Speculative |
| UOPS_EXECUTED.X87 |
Counts the number of x87 uops executed. |
EventSel=B1H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_ISSUED.ANY |
Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS). |
EventSel=AEH UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_ISSUED.CYCLES |
UOPS_ISSUED.CYCLES |
EventSel=AEH UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| UOPS_RETIRED.CYCLES |
Counts cycles where at least one uop has retired. |
EventSel=C2H UMask=02H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| UOPS_RETIRED.HEAVY |
Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count. |
EventSel=C2H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| UOPS_RETIRED.MS |
UOPS_RETIRED.MS |
EventSel=C2H UMask=04H MSR_PEBS_FRONTEND(3F7H)=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| UOPS_RETIRED.MS_SWITCHES |
Switches to the Microcode Sequencer |
EventSel=C2H UMask=04H EdgeDetect=1 CMask=01H MSR_PEBS_FRONTEND(3F7H)=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| UOPS_RETIRED.STALLS |
This event counts cycles without actually retired uops. |
EventSel=C2H UMask=02H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement |
| XQ.FULL |
number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache). |
EventSel=2DH UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative |
| FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_DOUBLE |
EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.128B_PACKED_SINGLE |
EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_DOUBLE |
EventSel=C7H UMask=10H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.256B_PACKED_SINGLE |
EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.4_FLOPS |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.4_FLOPS |
EventSel=C7H UMask=18H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.SCALAR |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR |
EventSel=C7H UMask=03H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.SCALAR_DOUBLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_DOUBLE |
EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.SCALAR_SINGLE |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.SCALAR_SINGLE |
EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| FP_ARITH_INST_RETIRED.VECTOR |
This event is deprecated. Refer to new event FP_ARITH_OPS_RETIRED.VECTOR |
EventSel=C7H UMask=3CH Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] AtRetirement, Deprecated |
| IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE |
This event is deprecated. |
EventSel=9CH UMask=01H CMask=08H Counter=0,1,2,3,4,5,6,7,8,9 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7,8,9] Speculative, Deprecated |