| UNC_M_HCLOCKTICKS |
Half clockticks for IMC |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_U_CLOCKTICKS |
Clockticks in the UBOX using a dedicated 48-bit Fixed Counter |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_CHA_CLOCKTICKS |
Clockticks of the uncore caching and home agent (CHA) |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_CHA_IMC_READS_COUNT.NORMAL |
Normal priority reads issued to the memory controller from the CHA |
EventSel=59H UMask=01H |
| UNC_CHA_IMC_WRITES_COUNT.FULL |
CHA to iMC Full Line Writes Issued : Full Line Non-ISOCH |
EventSel=5BH UMask=01H |
| UNC_CHA_LLC_LOOKUP.DATA_READ |
Cache and Snoop Filter Lookups; Data Read Request |
EventSel=34H UMask=FFH UMaskExt=1BC1H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.ALL |
Lines Victimized : All Lines Victimized |
EventSel=37H UMask=0FH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS |
Local read requests that miss the SF/LLC and remote read requests sent to the CHA's home agent |
EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES |
Local write requests that miss the SF/LLC and remote write requests sent to the CHA's home agent |
EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_SF_EVICTION.E_STATE |
Snoop filter capacity evictions for E-state entries. |
EventSel=3DH UMask=02H |
| UNC_CHA_SF_EVICTION.M_STATE |
Snoop filter capacity evictions for M-state entries. |
EventSel=3DH UMask=01H |
| UNC_CHA_SF_EVICTION.S_STATE |
Snoop filter capacity evictions for S-state entries. |
EventSel=3DH UMask=04H |
| UNC_CHA_TOR_INSERTS.IA |
TOR Inserts : All requests from iA Cores |
EventSel=35H UMask=01H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH |
TOR Inserts : CLFlushes issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD |
TOR Inserts : CRDs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT |
TOR Inserts : DRd_Opts issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C827FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C8A7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT |
TOR Inserts : All requests from iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD |
TOR Inserts : CRds issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT |
TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=C827FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=C8A7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO |
TOR Inserts : RFOs issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS |
TOR Inserts : All requests from iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD |
TOR Inserts : CRds issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT |
TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=C827FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=C8A7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR |
TOR Inserts; WCiLF misses from local IA |
EventSel=35H UMask=01H UMaskExt=C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR |
TOR Inserts; WCiL misses from local IA |
EventSel=35H UMask=01H UMaskExt=C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF |
TOR Inserts : UCRdFs issued by iA Cores that Missed LLC |
EventSel=35H UMask=01H UMaskExt=C877DEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCIL |
TOR Inserts : WCiLs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCILF |
TOR Inserts : WCiLF issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WIL |
TOR Inserts : WiLs issued by iA Cores that Missed LLC |
EventSel=35H UMask=01H UMaskExt=C87FDEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO |
TOR Inserts : RFOs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO |
TOR Inserts : All requests from IO Devices |
EventSel=35H UMask=04H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT |
TOR Inserts : All requests from IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=04H UMaskExt=CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM |
TOR Inserts : ItoMs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices |
EventSel=35H UMask=04H UMaskExt=CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS |
TOR Inserts : All requests from IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM |
TOR Inserts : ItoMs issued by IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA |
TOR Occupancy : All requests from iA Cores |
EventSel=36H UMask=01H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD |
TOR Occupancy : CRDs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT |
TOR Occupancy : DRd_Opts issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=C827FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF |
TOR Occupancy : DRd_Opt_Prefs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=C8A7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT |
TOR Occupancy : All requests from iA Cores that Hit the LLC |
EventSel=36H UMask=01H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT |
TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=C827FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF |
TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=C8A7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS |
TOR Occupancy : All requests from iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD |
TOR Occupancy : CRds issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT |
TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC |
EventSel=36H UMask=01H UMaskExt=C827FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO |
TOR Occupancy : RFOs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO |
TOR Occupancy : RFOs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO |
TOR Occupancy : All requests from IO Devices |
EventSel=36H UMask=04H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT |
TOR Occupancy : All requests from IO Devices that hit the LLC |
EventSel=36H UMask=04H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS |
TOR Occupancy : All requests from IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=C8F3FFH Counter=0 |
| UNC_IIO_CLOCKTICKS |
Clockticks of the integrated IO (IIO) traffic controller |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS_FREERUN |
Free running counter that increments for IIO clocktick |
EventSel=00H UMask=00H Counter=0 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS |
PCIe Completion Buffer Inserts of completions with data: Part 0-7 |
EventSel=C2H UMask=03H FCMask=04H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0 |
PCIe Completion Buffer Inserts of completions with data: Part 0 |
EventSel=C2H UMask=03H FCMask=04H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1 |
PCIe Completion Buffer Inserts of completions with data: Part 1 |
EventSel=C2H UMask=03H FCMask=04H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2 |
PCIe Completion Buffer Inserts of completions with data: Part 2 |
EventSel=C2H UMask=03H FCMask=04H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3 |
PCIe Completion Buffer Inserts of completions with data: Part 3 |
EventSel=C2H UMask=03H FCMask=04H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4 |
PCIe Completion Buffer Inserts of completions with data: Part 4 |
EventSel=C2H UMask=03H FCMask=04H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5 |
PCIe Completion Buffer Inserts of completions with data: Part 5 |
EventSel=C2H UMask=03H FCMask=04H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6 |
PCIe Completion Buffer Inserts of completions with data: Part 6 |
EventSel=C2H UMask=03H FCMask=04H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7 |
PCIe Completion Buffer Inserts of completions with data: Part 7 |
EventSel=C2H UMask=03H FCMask=04H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS |
PCIe Completion Buffer Occupancy of completions with data : Part 0-7 |
EventSel=D5H UMask=FFH FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0 |
PCIe Completion Buffer Occupancy of completions with data : Part 0 |
EventSel=D5H UMask=01H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1 |
PCIe Completion Buffer Occupancy of completions with data : Part 1 |
EventSel=D5H UMask=02H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2 |
PCIe Completion Buffer Occupancy of completions with data : Part 2 |
EventSel=D5H UMask=04H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3 |
PCIe Completion Buffer Occupancy of completions with data : Part 3 |
EventSel=D5H UMask=08H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4 |
PCIe Completion Buffer Occupancy of completions with data : Part 4 |
EventSel=D5H UMask=10H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5 |
PCIe Completion Buffer Occupancy of completions with data : Part 5 |
EventSel=D5H UMask=20H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6 |
PCIe Completion Buffer Occupancy of completions with data : Part 6 |
EventSel=D5H UMask=40H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7 |
PCIe Completion Buffer Occupancy of completions with data : Part 7 |
EventSel=D5H UMask=80H FCMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 |
Data requested by the CPU : Core writing to Card's MMIO space |
EventSel=C0H UMask=01H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7 |
Data requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=83H UMask=80H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL |
Number requests PCIe makes of the main die : All |
EventSel=85H UMask=01H FCMask=07H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space |
EventSel=C1H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space |
EventSel=C1H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request |
EventSel=84H UMask=80H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_M_ACT_COUNT.ALL |
DRAM Activate Count : All Activates |
EventSel=01H UMask=0BH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.ALL |
All DRAM CAS commands issued |
EventSel=04H UMask=3FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD |
All DRAM read CAS commands issued (including underfills) |
EventSel=04H UMask=0FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR |
All DRAM write CAS commands issued |
EventSel=04H UMask=30H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS |
Clockticks of the integrated memory controller (IMC) |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.HIGH |
Number of DRAM Refreshes Issued |
EventSel=45H UMask=04H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.OPPORTUNISTIC |
Number of DRAM Refreshes Issued |
EventSel=45H UMask=01H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.PANIC |
Number of DRAM Refreshes Issued |
EventSel=45H UMask=02H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.ALL |
DRAM Precharge commands. |
EventSel=02H UMask=1CH Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT |
DRAM Precharge commands. : Precharge due to page table |
EventSel=02H UMask=10H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.RD |
DRAM Precharge commands. : Precharge due to read |
EventSel=02H UMask=04H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.WR |
DRAM Precharge commands. : Precharge due to write |
EventSel=02H UMask=08H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH0 |
Read Pending Queue Allocations |
EventSel=10H UMask=01H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH1 |
Read Pending Queue Allocations |
EventSel=10H UMask=02H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH0 |
Read Pending Queue Occupancy |
EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH1 |
Read Pending Queue Occupancy |
EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH0 |
Write Pending Queue Allocations |
EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH1 |
Write Pending Queue Allocations |
EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH0 |
Write Pending Queue Occupancy |
EventSel=82H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH1 |
Write Pending Queue Occupancy |
EventSel=83H UMask=00H Counter=0,1,2,3 |
| UNC_I_CACHE_TOTAL_OCCUPANCY.MEM |
Total IRP occupancy of inbound read and write requests to coherent memory. |
EventSel=0FH UMask=04H Counter=0,1 |
| UNC_I_CLOCKTICKS |
Clockticks of the IO coherency tracker (IRP) |
EventSel=01H UMask=00H Counter=0,1 |
| UNC_I_COHERENT_OPS.PCITOM |
PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline. |
EventSel=10H UMask=10H Counter=0,1 |
| UNC_I_COHERENT_OPS.WBMTOI |
Coherent Ops : WbMtoI |
EventSel=10H UMask=40H Counter=0,1 |
| UNC_I_FAF_FULL |
FAF RF full |
EventSel=17H UMask=00H Counter=0,1 |
| UNC_I_FAF_INSERTS |
Inbound read requests received by the IRP and inserted into the FAF queue. |
EventSel=18H UMask=00H Counter=0,1 |
| UNC_I_FAF_OCCUPANCY |
Occupancy of the IRP FAF queue. |
EventSel=19H UMask=00H Counter=0,1 |
| UNC_I_FAF_TRANSACTIONS |
FAF allocation -- sent to ADQ |
EventSel=16H UMask=00H Counter=0,1 |
| UNC_I_IRP_ALL.INBOUND_INSERTS |
: All Inserts Inbound (p2p + faf + cset) |
EventSel=20H UMask=01H Counter=0,1 |
| UNC_I_MISC1.LOST_FWD |
Misc Events - Set 1 : Lost Forward |
EventSel=1FH UMask=10H Counter=0,1 |
| UNC_I_SNOOP_RESP.ALL_HIT_M |
Responses to snoops of any type that hit M line in the IIO cache |
EventSel=12H UMask=78H Counter=0,1 |
| UNC_I_TRANSACTIONS.WR_PREF |
Inbound write (fast path) requests received by the IRP. |
EventSel=11H UMask=08H Counter=0,1 |
| UNC_M2M_CLOCKTICKS |
Clockticks of the mesh to memory (M2M) |
EventSel=00H UMask=00H |
| UNC_M2M_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_M2P_CLOCKTICKS |
Clockticks of the mesh to PCI (M2P) |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2P_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_P_CLOCKTICKS |
Clockticks of the power control unit (PCU) |
EventSel=00H UMask=00H Counter=0,1,2,3 |