| UNC_M_HCLOCKTICKS |
Half clockticks for IMC |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_U_CLOCKTICKS |
Clockticks in the UBOX using a dedicated 48-bit Fixed Counter |
MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_CHA_CLOCKTICKS |
Clockticks of the uncore caching and home agent (CHA) |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_CHA_DIR_UPDATE.HA |
Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=01H |
| UNC_CHA_DIR_UPDATE.TOR |
Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=02H |
| UNC_CHA_IMC_READS_COUNT.NORMAL |
Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA. |
EventSel=59H UMask=01H |
| UNC_CHA_IMC_WRITES_COUNT.FULL |
Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels. |
EventSel=5BH UMask=01H |
| UNC_CHA_LLC_LOOKUP.DATA_READ |
Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions |
EventSel=34H UMask=FFH UMaskExt=1BC1H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.ALL |
Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. |
EventSel=37H UMask=0FH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL |
Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_REMOTE |
Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=20H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS |
Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) . |
EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL |
Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_REMOTE |
Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES |
Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL |
Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_REMOTE |
Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc). |
EventSel=50H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_SF_EVICTION.E_STATE |
Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=02H |
| UNC_CHA_SF_EVICTION.M_STATE |
Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=01H |
| UNC_CHA_SF_EVICTION.S_STATE |
Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=04H |
| UNC_CHA_TOR_INSERTS.IA |
TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH |
TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD |
TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_PREF |
TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C897FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT |
TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD |
TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD |
TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C817FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF |
TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C897FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CCC7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO |
TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA |
TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CCD7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CCC7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS |
TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD |
TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD |
TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C817FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR |
TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C81786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL |
TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C816FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR |
TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C81686H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM |
TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8168AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM |
TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8178AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF |
TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C897FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL |
TOR Inserts; Data read prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=C896FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE |
TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=C8977EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE |
TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8177EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR |
TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C81706H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM |
TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8170AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR |
TOR Inserts; Data read from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA |
TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CCD7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CCC7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR |
TOR Inserts; Data read from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C806FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C886FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8877EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C8077EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO |
TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_SPECITOM |
TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=CC57FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO |
TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT |
TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM |
TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL |
TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CC42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE |
TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CC437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CD42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CD437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS |
TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM |
TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_RFO |
TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C803FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL |
TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C8F2FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE |
TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C8F37FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_RFO |
TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=C803FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA |
TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD |
TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD |
TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C817FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT |
TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS |
TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD |
TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD |
TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C817FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR |
TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C81786H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL |
TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C816FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM |
TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C8178AH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE |
TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C8177EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO |
TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO |
TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO |
TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT |
TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS |
TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=C8F3FFH Counter=0 |
| UNC_IIO_CLOCKTICKS |
Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz) |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS_FREERUN |
Free running counter that increments for integrated IO (IIO) traffic controller clockticks |
EventSel=00H UMask=00H Counter=0 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS |
PCIe Completion Buffer Inserts of completions with data : Part 0-7 |
EventSel=C2H UMask=03H FCMask=04H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0 |
PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C2H UMask=03H FCMask=04H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1 |
PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 |
EventSel=C2H UMask=03H FCMask=04H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2 |
PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 |
EventSel=C2H UMask=03H FCMask=04H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3 |
PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 |
EventSel=C2H UMask=03H FCMask=04H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4 |
PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 |
EventSel=C2H UMask=03H FCMask=04H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5 |
PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 |
EventSel=C2H UMask=03H FCMask=04H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6 |
PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 |
EventSel=C2H UMask=03H FCMask=04H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7 |
PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 |
EventSel=C2H UMask=03H FCMask=04H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS |
PCIe Completion Buffer Occupancy : Part 0-7 |
EventSel=D5H UMask=FFH FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0 |
PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=D5H UMask=01H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1 |
PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 |
EventSel=D5H UMask=02H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2 |
PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 |
EventSel=D5H UMask=04H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3 |
PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 |
EventSel=D5H UMask=08H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4 |
PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 |
EventSel=D5H UMask=10H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5 |
PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 |
EventSel=D5H UMask=20H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6 |
PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 |
EventSel=D5H UMask=40H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7 |
PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 |
EventSel=D5H UMask=80H FCMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=04H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=04H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=C0H UMask=04H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=04H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=C0H UMask=04H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=C0H UMask=04H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=C0H UMask=04H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7 |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=C0H UMask=04H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=01H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=01H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=C0H UMask=01H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=01H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=C0H UMask=01H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=C0H UMask=01H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=C0H UMask=01H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=C0H UMask=01H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=80H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=80H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=83H UMask=80H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=80H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=83H UMask=80H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=83H UMask=80H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=83H UMask=80H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=83H UMask=80H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=04H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=04H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=83H UMask=04H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=04H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=83H UMask=04H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=83H UMask=04H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=83H UMask=04H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=83H UMask=04H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=01H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=01H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=83H UMask=01H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=01H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=83H UMask=01H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=83H UMask=01H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=83H UMask=01H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=83H UMask=01H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL |
Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. |
EventSel=85H UMask=01H FCMask=07H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=C1H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=C1H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=C1H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=C1H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=C1H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=C1H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=C1H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=C1H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=C1H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=C1H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=80H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=80H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=84H UMask=80H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=80H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=84H UMask=80H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=84H UMask=80H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=84H UMask=80H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=84H UMask=80H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=84H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=84H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=84H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=84H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=84H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=84H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=84H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=84H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=84H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=84H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_M_ACT_COUNT.ALL |
DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. |
EventSel=01H UMask=0BH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.ALL |
Counts the total number of DRAM CAS commands issued on this channel. |
EventSel=04H UMask=3FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD |
Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills. |
EventSel=04H UMask=0FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR |
Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel. |
EventSel=04H UMask=30H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS |
DRAM Clockticks |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.HIGH |
Number of DRAM Refreshes Issued : Counts the number of refreshes issued. |
EventSel=45H UMask=04H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.OPPORTUNISTIC |
Number of DRAM Refreshes Issued : Counts the number of refreshes issued. |
EventSel=45H UMask=01H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.PANIC |
Number of DRAM Refreshes Issued : Counts the number of refreshes issued. |
EventSel=45H UMask=02H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.ALL |
PMM Commands : All : Counts all commands issued to PMM |
EventSel=EAH UMask=01H |
| UNC_M_PMM_CMD1.RD |
PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ |
EventSel=EAH UMask=02H |
| UNC_M_PMM_CMD1.UFILL_RD |
PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM |
EventSel=EAH UMask=08H |
| UNC_M_PMM_CMD1.WR |
PMM Commands : Writes : Counts write commands issued to PMM |
EventSel=EAH UMask=04H |
| UNC_M_PMM_RPQ_INSERTS |
PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests. |
EventSel=E3H UMask=00H |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL |
PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue. |
EventSel=E0H UMask=01H |
| UNC_M_PMM_WPQ_INSERTS |
PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue. |
EventSel=E7H UMask=00H |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL |
PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. |
EventSel=E4H UMask=01H |
| UNC_M_PRE_COUNT.ALL |
DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. |
EventSel=02H UMask=1CH Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT |
DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table |
EventSel=02H UMask=10H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.RD |
DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler |
EventSel=02H UMask=04H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.WR |
DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler |
EventSel=02H UMask=08H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH0 |
Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. |
EventSel=10H UMask=01H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH1 |
Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. |
EventSel=10H UMask=02H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH0 |
Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. |
EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH1 |
Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. |
EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_M_TAGCHK.HIT |
2LM Tag Check : Hit in Near Memory Cache |
EventSel=D3H UMask=01H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_CLEAN |
2LM Tag Check : Miss, no data in this line |
EventSel=D3H UMask=02H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_DIRTY |
2LM Tag Check : Miss, existing data may be evicted to Far Memory |
EventSel=D3H UMask=04H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_RD_HIT |
2LM Tag Check : Read Hit in Near Memory Cache |
EventSel=D3H UMask=08H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_WR_HIT |
2LM Tag Check : Write Hit in Near Memory Cache |
EventSel=D3H UMask=10H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH0 |
Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. |
EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH1 |
Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. |
EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH0 |
Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. |
EventSel=82H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH1 |
Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. |
EventSel=83H UMask=00H Counter=0,1,2,3 |
| UNC_I_CACHE_TOTAL_OCCUPANCY.MEM |
Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy. |
EventSel=0FH UMask=04H Counter=0,1 |
| UNC_I_CLOCKTICKS |
Clockticks of the IO coherency tracker (IRP) |
EventSel=01H UMask=00H Counter=0,1 |
| UNC_I_COHERENT_OPS.PCITOM |
PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache. |
EventSel=10H UMask=10H Counter=0,1 |
| UNC_I_COHERENT_OPS.WBMTOI |
Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP |
EventSel=10H UMask=40H Counter=0,1 |
| UNC_I_FAF_FULL |
FAF RF full |
EventSel=17H UMask=00H Counter=0,1 |
| UNC_I_FAF_INSERTS |
Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP. |
EventSel=18H UMask=00H Counter=0,1 |
| UNC_I_FAF_OCCUPANCY |
Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP. |
EventSel=19H UMask=00H Counter=0,1 |
| UNC_I_FAF_TRANSACTIONS |
FAF allocation -- sent to ADQ |
EventSel=16H UMask=00H Counter=0,1 |
| UNC_I_IRP_ALL.INBOUND_INSERTS |
: All Inserts Inbound (p2p + faf + cset) |
EventSel=20H UMask=01H Counter=0,1 |
| UNC_I_MISC1.LOST_FWD |
Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed |
EventSel=1FH UMask=10H Counter=0,1 |
| UNC_I_SNOOP_RESP.ALL_HIT_M |
Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache |
EventSel=12H UMask=78H Counter=0,1 |
| UNC_I_TRANSACTIONS.WR_PREF |
Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. |
EventSel=11H UMask=08H Counter=0,1 |
| UNC_M2M_CLOCKTICKS |
Clockticks of the mesh to memory (M2M) |
EventSel=00H UMask=00H |
| UNC_M2M_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_M2M_DIRECTORY_LOOKUP.ANY |
Multi-socket cacheline Directory Lookups : Found in any state |
EventSel=2DH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_A |
Multi-socket cacheline Directory Lookups : Found in A state |
EventSel=2DH UMask=08H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_I |
Multi-socket cacheline Directory Lookups : Found in I state |
EventSel=2DH UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_S |
Multi-socket cacheline Directory Lookups : Found in S state |
EventSel=2DH UMask=04H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.ANY |
Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode. |
EventSel=2EH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.TO_PMM |
M2M Reads Issued to iMC : PMM - All Channels |
EventSel=37H UMask=20H UMaskExt=07H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.TO_PMM |
M2M Writes Issued to iMC : PMM - All Channels |
EventSel=38H UMask=80H UMaskExt=1CH Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN |
Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs). |
EventSel=2CH UMask=01H |
| UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY |
Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs). |
EventSel=2CH UMask=02H |
| UNC_M2P_CLOCKTICKS |
Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2P_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H |
| UNC_M3UPI_CLOCKTICKS |
Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS |
Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time. |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_CLOCKTICKS |
Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the "GT/s" speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_L1_POWER_CYCLES |
Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode. |
EventSel=21H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_DATA |
Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=03H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_NULL |
Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=03H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.NON_DATA |
Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=03H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_DATA |
Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=02H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_NULL |
Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=02H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.NON_DATA |
Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=02H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL0P_POWER_CYCLES |
Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. |
EventSel=27H UMask=00H Counter=0,1,2,3 |