| UNC_B2CMI_CLOCKTICKS |
Clockticks of the mesh to memory (B2CMI) |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_DIRECT2CORE_TAKEN |
Counts the number of times B2CMI egress did D2C (direct to core) |
EventSel=16H UMask=01H Counter=0,1,2,3 |
| UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE |
Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn |
EventSel=18H UMask=01H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_READS.ALL |
Counts any read |
EventSel=24H UMask=04H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_READS.NORMAL |
Counts normal reads issue to CMI |
EventSel=24H UMask=01H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.ALL |
All Writes - All Channels |
EventSel=25H UMask=10H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.FULL |
Full Non-ISOCH - All Channels |
EventSel=25H UMask=01H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.PARTIAL |
Partial Non-ISOCH - All Channels |
EventSel=25H UMask=02H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH |
Prefetch CAM Inserts : XPT - All Channels |
EventSel=56H UMask=01H Counter=0,1,2,3 |
| UNC_B2CMI_TRACKER_INSERTS.CH0 |
Tracker Inserts : Channel 0 |
EventSel=32H UMask=04H UMaskExt=00000001H Counter=0,1,2,3 |
| UNC_B2CMI_TRACKER_OCCUPANCY.CH0 |
Tracker Occupancy : Channel 0 |
EventSel=33H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_CLOCKTICKS |
Clockticks of the uncore caching and home agent (CHA) |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_ANY |
Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering). |
EventSel=59H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ |
Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering). |
EventSel=59H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_TOR |
Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering). |
EventSel=59H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_MISC.RFO_HIT_S |
Cbo Misc : RFO HitS |
EventSel=39H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_OSB.RFO_HITS_SNP_BCAST |
OSB Snoop Broadcast : RFO HitS Snoop Broadcast |
EventSel=55H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE |
HA Read and Write Requests : InvalItoE |
EventSel=50H UMask=30H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL |
Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS |
HA Read and Write Requests : Reads |
EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL |
Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES |
HA Read and Write Requests : Writes |
EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL |
Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH |
TOR Inserts : CLFlushes issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT |
TOR Inserts : CLFlushOpts issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C8D7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD |
TOR Inserts : CRDs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD_PREF |
TOR Inserts; Code read prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C88FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT |
TOR Inserts : DRd_Opts issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C827FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C8A7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD |
TOR Inserts : CRds issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT |
TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C827FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C8A7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_ITOM |
TOR Inserts : ItoMs issued by iA Cores that Hit LLC |
EventSel=35H UMask=01H UMaskExt=00CC47FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE |
TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CCCFFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA |
TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CCD7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CCC7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO |
TOR Inserts : RFOs issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_ITOM |
TOR Inserts : ItoMs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CC47FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CD47FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE |
TOR Inserts : LLCPrefCode issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CCCFFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA |
TOR Inserts : LLCPrefData issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CCD7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CCC7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS |
TOR Inserts : All requests from iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD |
TOR Inserts : CRds issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL |
TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C80EFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF |
TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL |
TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C88EFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT |
TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C827FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL |
TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C826FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF |
TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C8A7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL |
TOR Inserts : Data read opt prefetch from local iA that missed the LLC targeting local memory |
EventSel=35H UMask=01H UMaskExt=00C8A6FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_ITOM |
TOR Inserts : ItoMs issued by iA Cores that Missed LLC |
EventSel=35H UMask=01H UMaskExt=00CC47FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE |
TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00CCCFFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA |
TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00CCD7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00CCC7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR |
TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C86E86H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR |
TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C86686H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C806FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL |
TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=35H UMask=01H UMaskExt=00C886FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF |
TOR Inserts : UCRdFs issued by iA Cores that Missed LLC |
EventSel=35H UMask=01H UMaskExt=00C877DEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCIL |
TOR Inserts : WCiLs issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR |
TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C86F86H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCILF |
TOR Inserts : WCiLF issued by iA Cores that Missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR |
TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC |
EventSel=35H UMask=01H UMaskExt=00C86786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WIL |
TOR Inserts : WiLs issued by iA Cores that Missed LLC |
EventSel=35H UMask=01H UMaskExt=00C87FDEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO |
TOR Inserts : RFOs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF |
TOR Inserts : RFO_Prefs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_SPECITOM |
TOR Inserts : SpecItoMs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CC57FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBEFTOE |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CC3FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBEFTOI |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CC37FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBMTOE |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CC2FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBMTOI |
TOR Inserts : WbMtoIs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00CC27FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBSTOI |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=01H UMaskExt=00CC67FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WCIL |
TOR Inserts : WCiLs issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C86FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WCILF |
TOR Inserts : WCiLF issued by iA Cores |
EventSel=35H UMask=01H UMaskExt=00C867FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_CLFLUSH |
TOR Inserts : CLFlushes issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=00C8C3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM |
TOR Inserts : ItoMs issued by IO Devices that Hit the LLC |
EventSel=35H UMask=04H UMaskExt=00CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=00CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=00C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_RFO |
TOR Inserts : RFOs issued by IO Devices that hit the LLC |
EventSel=35H UMask=04H UMaskExt=00C803FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM |
TOR Inserts : ItoMs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=00CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices |
EventSel=35H UMask=04H UMaskExt=00CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM |
TOR Inserts : ItoMs issued by IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=00CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=00CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=00C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_RFO |
TOR Inserts : RFOs issued by IO Devices that missed the LLC |
EventSel=35H UMask=04H UMaskExt=00C803FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=00C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_RFO |
TOR Inserts : RFOs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=00C803FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_WBMTOI |
TOR Inserts : WbMtoIs issued by IO Devices |
EventSel=35H UMask=04H UMaskExt=00CC23FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS |
TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) |
EventSel=35H UMask=02H UMaskExt=00C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH |
TOR Occupancy : CLFlushes issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C8C7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT |
TOR Occupancy : CLFlushOpts issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C8D7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD |
TOR Occupancy : CRDs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF |
TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C88FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT |
TOR Occupancy : DRd_Opts issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C827FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD |
TOR Occupancy : CRds issued by iA Cores that Hit the LLC |
EventSel=36H UMask=01H UMaskExt=00C80FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF |
TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=00C88FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM |
TOR Occupancy : ItoMs issued by iA Cores that Hit LLC |
EventSel=36H UMask=01H UMaskExt=00CC47FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE |
TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=00CCCFFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA |
TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=00CCD7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO |
TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC |
EventSel=36H UMask=01H UMaskExt=00CCC7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO |
TOR Occupancy : RFOs issued by iA Cores that Hit the LLC |
EventSel=36H UMask=01H UMaskExt=00C807FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF |
TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC |
EventSel=36H UMask=01H UMaskExt=00C887FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_ITOM |
TOR Occupancy : ItoMs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CC47FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CD47FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE |
TOR Occupancy : LLCPrefCode issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CCCFFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA |
TOR Occupancy : LLCPrefData issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CCD7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO |
TOR Occupancy : LLCPrefRFO issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CCC7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD |
TOR Occupancy : CRds issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL |
TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C80EFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF |
TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C88FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL |
TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C88EFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM |
TOR Occupancy : ItoMs issued by iA Cores that Missed LLC |
EventSel=36H UMask=01H UMaskExt=00CC47FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE |
TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC |
EventSel=36H UMask=01H UMaskExt=00CCCFFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA |
TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC |
EventSel=36H UMask=01H UMaskExt=00CCD7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO |
TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC |
EventSel=36H UMask=01H UMaskExt=00CCC7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR |
TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C86E86H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR |
TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C86686H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO |
TOR Occupancy : RFOs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL |
TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C806FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF |
TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C887FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL |
TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally |
EventSel=36H UMask=01H UMaskExt=00C886FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF |
TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC |
EventSel=36H UMask=01H UMaskExt=00C877DEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL |
TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C86FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR |
TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C86F86H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF |
TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C867FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR |
TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC |
EventSel=36H UMask=01H UMaskExt=00C86786H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL |
TOR Occupancy : WiLs issued by iA Cores that Missed LLC |
EventSel=36H UMask=01H UMaskExt=00C87FDEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO |
TOR Occupancy : RFOs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF |
TOR Occupancy : RFO_Prefs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C887FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM |
TOR Occupancy : SpecItoMs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CC57FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI |
TOR Occupancy : WbMtoIs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00CC27FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WCIL |
TOR Occupancy : WCiLs issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C86FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WCILF |
TOR Occupancy : WCiLF issued by iA Cores |
EventSel=36H UMask=01H UMaskExt=00C867FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH |
TOR Occupancy : CLFlushes issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=00C8C3FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM |
TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC |
EventSel=36H UMask=04H UMaskExt=00CC43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC |
EventSel=36H UMask=04H UMaskExt=00CD43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC |
EventSel=36H UMask=04H UMaskExt=00C8F3FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO |
TOR Occupancy : RFOs issued by IO Devices that hit the LLC |
EventSel=36H UMask=04H UMaskExt=00C803FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_ITOM |
TOR Occupancy : ItoMs issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=00CC43FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices |
EventSel=36H UMask=04H UMaskExt=00CD43FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM |
TOR Occupancy : ItoMs issued by IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=00CC43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=00CD43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=00C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO |
TOR Occupancy : RFOs issued by IO Devices that missed the LLC |
EventSel=36H UMask=04H UMaskExt=00C803FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=00C8F3FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_RFO |
TOR Occupancy : RFOs issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=00C803FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI |
TOR Occupancy : WbMtoIs issued by IO Devices |
EventSel=36H UMask=04H UMaskExt=00CC23FFH Counter=0 |
| UNC_CHACMS_CLOCKTICKS |
Clockticks for CMS units attached to CHA |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS |
IIO Clockticks |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS |
Data requested by the CPU : Core reporting completion of Card read from Core DRAM |
EventSel=C0H UMask=04H UMaskExt=00070FF0H FCMask=07H PortMask=0FFH Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070FF0H FCMask=07H PortMask=0FFH Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 |
Data requested by the CPU : Core writing to Cards MMIO space |
EventSel=C0H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 |
Four byte data request of the CPU : Card reading from DRAM |
EventSel=83H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 |
Four byte data request of the CPU : Card writing to DRAM |
EventSel=83H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX_POSTED |
Posted requests sent by the integrated IO (IIO) controller to the Ubox, useful for counting message signaled interrupts (MSI). |
EventSel=8EH UMask=04H UMaskExt=00010FF0H FCMask=01H PortMask=0FFH Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space |
EventSel=C1H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space |
EventSel=C1H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 |
Number Transactions requested of the CPU : Card reading from DRAM |
EventSel=84H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 |
Number Transactions requested of the CPU : Card writing to DRAM |
EventSel=84H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=0,1 |
| UNC_M_ACT_COUNT.ALL |
DRAM Activate Count |
EventSel=02H UMask=F7H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.ALL |
CAS count for SubChannel 0, all CAS operations |
EventSel=05H UMask=FFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD |
CAS count for SubChannel 0, all reads |
EventSel=05H UMask=CFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD_REG |
CAS count for SubChannel 0 regular reads |
EventSel=05H UMask=C1H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL |
CAS count for SubChannel 0 underfill reads |
EventSel=05H UMask=C4H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.WR |
CAS count for SubChannel 0, all writes |
EventSel=05H UMask=F0H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.ALL |
CAS count for SubChannel 1, all CAS operations |
EventSel=06H UMask=FFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD |
CAS count for SubChannel 1, all reads |
EventSel=06H UMask=CFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD_REG |
CAS count for SubChannel 1 regular reads |
EventSel=06H UMask=C1H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL |
CAS count for SubChannel 1 underfill reads |
EventSel=06H UMask=C4H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.WR |
CAS count for SubChannel 1, all writes |
EventSel=06H UMask=F0H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS |
DRAM Clockticks |
EventSel=01H UMask=01H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.ALL |
DRAM Precharge commands. |
EventSel=03H UMask=FFH Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT |
DRAM Precharge commands. |
EventSel=03H UMask=F8H Counter=0,1,2,3 |
| UNC_M_RDB_OCCUPANCY_SCH0 |
Read buffer occupancy on subchannel 0 |
EventSel=1AH UMask=00H Counter=0,1,2,3 |
| UNC_M_RDB_OCCUPANCY_SCH1 |
Read buffer occupancy on subchannel 1 |
EventSel=1BH UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH0_PCH0 |
Read Pending Queue inserts for subchannel 0, pseudochannel 0 |
EventSel=10H UMask=10H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH0_PCH1 |
Read Pending Queue inserts for subchannel 0, pseudochannel 1 |
EventSel=10H UMask=20H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH1_PCH0 |
Read Pending Queue inserts for subchannel 1, pseudochannel 0 |
EventSel=10H UMask=40H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH1_PCH1 |
Read Pending Queue inserts for subchannel 1, pseudochannel 1 |
EventSel=10H UMask=80H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH0_PCH0 |
Read pending queue occupancy for subchannel 0, pseudochannel 0 |
EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH0_PCH1 |
Read pending queue occupancy for subchannel 0, pseudochannel 1 |
EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH1_PCH0 |
Read pending queue occupancy for subchannel 1, pseudochannel 0 |
EventSel=82H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH1_PCH1 |
Read pending queue occupancy for subchannel 1, pseudochannel 1 |
EventSel=83H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH0_PCH0 |
Write Pending Queue inserts for subchannel 0, pseudochannel 0 |
EventSel=22H UMask=10H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH0_PCH1 |
Write Pending Queue inserts for subchannel 0, pseudochannel 1 |
EventSel=22H UMask=20H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH1_PCH0 |
Write Pending Queue inserts for subchannel 1, pseudochannel 0 |
EventSel=22H UMask=40H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH1_PCH1 |
Write Pending Queue inserts for subchannel 1, pseudochannel 1 |
EventSel=22H UMask=80H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH0_PCH0 |
Write pending queue occupancy for subchannel 0, pseudochannel 0 |
EventSel=84H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH0_PCH1 |
Write pending queue occupancy for subchannel 0, pseudochannel 1 |
EventSel=85H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH1_PCH0 |
Write pending queue occupancy for subchannel 1, pseudochannel 0 |
EventSel=86H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH1_PCH1 |
Write pending queue occupancy for subchannel 1, pseudochannel 1 |
EventSel=87H UMask=00H Counter=0,1,2,3 |
| UNC_I_CLOCKTICKS |
IRP Clockticks |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_I_FAF_INSERTS |
Inbound read requests received by the IRP and inserted into the FAF queue |
EventSel=18H UMask=00H Counter=0,1,2,3 |
| UNC_I_TRANSACTIONS.WR_PREF |
Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. |
EventSel=11H UMask=08H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS |
PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_U_EVENT_MSG.MSI_RCVD |
Message Received : MSI : Message Signaled Interrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket Mode only) |
EventSel=42H UMask=02H Counter=0,1 |