| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0002H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0004H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0010H |
| OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0010H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0020H |
| OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0020H |
| OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0040H |
| OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0040H |
| OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0040H |
| OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0040H |
| OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0040H |
| OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM |
Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0400H |
| OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001003C0000H |
| OCR.UC_RD.L3_HIT.SNOOP_MISS |
Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002003C0000H |
| OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1004003C0000H |
| OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1008003C0000H |
| OCR.UC_RD.L3_HIT.SNOOP_HITM |
Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1010003C0000H |
| OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0044H |
| OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS |
Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0044H |
| OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0044H |
| OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0044H |
| OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM |
Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0044H |
| OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE |
Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=400000010000H |
| OCR.PARTIAL_STREAMING_WR.L3_MISS |
Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H |
| OCR.FULL_STREAMING_WR.ANY_RESPONSE |
Counts streaming stores which modify a full 64 byte cacheline that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800000010000H |
| OCR.FULL_STREAMING_WR.L3_MISS |
Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H |
| OCR.L1WB_M.ANY_RESPONSE |
Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000010000H |
| OCR.L1WB_M.L3_MISS |
Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H |
| OCR.L2WB_M.ANY_RESPONSE |
Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000000010000H |
| OCR.L2WB_M.L3_MISS |
Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H |
| OCR.ALL_CODE_RD.ANY_RESPONSE |
Counts all code reads that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10044H |
| OCR.ALL_CODE_RD.OUTSTANDING |
Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000044H |
| OCR.ALL_CODE_RD.DRAM |
Counts all code reads that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H |
| OCR.ALL_CODE_RD.L3_MISS |
Counts all code reads that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H |
| OCR.DEMAND_DATA_RD.ANY_RESPONSE |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_RD.OUTSTANDING |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H |
| OCR.DEMAND_DATA_RD.DRAM |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_DATA_RD.L3_MISS |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H |
| OCR.DEMAND_RFO.ANY_RESPONSE |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OCR.DEMAND_RFO.OUTSTANDING |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000002H |
| OCR.DEMAND_RFO.DRAM |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H |
| OCR.DEMAND_RFO.L3_MISS |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H |
| OCR.DEMAND_CODE_RD.ANY_RESPONSE |
Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OCR.DEMAND_CODE_RD.DRAM |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H |
| OCR.DEMAND_CODE_RD.L3_MISS |
Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H |
| OCR.COREWB_M.ANY_RESPONSE |
Counts modified writebacks from L1 cache and L2 cache that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3000000010000H |
| OCR.COREWB_M.OUTSTANDING |
Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8003000000000000H |
| OCR.COREWB_M.L3_MISS |
Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H |
| OCR.HWPF_L2_DATA_RD.ANY_RESPONSE |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H |
| OCR.HWPF_L2_DATA_RD.DRAM |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H |
| OCR.HWPF_L2_DATA_RD.L3_MISS |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H |
| OCR.HWPF_L2_RFO.ANY_RESPONSE |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H |
| OCR.HWPF_L2_RFO.OUTSTANDING |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000020H |
| OCR.HWPF_L2_RFO.DRAM |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H |
| OCR.HWPF_L2_RFO.L3_MISS |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H |
| OCR.HWPF_L2_CODE_RD.ANY_RESPONSE |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10040H |
| OCR.HWPF_L2_CODE_RD.OUTSTANDING |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000040H |
| OCR.HWPF_L2_CODE_RD.DRAM |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H |
| OCR.HWPF_L2_CODE_RD.L3_MISS |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H |
| OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE |
Counts L1 data cache hardware prefetches and software prefetches (except PREFETCHW and PFRFO) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H |
| OCR.STREAMING_WR.ANY_RESPONSE |
Counts streaming stores that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OCR.STREAMING_WR.L3_MISS |
Counts streaming stores that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H |
| OCR.OTHER.ANY_RESPONSE |
Counts miscellaneous requests, such as I/O accesses, that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H |
| OCR.OTHER.L3_MISS |
Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H |
| OCR.UC_RD.ANY_RESPONSE |
Counts uncached memory reads that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100000010000H |
| OCR.UC_RD.OUTSTANDING |
Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000100000000000H |
| OCR.UC_RD.DRAM |
Counts uncached memory reads that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H |
| OCR.UC_RD.L3_MISS |
Counts uncached memory reads that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H |
| OCR.UC_WR.ANY_RESPONSE |
Counts uncached memory writes that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000010000H |
| OCR.UC_WR.L3_MISS |
Counts uncached memory writes that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.DRAM |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H |
| OCR.DEMAND_DATA_RD.LOCAL_DRAM |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_RFO.LOCAL_DRAM |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H |
| OCR.DEMAND_CODE_RD.LOCAL_DRAM |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H |
| OCR.HWPF_L2_DATA_RD.LOCAL_DRAM |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H |
| OCR.HWPF_L2_RFO.LOCAL_DRAM |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H |
| OCR.HWPF_L2_CODE_RD.LOCAL_DRAM |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H |
| OCR.UC_RD.LOCAL_DRAM |
Counts uncached memory reads that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H |
| OCR.ALL_CODE_RD.LOCAL_DRAM |
Counts all code reads that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H |
| OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H |
| OCR.DEMAND_DATA_RD.L3_MISS_LOCAL |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H |
| OCR.DEMAND_RFO.L3_MISS_LOCAL |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H |
| OCR.DEMAND_CODE_RD.L3_MISS_LOCAL |
Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H |
| OCR.COREWB_M.L3_MISS_LOCAL |
Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H |
| OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H |
| OCR.HWPF_L2_RFO.L3_MISS_LOCAL |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H |
| OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H |
| OCR.STREAMING_WR.L3_MISS_LOCAL |
Counts streaming stores that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H |
| OCR.OTHER.L3_MISS_LOCAL |
Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H |
| OCR.UC_RD.L3_MISS_LOCAL |
Counts uncached memory reads that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H |
| OCR.UC_WR.L3_MISS_LOCAL |
Counts uncached memory writes that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H |
| OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL |
Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H |
| OCR.FULL_STREAMING_WR.L3_MISS_LOCAL |
Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H |
| OCR.L1WB_M.L3_MISS_LOCAL |
Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H |
| OCR.L2WB_M.L3_MISS_LOCAL |
Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H |
| OCR.ALL_CODE_RD.L3_MISS_LOCAL |
Counts all code reads that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H |
| OCR.PREFETCHES.ANY_RESPONSE |
Counts all hardware and software prefetches that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10470H |
| OCR.PREFETCHES.L3_MISS |
Counts all hardware and software prefetches that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000470H |
| OCR.READS_TO_CORE.ANY_RESPONSE |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10477H |
| OCR.READS_TO_CORE.OUTSTANDING |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000477H |
| OCR.READS_TO_CORE.DRAM |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H |
| OCR.READS_TO_CORE.L3_MISS |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H |
| OCR.READS_TO_CORE.LOCAL_DRAM |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H |
| OCR.READS_TO_CORE.L3_MISS_LOCAL |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0477H |
| OCR.DEMAND_DATA_RD.L3_HIT |
This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H |
| OCR.DEMAND_RFO.L3_HIT |
Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0004H |
| OCR.COREWB_M.L3_HIT |
Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3001F803C0000H |
| OCR.HWPF_L2_DATA_RD.L3_HIT |
Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0010H |
| OCR.HWPF_L2_RFO.L3_HIT |
Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0020H |
| OCR.HWPF_L2_CODE_RD.L3_HIT |
Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0040H |
| OCR.STREAMING_WR.L3_HIT |
Counts streaming stores that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0800H |
| OCR.UC_RD.L3_HIT |
Counts uncached memory reads that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101F803C0000H |
| OCR.UC_WR.L3_HIT |
Counts uncached memory writes that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=201F803C0000H |
| OCR.PARTIAL_STREAMING_WR.L3_HIT |
Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=401F803C0000H |
| OCR.FULL_STREAMING_WR.L3_HIT |
Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=801F803C0000H |
| OCR.L1WB_M.L3_HIT |
Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001F803C0000H |
| OCR.L2WB_M.L3_HIT |
Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2001F803C0000H |
| OCR.ALL_CODE_RD.L3_HIT |
Counts all code reads that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0044H |
| OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT |
Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H |
| OCR.READS_TO_CORE.L3_HIT |
Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0477H |