| INST_RETIRED.ANY |
Instructions retired from execution. |
IA32_FIXED_CTR0 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD |
Core cycles when the thread is not in halt state. |
IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD_ANY |
Core cycles when at least one thread on the physical core is not in halt state. |
IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.REF_TSC |
Reference cycles when the core is not in halt state. |
IA32_FIXED_CTR2 Architectural, Fixed |
| BR_INST_RETIRED.ALL_BRANCHES |
Branch instructions at retirement. |
EventSel=C4H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| BR_MISP_RETIRED.ALL_BRANCHES |
Mispredicted branch instructions at retirement. |
EventSel=C5H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_THREAD_UNHALTED.REF_XCLK |
Increments at the frequency of XCLK (100 MHz) when not halted. |
EventSel=3CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY |
Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) |
EventSel=3CH UMask=01H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_UNHALTED.REF_XCLK |
Reference cycles when the thread is unhalted. (counts at 100 MHz rate) |
EventSel=3CH UMask=01H CMask=0 Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.REF_XCLK_ANY |
Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) |
EventSel=3CH UMask=01H AnyThread=1 CMask=0 Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.THREAD_P |
Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. |
EventSel=3CH UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_UNHALTED.THREAD_P_ANY |
Core cycles when at least one thread on the physical core is not in halt state. |
EventSel=3CH UMask=00H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| INST_RETIRED.ANY_P |
Number of instructions at retirement. |
EventSel=C0H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| LONGEST_LAT_CACHE.MISS |
This event counts each cache miss condition for references to the last level cache. |
EventSel=2EH UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| LONGEST_LAT_CACHE.REFERENCE |
This event counts requests originating from the core that reference a cache line in the last level cache. |
EventSel=2EH UMask=4FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| ARITH.FPU_DIV |
Divide operations executed. |
EventSel=14H UMask=04H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ARITH.FPU_DIV_ACTIVE |
Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. |
EventSel=14H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BACLEARS.ANY |
Number of front end re-steers due to BPU misprediction. |
EventSel=E6H UMask=1FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_BRANCHES |
Counts all near executed branches (not necessarily retired). |
EventSel=88H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_CONDITIONAL |
Speculative and retired macro-conditional branches. |
EventSel=88H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_DIRECT_JMP |
Speculative and retired macro-unconditional branches excluding calls and indirects. |
EventSel=88H UMask=C2H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_DIRECT_NEAR_CALL |
Speculative and retired direct near calls. |
EventSel=88H UMask=D0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET |
Speculative and retired indirect branches excluding calls and returns. |
EventSel=88H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN |
Speculative and retired indirect return branches. |
EventSel=88H UMask=C8H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.NONTAKEN_CONDITIONAL |
Not taken macro-conditional branches. |
EventSel=88H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_CONDITIONAL |
Taken speculative and retired macro-conditional branches. |
EventSel=88H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_DIRECT_JUMP |
Taken speculative and retired macro-conditional branch instructions excluding calls and indirects. |
EventSel=88H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL |
Taken speculative and retired direct near calls. |
EventSel=88H UMask=90H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET |
Taken speculative and retired indirect branches excluding calls and returns. |
EventSel=88H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL |
Taken speculative and retired indirect calls. |
EventSel=88H UMask=A0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN |
Taken speculative and retired indirect branches with return mnemonic. |
EventSel=88H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_RETIRED.ALL_BRANCHES_PS |
All (macro) branch instructions retired. |
EventSel=C4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL |
Counts the number of conditional branch instructions retired. |
EventSel=C4H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL_PS |
Conditional branch instructions retired. |
EventSel=C4H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.FAR_BRANCH |
Number of far branches retired. |
EventSel=C4H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL |
Direct and indirect near call instructions retired. |
EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_PS |
Direct and indirect near call instructions retired. |
EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3 |
Direct and indirect macro near call instructions retired (captured in ring 3). |
EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3_PS |
Direct and indirect macro near call instructions retired (captured in ring 3). |
EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_RETURN |
Counts the number of near return instructions retired. |
EventSel=C4H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_RETURN_PS |
Return instructions retired. |
EventSel=C4H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_TAKEN |
Number of near taken branches retired. |
EventSel=C4H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_TAKEN_PS |
Taken branch instructions retired. |
EventSel=C4H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NOT_TAKEN |
Counts the number of not taken branch instructions retired. |
EventSel=C4H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_EXEC.ALL_BRANCHES |
Counts all near executed branches (not necessarily retired). |
EventSel=89H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.ALL_CONDITIONAL |
Speculative and retired mispredicted macro conditional branches. |
EventSel=89H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET |
Mispredicted indirect branches excluding calls and returns. |
EventSel=89H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.INDIRECT |
Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded). |
EventSel=89H UMask=E4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.NONTAKEN_CONDITIONAL |
Not taken speculative and retired mispredicted macro conditional branches. |
EventSel=89H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_CONDITIONAL |
Taken speculative and retired mispredicted macro conditional branches. |
EventSel=89H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET |
Taken speculative and retired mispredicted indirect branches excluding calls and returns. |
EventSel=89H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL |
Taken speculative and retired mispredicted indirect calls. |
EventSel=89H UMask=A0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_RETURN_NEAR |
Taken speculative and retired mispredicted indirect branches with return mnemonic. |
EventSel=89H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_RETIRED.ALL_BRANCHES_PS |
Mispredicted macro branch instructions retired. |
EventSel=C5H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL |
Mispredicted conditional branch instructions retired. |
EventSel=C5H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL_PS |
Mispredicted conditional branch instructions retired. |
EventSel=C5H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_TAKEN |
Mispredicted taken branch instructions retired. |
EventSel=C5H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_TAKEN_PS |
number of near branch instructions retired that were mispredicted and taken. |
EventSel=C5H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| CPL_CYCLES.RING0 |
Unhalted core cycles when the thread is in ring 0. |
EventSel=5CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPL_CYCLES.RING0_TRANS |
Number of intervals between processor halts while thread is in ring 0. |
EventSel=5CH UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPL_CYCLES.RING123 |
Unhalted core cycles when the thread is not in ring 0. |
EventSel=5CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE |
Count XClk pulses when this thread is unhalted and the other is halted. |
EventSel=3CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE |
Count XClk pulses when this thread is unhalted and the other thread is halted. |
EventSel=3CH UMask=02H CMask=0 Counter=0,1,2,3 |
| CYCLE_ACTIVITY.CYCLES_L1D_MISS |
Cycles while L1 cache miss demand load is outstanding. |
EventSel=A3H UMask=08H CMask=08H Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.CYCLES_L1D_PENDING |
Cycles with pending L1 cache miss loads. Set AnyThread to count per core. |
EventSel=A3H UMask=08H CMask=08H Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.CYCLES_L2_MISS |
Cycles while L2 cache miss load* is outstanding. |
EventSel=A3H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.CYCLES_L2_PENDING |
Cycles with pending L2 miss loads. Set AnyThread to count per core. |
EventSel=A3H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.CYCLES_LDM_PENDING |
Cycles with pending memory loads. Set AnyThread to count per core. |
EventSel=A3H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.CYCLES_MEM_ANY |
Cycles while memory subsystem has an outstanding load. |
EventSel=A3H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.CYCLES_NO_EXECUTE |
Total execution stalls. |
EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_L1D_MISS |
Execution stalls while L1 cache miss demand load is outstanding. |
EventSel=A3H UMask=0CH CMask=0CH Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.STALLS_L1D_PENDING |
Execution stalls due to L1 data cache miss loads. Set Cmask=0CH. |
EventSel=A3H UMask=0CH CMask=0CH Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.STALLS_L2_MISS |
Execution stalls while L2 cache miss load* is outstanding. |
EventSel=A3H UMask=05H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_L2_PENDING |
Number of loads missed L2. |
EventSel=A3H UMask=05H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_LDM_PENDING |
Execution stalls due to memory subsystem. |
EventSel=A3H UMask=06H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_MEM_ANY |
Execution stalls while memory subsystem has an outstanding load. |
EventSel=A3H UMask=06H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_TOTAL |
Total execution stalls. |
EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| DSB_FILL.EXCEED_DSB_LINES |
DSB Fill encountered > 3 DSB lines. |
EventSel=ACH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DSB2MITE_SWITCHES.COUNT |
Number of DSB to MITE switches. |
EventSel=ABH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DSB2MITE_SWITCHES.PENALTY_CYCLES |
Cycles DSB to MITE switches caused delay. |
EventSel=ABH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED |
Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size. |
EventSel=08H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION |
Demand load cycles page miss handler (PMH) is busy with this walk. |
EventSel=08H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED |
Page walk for a large page completed for Demand load. |
EventSel=08H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK |
Misses in all TLB levels that cause a page walk of any page size from demand loads. |
EventSel=08H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.STLB_HIT |
Counts load operations that missed 1st level DTLB but hit the 2nd level. |
EventSel=5FH UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_COMPLETED |
Misses in all TLB levels that caused page walk completed of any size by demand loads. |
EventSel=08H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_DURATION |
Cycle PMH is busy with a walk due to demand loads. |
EventSel=08H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.MISS_CAUSES_A_WALK |
Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G). |
EventSel=49H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.STLB_HIT |
Store operations that miss the first TLB level but hit the second and do not cause page walks. |
EventSel=49H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_COMPLETED |
Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). |
EventSel=49H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_DURATION |
Cycles PMH is busy with this walk. |
EventSel=49H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| EPT.WALK_CYCLES |
Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. |
EventSel=4FH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_ASSIST.ANY |
Cycles with any input/output SSE* or FP assists. |
EventSel=CAH UMask=1EH CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.SIMD_INPUT |
Number of SIMD FP assists due to input values. |
EventSel=CAH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.SIMD_OUTPUT |
Number of SIMD FP assists due to output values. |
EventSel=CAH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.X87_INPUT |
Number of X87 FP assists due to input values. |
EventSel=CAH UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.X87_OUTPUT |
Number of X87 FP assists due to output values. |
EventSel=CAH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE |
Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle. |
EventSel=10H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_COMP_OPS_EXE.SSE_PACKED_SINGLE |
Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle. |
EventSel=10H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE |
Counts number of SSE* or AVX-128 double precision FP scalar uops executed. |
EventSel=10H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE |
Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle. |
EventSel=10H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_COMP_OPS_EXE.X87 |
Counts number of X87 uops executed. |
EventSel=10H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.HIT |
Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches. |
EventSel=80H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.IFETCH_STALL |
Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss. |
EventSel=80H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.MISSES |
Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. |
EventSel=80H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_DSB_CYCLES_4_UOPS |
Counts cycles DSB is delivered four uops. Set Cmask = 4. |
EventSel=79H UMask=18H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_DSB_CYCLES_ANY_UOPS |
Counts cycles DSB is delivered at least one uops. Set Cmask = 1. |
EventSel=79H UMask=18H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_MITE_CYCLES_4_UOPS |
Counts cycles MITE is delivered four uops. Set Cmask = 4. |
EventSel=79H UMask=24H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_MITE_CYCLES_ANY_UOPS |
Counts cycles MITE is delivered at least one uops. Set Cmask = 1. |
EventSel=79H UMask=24H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.DSB_CYCLES |
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path. |
EventSel=79H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.DSB_UOPS |
Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. |
EventSel=79H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.EMPTY |
Counts cycles the IDQ is empty. |
EventSel=79H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ.MITE_ALL_UOPS |
Number of uops delivered to IDQ from any path. |
EventSel=79H UMask=3CH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MITE_CYCLES |
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path. |
EventSel=79H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MITE_UOPS |
Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. |
EventSel=79H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_CYCLES |
Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy. |
EventSel=79H UMask=30H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_CYCLES |
Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy. |
EventSel=79H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_OCCUR |
Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy. |
EventSel=79H UMask=10H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_UOPS |
Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. |
EventSel=79H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_MITE_UOPS |
Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. |
EventSel=79H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_SWITCHES |
Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. |
EventSel=79H UMask=30H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_UOPS |
Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. |
EventSel=79H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ_UOPS_NOT_DELIVERED.CORE |
Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall. |
EventSel=9CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE |
Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled. |
EventSel=9CH UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK |
Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE. |
EventSel=9CH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE |
Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled. |
EventSel=9CH UMask=01H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE |
Cycles with less than 2 uops delivered by the front end. |
EventSel=9CH UMask=01H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE |
Cycles with less than 3 uops delivered by the front end. |
EventSel=9CH UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| ILD_STALL.IQ_FULL |
Stall cycles due to IQ is full. |
EventSel=87H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ILD_STALL.LCP |
Stalls caused by changing prefix length of the instruction. |
EventSel=87H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INST_RETIRED.PREC_DIST |
Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. |
EventSel=C0H UMask=01H Counter=1 CounterHTOff=1 PEBS:[Precise] |
| INT_MISC.RECOVERY_CYCLES |
Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) |
EventSel=0DH UMask=03H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INT_MISC.RECOVERY_CYCLES_ANY |
Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke). |
EventSel=0DH UMask=03H AnyThread=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INT_MISC.RECOVERY_STALLS_COUNT |
Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) |
EventSel=0DH UMask=03H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB.ITLB_FLUSH |
Counts the number of ITLB flushes, includes 4k/2M/4M pages. |
EventSel=AEH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED |
Completed page walks in ITLB due to STLB load misses for large pages. |
EventSel=85H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.MISS_CAUSES_A_WALK |
Misses in all ITLB levels that cause page walks. |
EventSel=85H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.STLB_HIT |
Number of cache load STLB hits. No page walk. |
EventSel=85H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_COMPLETED |
Misses in all ITLB levels that cause completed page walks. |
EventSel=85H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_DURATION |
Cycle PMH is busy with a walk. |
EventSel=85H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D.REPLACEMENT |
Counts the number of lines brought into the L1 data cache. |
EventSel=51H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D_PEND_MISS.FB_FULL |
Cycles a demand request was blocked due to Fill Buffers unavailability. |
EventSel=48H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D_PEND_MISS.PENDING |
Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences. |
EventSel=48H UMask=01H Counter=2 CounterHTOff=2 |
| L1D_PEND_MISS.PENDING_CYCLES |
Cycles with L1D load Misses outstanding. |
EventSel=48H UMask=01H CMask=01H Counter=2 CounterHTOff=2 |
| L1D_PEND_MISS.PENDING_CYCLES_ANY |
Cycles with L1D load Misses outstanding from any thread on physical core. |
EventSel=48H UMask=01H AnyThread=1 CMask=01H Counter=2 CounterHTOff=2 |
| L2_L1D_WB_RQSTS.ALL |
Not rejected writebacks from L1D to L2 cache lines in any state. |
EventSel=28H UMask=0FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_L1D_WB_RQSTS.HIT_E |
Not rejected writebacks from L1D to L2 cache lines in E state. |
EventSel=28H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_L1D_WB_RQSTS.HIT_M |
Not rejected writebacks from L1D to L2 cache lines in M state. |
EventSel=28H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_L1D_WB_RQSTS.MISS |
Not rejected writebacks that missed LLC. |
EventSel=28H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.ALL |
L2 cache lines filling L2. |
EventSel=F1H UMask=07H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.E |
L2 cache lines in E state filling L2. |
EventSel=F1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.I |
L2 cache lines in I state filling L2. |
EventSel=F1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.S |
L2 cache lines in S state filling L2. |
EventSel=F1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.DEMAND_CLEAN |
Clean L2 cache lines evicted by demand. |
EventSel=F2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.DEMAND_DIRTY |
Dirty L2 cache lines evicted by demand. |
EventSel=F2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.DIRTY_ALL |
Dirty L2 cache lines filling the L2. |
EventSel=F2H UMask=0AH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.PF_CLEAN |
Clean L2 cache lines evicted by the MLC prefetcher. |
EventSel=F2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.PF_DIRTY |
Dirty L2 cache lines evicted by the MLC prefetcher. |
EventSel=F2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_CODE_RD |
Counts all L2 code requests. |
EventSel=24H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_DEMAND_DATA_RD |
Counts any demand and L1 HW prefetch data load requests to L2. |
EventSel=24H UMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_PF |
Counts all L2 HW prefetcher requests. |
EventSel=24H UMask=C0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_RFO |
Counts all L2 store RFO requests. |
EventSel=24H UMask=0CH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.CODE_RD_HIT |
Number of instruction fetches that hit the L2 cache. |
EventSel=24H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.CODE_RD_MISS |
Number of instruction fetches that missed the L2 cache. |
EventSel=24H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.DEMAND_DATA_RD_HIT |
Demand Data Read requests that hit L2 cache. |
EventSel=24H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.PF_HIT |
Counts all L2 HW prefetcher requests that hit L2. |
EventSel=24H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.PF_MISS |
Counts all L2 HW prefetcher requests that missed L2. |
EventSel=24H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.RFO_HIT |
RFO requests that hit L2 cache. |
EventSel=24H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.RFO_MISS |
Counts the number of store RFO requests that miss the L2 cache. |
EventSel=24H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_STORE_LOCK_RQSTS.ALL |
RFOs that access cache lines in any state. |
EventSel=27H UMask=0FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_STORE_LOCK_RQSTS.HIT_M |
RFOs that hit cache lines in M state. |
EventSel=27H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_STORE_LOCK_RQSTS.MISS |
RFOs that miss cache lines. |
EventSel=27H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.ALL_PF |
Any MLC or LLC HW prefetch accessing L2, including rejects. |
EventSel=F0H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.ALL_REQUESTS |
Transactions accessing L2 pipe. |
EventSel=F0H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.CODE_RD |
L2 cache accesses when fetching instructions. |
EventSel=F0H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.DEMAND_DATA_RD |
Demand Data Read requests that access L2 cache. |
EventSel=F0H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L1D_WB |
L1D writebacks that access L2 cache. |
EventSel=F0H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L2_FILL |
L2 fill requests that access L2 cache. |
EventSel=F0H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L2_WB |
L2 writebacks that access L2 cache. |
EventSel=F0H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.RFO |
RFO requests that access L2 cache. |
EventSel=F0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS.NO_SR |
The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. |
EventSel=03H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS.STORE_FORWARD |
Loads blocked by overlapping with store buffer that cannot be forwarded. |
EventSel=03H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS_PARTIAL.ADDRESS_ALIAS |
False dependencies in MOB due to partial compare on address. |
EventSel=07H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOAD_HIT_PRE.HW_PF |
Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. |
EventSel=4CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOAD_HIT_PRE.SW_PF |
SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. |
EventSel=4CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOCK_CYCLES.CACHE_LOCK_DURATION |
Cycles in which the L1D is locked. |
EventSel=63H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION |
Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. |
EventSel=63H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.CYCLES_4_UOPS |
Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. |
EventSel=A8H UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.CYCLES_ACTIVE |
Cycles Uops delivered by the LSD, but didn't come from the decoder. |
EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.UOPS |
Number of Uops delivered by the LSD. |
EventSel=A8H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.COUNT |
Number of machine clears (nukes) of any type. |
EventSel=C3H UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.MASKMOV |
Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. |
EventSel=C3H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.MEMORY_ORDERING |
Counts the number of machine clears due to memory order conflicts. |
EventSel=C3H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.SMC |
Number of self-modifying-code machine clears detected. |
EventSel=C3H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT |
Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits. |
EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS |
Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. |
EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM |
Retired load uops whose data source was an on-package core cache with HitM responses. |
EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS |
Retired load uops which data sources were HitM responses from shared LLC. |
EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS |
Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed. |
EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS |
Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. |
EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE |
Retired load uops whose data source was LLC hit with no snoop required. |
EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE_PS |
Retired load uops which data sources were hits in LLC without snoops required. |
EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM |
Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded). |
EventSel=D3H UMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM |
Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded). |
EventSel=D3H UMask=0CH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD |
Data forwarded from remote cache. |
EventSel=D3H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM |
Remote cache HITM. |
EventSel=D3H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.HIT_LFB |
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. |
EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS |
Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. |
EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_HIT |
Retired load uops with L1 cache hits as data sources. |
EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_HIT_PS |
Retired load uops with L1 cache hits as data sources. |
EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_MISS |
Retired load uops whose data source followed an L1 miss. |
EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_MISS_PS |
Retired load uops which data sources following L1 data-cache miss. |
EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_HIT |
Retired load uops with L2 cache hits as data sources. |
EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_HIT_PS |
Retired load uops with L2 cache hits as data sources. |
EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_MISS |
Retired load uops that missed L2, excluding unknown sources. |
EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_MISS_PS |
Retired load uops with L2 cache misses as data sources. |
EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.LLC_HIT |
Retired load uops whose data source was LLC hit with no snoop required. |
EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS |
Retired load uops which data sources were data hits in LLC without snoops required. |
EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.LLC_MISS |
Retired load uops whose data source is LLC miss. |
EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS |
Miss in last-level (L3) cache. Excludes Unknown data-source. |
EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 |
Randomly selected loads with latency value being above 128. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 |
Randomly selected loads with latency value being above 16. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 |
Randomly selected loads with latency value being above 256. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 |
Randomly selected loads with latency value being above 32. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 |
Randomly selected loads with latency value being above 4. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 |
Randomly selected loads with latency value being above 512. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 |
Randomly selected loads with latency value being above 64. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 |
Randomly selected loads with latency value being above 8. |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.PRECISE_STORE |
Sample stores and collect precise store operation via PEBS record. PMC3 only. |
EventSel=CDH UMask=02H Counter=3 CounterHTOff=3 PEBS:[Precise, Latency] |
| MEM_UOPS_RETIRED.ALL_LOADS |
All retired load uops. |
EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.ALL_LOADS_PS |
All retired load uops. (Precise Event) |
EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.ALL_STORES |
All retired store uops. |
EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.ALL_STORES_PS |
All retired store uops. (Precise Event) |
EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.LOCK_LOADS |
Retired load uops with locked access. |
EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.LOCK_LOADS_PS |
Retired load uops with locked access. (Precise Event) |
EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_LOADS |
Retired load uops that split across a cacheline boundary. |
EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_LOADS_PS |
Retired load uops that split across a cacheline boundary. (Precise Event) |
EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_STORES |
Retired store uops that split across a cacheline boundary. |
EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_STORES_PS |
Retired store uops that split across a cacheline boundary. (Precise Event) |
EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS |
Retired load uops that miss the STLB. |
EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS |
Retired load uops that miss the STLB. (Precise Event) |
EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_STORES |
Retired store uops that miss the STLB. |
EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_STORES_PS |
Retired store uops that miss the STLB. (Precise Event) |
EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MISALIGN_MEM_REF.LOADS |
Speculative cache-line split load uops dispatched to L1D. |
EventSel=05H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MISALIGN_MEM_REF.STORES |
Speculative cache-line split Store-address uops dispatched to L1D. |
EventSel=05H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.INT_ELIMINATED |
Number of integer Move Elimination candidate uops that were eliminated. |
EventSel=58H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.INT_NOT_ELIMINATED |
Number of integer Move Elimination candidate uops that were not eliminated. |
EventSel=58H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.SIMD_ELIMINATED |
Number of SIMD Move Elimination candidate uops that were eliminated. |
EventSel=58H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.SIMD_NOT_ELIMINATED |
Number of SIMD Move Elimination candidate uops that were not eliminated. |
EventSel=58H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.ALL_DATA_RD |
Data read requests sent to uncore (demand and prefetch). |
EventSel=B0H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.ALL_REQUESTS |
Any memory transaction that reached the SQ. This includes requests initiated by the core, include all LLC prefetches, page walks, etc. |
EventSel=B0H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_CODE_RD |
Demand code read requests sent to uncore. |
EventSel=B0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_DATA_RD |
Demand data read requests sent to uncore. |
EventSel=B0H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_RFO |
Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. |
EventSel=B0H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_BUFFER.SQ_FULL |
Cases when offcore requests buffer cannot take more entries for core. |
EventSel=B2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD |
Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. |
EventSel=60H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD |
Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore. |
EventSel=60H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD |
Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle. |
EventSel=60H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD |
Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore. |
EventSel=60H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO |
Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle. |
EventSel=60H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD |
Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. |
EventSel=60H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD |
Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. |
EventSel=60H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 |
Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue. |
EventSel=60H UMask=01H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO |
Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. |
EventSel=60H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OTHER_ASSISTS.ANY_WB_ASSIST |
Number of times any microcode assist is invoked by HW upon uop writeback. |
EventSel=C1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| OTHER_ASSISTS.AVX_STORE |
Number of assists associated with 256-bit AVX store operations. |
EventSel=C1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| OTHER_ASSISTS.AVX_TO_SSE |
Number of transitions from AVX-256 to legacy SSE when penalty applicable. |
EventSel=C1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| OTHER_ASSISTS.SSE_TO_AVX |
Number of transitions from SSE to AVX-256 when penalty applicable. |
EventSel=C1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| RESOURCE_STALLS.ANY |
Cycles Allocation is stalled due to Resource Related reason. |
EventSel=A2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.ROB |
Cycles stalled due to re-order buffer full. |
EventSel=A2H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.RS |
Cycles stalled due to no eligible RS entry available. |
EventSel=A2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.SB |
Cycles stalled due to no store buffers available (not including draining form sync). |
EventSel=A2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ROB_MISC_EVENTS.LBR_INSERTS |
Count cases of saving new LBR records by hardware. |
EventSel=CCH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RS_EVENTS.EMPTY_CYCLES |
Cycles the RS is empty for the thread. |
EventSel=5EH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RS_EVENTS.EMPTY_END |
Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues. |
EventSel=5EH UMask=01H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| SIMD_FP_256.PACKED_DOUBLE |
Counts 256-bit packed double-precision floating-point instructions. |
EventSel=11H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| SIMD_FP_256.PACKED_SINGLE |
Counts 256-bit packed single-precision floating-point instructions. |
EventSel=11H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| SQ_MISC.SPLIT_LOCK |
Split locks in SQ |
EventSel=F4H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TLB_FLUSH.DTLB_THREAD |
DTLB flush attempts of the thread-specific entries. |
EventSel=BDH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TLB_FLUSH.STLB_ANY |
Count number of STLB flush attempts. |
EventSel=BDH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_0 |
Cycles which a Uop is dispatched on port 0. |
EventSel=A1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_0_CORE |
Cycles per core when uops are dispatched to port 0. |
EventSel=A1H UMask=01H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_1 |
Cycles which a Uop is dispatched on port 1. |
EventSel=A1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_1_CORE |
Cycles per core when uops are dispatched to port 1. |
EventSel=A1H UMask=02H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_2 |
Cycles which a Uop is dispatched on port 2. |
EventSel=A1H UMask=0CH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_2_CORE |
Uops dispatched to port 2, loads and stores per core (speculative and retired). |
EventSel=A1H UMask=0CH AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_3 |
Cycles which a Uop is dispatched on port 3. |
EventSel=A1H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_3_CORE |
Cycles per core when load or STA uops are dispatched to port 3. |
EventSel=A1H UMask=30H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_4 |
Cycles which a Uop is dispatched on port 4. |
EventSel=A1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_4_CORE |
Cycles per core when uops are dispatched to port 4. |
EventSel=A1H UMask=40H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_5 |
Cycles which a Uop is dispatched on port 5. |
EventSel=A1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_5_CORE |
Cycles per core when uops are dispatched to port 5. |
EventSel=A1H UMask=80H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE |
Counts total number of uops to be executed per-core each cycle. |
EventSel=B1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_1 |
Cycles at least 1 micro-op is executed from any thread on physical core. |
EventSel=B1H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_2 |
Cycles at least 2 micro-op is executed from any thread on physical core. |
EventSel=B1H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_3 |
Cycles at least 3 micro-op is executed from any thread on physical core. |
EventSel=B1H UMask=02H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_4 |
Cycles at least 4 micro-op is executed from any thread on physical core. |
EventSel=B1H UMask=02H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_NONE |
Cycles with no micro-ops executed from any thread on physical core. |
EventSel=B1H UMask=02H Invert=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC |
Cycles where at least 1 uop was executed per-thread. |
EventSel=B1H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC |
Cycles where at least 2 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC |
Cycles where at least 3 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC |
Cycles where at least 4 uops were executed per-thread. |
EventSel=B1H UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.STALL_CYCLES |
Counts number of cycles no uops were dispatched to be executed on this thread. |
EventSel=B1H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.THREAD |
Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. |
EventSel=B1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.ANY |
Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. |
EventSel=0EH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.CORE_STALL_CYCLES |
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads. |
EventSel=0EH UMask=01H AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_ISSUED.FLAGS_MERGE |
Number of flags-merge uops allocated. Such uops adds delay. |
EventSel=0EH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.SINGLE_MUL |
Number of multiply packed/scalar single precision uops allocated. |
EventSel=0EH UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.SLOW_LEA |
Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. |
EventSel=0EH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.STALL_CYCLES |
Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread. |
EventSel=0EH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_RETIRED.ALL |
Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. |
EventSel=C2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ALL_PS |
Retired uops. |
EventSel=C2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.CORE_STALL_CYCLES |
Cycles without actually retired uops. |
EventSel=C2H UMask=01H AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS |
Counts the number of retirement slots used each cycle. |
EventSel=C2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS_PS |
Retirement slots used. |
EventSel=C2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES |
Cycles without actually retired uops. |
EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES |
Cycles with less than 10 actually retired uops. |
EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |