| INST_RETIRED.ANY |
Fixed Counter: Counts the number of instructions retired. |
IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Architectural, Fixed, AtRetirement |
| CPU_CLK_UNHALTED.CORE |
Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD] |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.THREAD |
Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE] |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.REF_TSC |
Fixed Counter: Counts the number of unhalted reference clock cycles. |
IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| BR_INST_RETIRED.ALL_BRANCHES |
Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. Errata: null |
EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES |
Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. |
EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| CPU_CLK_UNHALTED.CORE_P |
Counts the number of unhalted core clock cycles |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| CPU_CLK_UNHALTED.REF_TSC_P |
Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. |
EventSel=3CH UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| INST_RETIRED.ANY_P |
Counts the number of instructions retired |
EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| LONGEST_LAT_CACHE.MISS |
Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| LONGEST_LAT_CACHE.REFERENCE |
Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| ARITH.DIV_ACTIVE |
Counts the number of cycles when any of the floating point or integer dividers are active. |
EventSel=CDH UMask=03H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_ACTIVE |
Counts the number of cycles when any of the floating point dividers are active. |
EventSel=CDH UMask=02H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.ANY |
Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. |
EventSel=E6H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BR_INST_RETIRED.COND |
Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. Errata: null |
EventSel=C4H UMask=7EH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN |
Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C4H UMask=FEH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH |
Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. Errata: null |
EventSel=C4H UMask=BFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT |
Counts the number of near indirect JMP and near indirect CALL branch instructions retired. Errata: null |
EventSel=C4H UMask=EBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT_CALL |
Counts the number of near indirect CALL branch instructions retired. Errata: null |
EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT_JMP |
Counts the number of near indirect JMP branch instructions retired. |
EventSel=C4H UMask=EFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL |
Counts the number of near CALL branch instructions retired. Errata: null |
EventSel=C4H UMask=F9H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN |
Counts the number of near RET branch instructions retired. |
EventSel=C4H UMask=F7H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN |
Counts the number of near taken branch instructions retired. Errata: null |
EventSel=C4H UMask=C0H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.REL_CALL |
Counts the number of near relative CALL branch instructions retired. |
EventSel=C4H UMask=FDH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.REL_JMP |
Counts the number of near relative JMP branch instructions retired. |
EventSel=C4H UMask=DFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND |
Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C5H UMask=7EH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN |
Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C5H UMask=FEH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT |
Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. |
EventSel=C5H UMask=EBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL |
Counts the number of mispredicted near indirect CALL branch instructions retired. |
EventSel=C5H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_JMP |
Counts the number of mispredicted near indirect JMP branch instructions retired. |
EventSel=C5H UMask=EFH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN |
Counts the number of mispredicted near taken branch instructions retired. |
EventSel=C5H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.RETURN |
Counts the number of mispredicted near RET branch instructions retired. |
EventSel=C5H UMask=F7H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| DL1.DIRTY_EVICTION |
Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back. |
EventSel=51H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB. |
EventSel=08H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to load DTLB misses. |
EventSel=08H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M |
Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. |
EventSel=08H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=08H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. |
EventSel=08H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB. |
EventSel=49H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to store DTLB misses to a 1G page. |
EventSel=49H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M |
Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. |
EventSel=49H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=49H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_PENDING |
Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. |
EventSel=49H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_FLOPS_RETIRED.ALL |
Counts the number of all types of floating point operations per uop with all default weighting |
EventSel=C8H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.128B_DP |
Counts the total number of floating point retired instructions. |
EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.128B_SP |
Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. |
EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.256B_DP |
Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. |
EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.32B_SP |
Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. |
EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.64B_DP |
Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. |
EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS |
Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss |
EventSel=C6H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| ICACHE.ACCESSES |
Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump. |
EventSel=80H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ICACHE.MISSES |
Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - |
EventSel=80H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.MISS_CAUSED_WALK |
Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs. |
EventSel=85H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.STLB_HIT |
Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB. |
EventSel=85H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=85H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED_2M_4M |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. |
EventSel=85H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. |
EventSel=85H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_PENDING |
Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks. |
EventSel=85H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_IN.E |
Counts the number of cache lines filled into the L2 cache that are in Exclusive state. Counts on a per core basis. |
EventSel=25H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_IN.F |
Counts the number of cache lines filled into the L2 cache that are in Forward state. Counts on a per core basis. |
EventSel=25H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_IN.M |
Counts the number of cache lines filled into the L2 cache that are in Modified state. Counts on a per core basis. |
EventSel=25H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_IN.S |
Counts the number of cache lines filled into the L2 cache that are in Shared state. Counts on a per core basis. |
EventSel=25H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_OUT.NON_SILENT |
Counts the number of L2 cache lines that are evicted due to an L2 cache fill. Increments on the core that brought the line in originally. |
EventSel=26H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_LINES_OUT.SILENT |
Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill. Increments on the core that brought the line in originally. |
EventSel=26H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.HIT |
Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles) |
EventSel=24H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.MISS |
Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles) |
EventSel=24H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| L2_REQUEST.REJECTS |
Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject – short and long rejects |
EventSel=24H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_BLOCKS.ADDRESS_ALIAS |
Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. |
EventSel=03H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_BLOCKS.DATA_UNKNOWN |
Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. |
EventSel=03H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_BLOCKS.STORE_FORWARD |
Counts the number of retired loads that are blocked because its address partially overlapped with an older store. |
EventSel=03H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_HEAD.ANY_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. |
EventSel=05H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.DTLB_MISS_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss. |
EventSel=05H UMask=90H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_BOUND_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. |
EventSel=05H UMask=F4H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_MISS_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss. |
EventSel=05H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.OTHER_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc. |
EventSel=05H UMask=C0H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.PGWALK_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk. |
EventSel=05H UMask=A0H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.ST_ADDR_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match. |
EventSel=05H UMask=84H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.DISAMBIGUATION |
Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. |
EventSel=C3H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.FP_ASSIST |
Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. |
EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING |
Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. |
EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.PAGE_FAULT |
Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. |
EventSel=C3H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SMC |
Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. |
EventSel=C3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.ALL |
Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss. |
EventSel=35H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.L2_HIT |
Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache. |
EventSel=35H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.LLC_HIT |
Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros. |
EventSel=35H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.LLC_MISS |
Counts the number of unhalted cycles when the core is stalled due to an ICACHE or ITLB miss which missed all the caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss. |
EventSel=35H UMask=78H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.ALL |
Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss. |
EventSel=34H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.L2_HIT |
Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache. |
EventSel=34H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_HIT |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. If the core has access to an L3 cache, an LLC hit refers to an L3 cache hit, otherwise it counts zeros. |
EventSel=34H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_MISS |
Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. If the core has access to an L3 cache, an LLC miss refers to an L3 cache miss, otherwise it is an L2 cache miss. |
EventSel=34H UMask=78H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.SBFULL |
Counts the number of unhalted cycles when the core is stalled to a store buffer full condition |
EventSel=34H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM |
Counts the number of load ops retired that miss the L3 cache and hit in DRAM |
EventSel=D3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_HIT |
Counts the number of load ops retired that hit the L1 data cache. |
EventSel=D1H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_MISS |
Counts the number of load ops retired that miss in the L1 data cache. |
EventSel=D1H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_HIT |
Counts the number of load ops retired that hit in the L2 cache. |
EventSel=D1H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_MISS |
Counts the number of load ops retired that miss in the L2 cache. |
EventSel=D1H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT |
Counts the number of load ops retired that hit in the L3 cache. |
EventSel=D1H UMask=1CH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.WCB_HIT |
Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate. |
EventSel=D1H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_SCHEDULER_BLOCK.ALL |
Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. |
EventSel=04H UMask=07H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.LD_BUF |
Counts the number of cycles that uops are blocked due to a load buffer full condition. |
EventSel=04H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.RSV |
Counts the number of cycles that uops are blocked due to an RSV full condition. |
EventSel=04H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.ST_BUF |
Counts the number of cycles that uops are blocked due to a store buffer full condition. |
EventSel=04H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_UOPS_RETIRED.ALL_LOADS |
Counts the number of load ops retired. |
EventSel=D0H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.ALL_STORES |
Counts the number of store ops retired. |
EventSel=D0H UMask=82H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024 |
Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128 |
Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16 |
Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048 |
Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256 |
Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32 |
Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4 |
Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512 |
Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64 |
Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8 |
Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOCK_LOADS |
Counts the number of load uops retired that performed one or more locks |
EventSel=D0H UMask=21H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT |
Counts the number of memory uops retired that were splits. |
EventSel=D0H UMask=43H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_LOADS |
Counts the number of retired split load uops. |
EventSel=D0H UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_STORES |
Counts the number of retired split store uops. |
EventSel=D0H UMask=42H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS |
Counts the number of memory uops retired that missed in the second level TLB. |
EventSel=D0H UMask=13H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS |
Counts the number of load uops retired that miss in the second Level TLB. |
EventSel=D0H UMask=11H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_STORES |
Counts the number of store uops retired that miss in the second level TLB. |
EventSel=D0H UMask=12H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.STORE_LATENCY |
Counts the number of stores uops retired. |
EventSel=D0H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISALIGN_MEM_REF.LOAD_PAGE_SPLIT |
Counts misaligned loads that are 4K page splits. |
EventSel=13H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISALIGN_MEM_REF.STORE_PAGE_SPLIT |
Counts misaligned stores that are 4K page splits. |
EventSel=13H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISC_RETIRED.LBR_INSERTS |
Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MS_DECODED.MS_BUSY |
Counts the number of cycles that the micro-sequencer is busy. |
EventSel=E7H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| SERIALIZATION.C01_MS_SCB |
Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. |
EventSel=75H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.ALL_P |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. |
EventSel=73H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.FASTNUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes |
EventSel=73H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. |
EventSel=73H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MISPREDICT |
Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict |
EventSel=73H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.NUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). |
EventSel=73H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALL_P |
Counts the number of retirement slots not consumed due to backend stalls |
EventSel=74H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS |
Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions |
EventSel=74H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block. |
EventSel=74H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) |
EventSel=74H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REGISTER |
Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST). |
EventSel=74H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REORDER_BUFFER |
Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full |
EventSel=74H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.SERIALIZATION |
Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb |
EventSel=74H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ALL_P |
Counts the number of retirement slots not consumed due to front end stalls |
EventSel=71H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_DETECT |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear |
EventSel=71H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_RESTEER |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear |
EventSel=71H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.CISC |
Counts the number of issue slots every cycle that were not delivered by the frontend due to ms |
EventSel=71H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.DECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall |
EventSel=71H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH |
Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. |
EventSel=71H UMask=8DH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_LATENCY |
Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. |
EventSel=71H UMask=72H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ICACHE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss |
EventSel=71H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ITLB_MISS |
Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss |
EventSel=71H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.OTHER |
Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall |
EventSel=71H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.PREDECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong |
EventSel=71H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_RETIRING.ALL_P |
Counts the number of consumed retirement slots. |
EventSel=72H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_ISSUED.ANY |
Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. |
EventSel=0EH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.ALL |
Counts the total number of uops retired. |
EventSel=C2H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.FPDIV |
Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). |
EventSel=C2H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.IDIV |
Counts the number of integer divide uops retired. |
EventSel=C2H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.MS |
Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. |
EventSel=C2H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.X87 |
Counts the number of x87 uops retired, includes those in ms flows |
EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.IND_CALL |
This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL Errata: null |
EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| FP_FLOPS_RETIRED.DP |
This event is deprecated. |
EventSel=C8H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| FP_FLOPS_RETIRED.SP |
This event is deprecated. |
EventSel=C8H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| MACHINE_CLEARS.SLOW |
This event is deprecated. |
EventSel=C3H UMask=6FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative, Deprecated |