| UNC_CHA_CLOCKTICKS |
Counts clockticks of the clock controlling the uncore caching and home agent (CHA). |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_CORE_SNP.CORE_GTONE |
Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s). |
EventSel=33H UMask=42H Counter=0,1,2,3 |
| UNC_CHA_CORE_SNP.EVICT_GTONE |
Counts the number of transactions that trigger a configurable number of cross snoops. Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set. For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them. However, if only 1 CV bit is set the core my have modified the data. If the transaction was an RFO, it would need to invalidate the lines. This event can be filtered based on who triggered the initial snoop(s). |
EventSel=33H UMask=82H Counter=0,1,2,3 |
| UNC_CHA_DIR_LOOKUP.NO_SNP |
Counts transactions that looked into the multi-socket cacheline Directory state, and therefore did not send a snoop because the Directory indicated it was not needed |
EventSel=53H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_DIR_LOOKUP.SNP |
Counts transactions that looked into the multi-socket cacheline Directory state, and sent one or more snoops, because the Directory indicated it was needed |
EventSel=53H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_DIR_UPDATE.HA |
Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_DIR_UPDATE.TOR |
Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_FAST_ASSERTED.HORZ |
Counts the number of cycles either the local or incoming distress signals are asserted. Incoming distress includes up, dn and across. |
EventSel=A5H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_HITME_HIT.EX_RDS |
Counts read requests from a remote socket which hit in the HitME cache (used to cache the multi-socket Directory state) to a line in the E(Exclusive) state. This includes the following read opcodes (RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv) |
EventSel=5FH UMask=01H Counter=0,1,2,3 |
| UNC_CHA_IMC_READS_COUNT.NORMAL |
Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA. |
EventSel=59H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_IMC_WRITES_COUNT.FULL |
Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels. |
EventSel=5BH UMask=01H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.TOTAL_E |
Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. |
EventSel=37H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.TOTAL_F |
Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. |
EventSel=37H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.TOTAL_M |
Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. |
EventSel=37H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.TOTAL_S |
Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. |
EventSel=37H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_MISC.RFO_HIT_S |
Counts when a RFO (the Read for Ownership issued before a write) request hit a cacheline in the S (Shared) state. |
EventSel=39H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL |
Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_REMOTE |
Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=20H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS |
Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) . |
EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL |
Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_REMOTE |
Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES |
Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL |
Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_REMOTE |
Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc). |
EventSel=50H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_RxC_INSERTS.IRQ |
Counts number of allocations per cycle into the specified Ingress queue. |
EventSel=13H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH |
Ingress (from CMS) Request Queue Rejects; PhyAddr Match |
EventSel=19H UMask=80H Counter=0,1,2,3 |
| UNC_CHA_RxC_OCCUPANCY.IRQ |
Counts number of entries in the specified Ingress queue in each cycle. |
EventSel=11H UMask=01H Counter=0 |
| UNC_CHA_SF_EVICTION.E_STATE |
Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores’ cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core’s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=02H Counter=0,1,2,3 |
| UNC_CHA_SF_EVICTION.M_STATE |
Counts snoop filter capacity evictions for entries tracking modified lines in the cores’ cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core’s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=01H Counter=0,1,2,3 |
| UNC_CHA_SF_EVICTION.S_STATE |
Counts snoop filter capacity evictions for entries tracking shared lines in the cores’ cache. Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry. Does not count clean evictions such as when a core’s cache replaces a tracked cacheline with a new cacheline. |
EventSel=3DH UMask=04H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSP_FWD_WB |
Counts when a transaction with the opcode type RspFwdWB Snoop Response was received which indicates the data was written back to its home socket, and the cacheline was forwarded to the requestor socket. This snoop response is only used in >= 4 socket systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to its home socket to be written back to memory. |
EventSel=5CH UMask=20H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSP_WBWB |
Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to its home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership. |
EventSel=5CH UMask=10H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSPCNFLCTS |
Counts when a a transaction with the opcode type RspCnflct* Snoop Response was received. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent. This triggers conflict resolution hardware. This covers both the opcode RspCnflct and RspCnflctWbI. |
EventSel=5CH UMask=40H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSPI |
Counts when a transaction with the opcode type RspI Snoop Response was received which indicates the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO: the Read for Ownership issued before a write hits non-modified data). |
EventSel=5CH UMask=01H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSPIFWD |
Counts when a a transaction with the opcode type RspIFwd Snoop Response was received which indicates a remote caching agent forwarded the data and the requesting agent is able to acquire the data in E (Exclusive) or M (modified) states. This is commonly returned with RFO (the Read for Ownership issued before a write) transactions. The snoop could have either been to a cacheline in the M,E,F (Modified, Exclusive or Forward) states. |
EventSel=5CH UMask=04H Counter=0,1,2,3 |
| UNC_CHA_SNOOP_RESP.RSPSFWD |
Counts when a a transaction with the opcode type RspSFwd Snoop Response was received which indicates a remote caching agent forwarded the data but held on to its current copy. This is common for data and code reads that hit in a remote socket in E (Exclusive) or F (Forward) state. |
EventSel=5CH UMask=08H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD |
TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40233H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD |
TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40433H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD |
UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B233H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD |
UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B433H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B033H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO |
TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40033H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD |
TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40233H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD |
TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40433H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD |
UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B233H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD |
UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B433H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO |
TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B033H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO |
TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40033H Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD |
TOR Occupancy : CRds issued by iA Cores that Hit the LLC |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40233H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD |
TOR Occupancy : DRds issued by iA Cores that Hit the LLC |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40433H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD |
UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B233H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD |
UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B433H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO |
TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=4B033H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO |
TOR Occupancy : RFOs issued by iA Cores that Hit the LLC |
EventSel=36H UMask=11H Cn_MSR_PMON_BOX_FILTER1=40033H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD |
TOR Occupancy : CRds issued by iA Cores that Missed the LLC |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40233H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD |
TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40433H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD |
UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B233H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD |
UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B433H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO |
TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=4B033H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO |
TOR Occupancy : RFOs issued by iA Cores that Missed the LLC |
EventSel=36H UMask=21H Cn_MSR_PMON_BOX_FILTER1=40033H Counter=0 |
| UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS |
Accumulates the number of UPI credits available in each cycle for either the AD or BL ring. In order to send snoops, snoop responses, requests, data, etc to the UPI agent on the ring, it is necessary to first acquire a credit for the UPI ingress buffer. This stat increments by the number of credits that are available each cycle. This can be used in conjunction with the Credit Acquired event in order to calculate average credit lifetime. This event supports filtering for the different types of credits that are available. Note that you must select the link that you would like to monitor using the link select register, and you can only monitor 1 link at a time. |
EventSel=3BH UMask=80H Counter=0 |
| UNC_IIO_CLOCKTICKS |
Counts clockticks of the 1GHz traffic controller clock in the IIO unit. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS |
PCIe Completion Buffer Inserts of completions with data: Part 0-3 |
EventSel=C2H UMask=03H FCMask=04H PortMask=0FH Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0 |
PCIe Completion Buffer Inserts of completions with data: Part 0 |
EventSel=C2H UMask=03H FCMask=04H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1 |
PCIe Completion Buffer Inserts of completions with data: Part 1 |
EventSel=C2H UMask=03H FCMask=04H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2 |
PCIe Completion Buffer Inserts of completions with data: Part 2 |
EventSel=C2H UMask=03H FCMask=04H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3 |
PCIe Completion Buffer Inserts of completions with data: Part 3 |
EventSel=C2H UMask=03H FCMask=04H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS |
PCIe Completion Buffer occupancy of completions with data: Part 0-3 |
EventSel=D5H UMask=0FH FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0 |
PCIe Completion Buffer occupancy of completions with data: Part 0 |
EventSel=D5H UMask=01H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1 |
PCIe Completion Buffer occupancy of completions with data: Part 1 |
EventSel=D5H UMask=02H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2 |
PCIe Completion Buffer occupancy of completions with data: Part 2 |
EventSel=D5H UMask=04H FCMask=04H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3 |
PCIe Completion Buffer occupancy of completions with data: Part 3 |
EventSel=D5H UMask=08H FCMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 |
Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=04H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 |
Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=04H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 |
Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=04H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 |
Counts every read request for 4 bytes of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=04H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 |
Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=01H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 |
Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=01H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 |
Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=01H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 |
Counts every write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=01H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0 |
Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=08H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1 |
Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=08H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2 |
Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=08H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3 |
Counts ever peer to peer read request for 4 bytes of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=08H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0 |
Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=02H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1 |
Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=02H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2 |
Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=02H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3 |
Counts every peer to peer write request of 4 bytes of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C0H UMask=02H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
Counts every read request for 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=83H UMask=04H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
Counts every read request for 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=83H UMask=04H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
Counts every read request for 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=83H UMask=04H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
Counts every read request for 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=83H UMask=04H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
Counts every write request of 4 bytes of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=83H UMask=01H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
Counts every write request of 4 bytes of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=83H UMask=01H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
Counts every write request of 4 bytes of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=83H UMask=01H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
Counts every write request of 4 bytes of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=83H UMask=01H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0 |
Counts every peer to peer read request for 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=83H UMask=08H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1 |
Counts every peer to peer read request for 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=83H UMask=08H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2 |
Counts every peer to peer read request for 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=83H UMask=08H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3 |
Counts every peer to peer read request for 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=83H UMask=08H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0 |
Counts every peer to peer write request of 4 bytes of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=83H UMask=02H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1 |
Counts every peer to peer write request of 4 bytes of data made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=83H UMask=02H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2 |
Counts every peer to peer write request of 4 bytes of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=83H UMask=02H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3 |
Counts every peer to peer write request of 4 bytes of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=83H UMask=02H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 |
Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part0. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 |
Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part1. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 |
Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part2. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 |
Counts every read request for up to a 64 byte transaction of data made by a unit on the main die (generally a core) or by another IIO unit to the MMIO space of a card on IIO Part3. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 |
Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 |
Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 |
Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 |
Counts every write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a unit on the main die (generally a core) or by another IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0 |
Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part0. Does not include requests made by the same IIO unit. In the general case, part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=08H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1 |
Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part1. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=08H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2 |
Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part2. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=08H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3 |
Counts every peer to peer read request for up to a 64 byte transaction of data made by a different IIO unit to the MMIO space of a card on IIO Part3. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=08H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0 |
Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part0 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=02H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1 |
Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part1 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=02H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2 |
Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part2 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=02H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3 |
Counts every peer to peer write request of up to a 64 byte transaction of data made to the MMIO space of a card on IIO Part3 by a different IIO unit. Does not include requests made by the same IIO unit. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=C1H UMask=02H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 |
Counts every read request for up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=84H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 |
Counts every read request for up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=84H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 |
Counts every read request for up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=84H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 |
Counts every read request for up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=84H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 |
Counts every write request of up to a 64 byte transaction of data made by IIO Part0 to a unit on the main die (generally memory). In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=84H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 |
Counts every write request of up to a 64 byte transaction of data made by IIO Part1 to a unit on the main die (generally memory). In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=84H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 |
Counts every write request of up to a 64 byte transaction of data made by IIO Part2 to a unit on the main die (generally memory). In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=84H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 |
Counts every write request of up to a 64 byte transaction of data made by IIO Part3 to a unit on the main die (generally memory). In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=84H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0 |
Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=84H UMask=08H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1 |
Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part1 to the MMIO space of an IIO target. In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=84H UMask=08H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2 |
Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=84H UMask=08H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3 |
Counts every peer to peer read request of up to a 64 byte transaction made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=84H UMask=08H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0 |
Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part0 to the MMIO space of an IIO target. In the general case, Part0 refers to a standard PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could also refer to any device plugged into the first slot of a PCIe riser card or to a device attached to the IIO unit which starts its use of the bus using lane 0 of the 16 lanes supported by the bus. |
EventSel=84H UMask=02H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1 |
Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part1 to the MMIO space of an IIO target.In the general case, Part1 refers to a x4 PCIe card plugged into the second slot of a PCIe riser card, but it could refer to any x4 device attached to the IIO unit using lanes starting at lane 4 of the 16 lanes supported by the bus. |
EventSel=84H UMask=02H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2 |
Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part2 to the MMIO space of an IIO target. In the general case, Part2 refers to a x4 or x8 PCIe card plugged into the third slot of a PCIe riser card, but it could refer to any x4 or x8 device attached to the IIO unit and using lanes starting at lane 8 of the 16 lanes supported by the bus. |
EventSel=84H UMask=02H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3 |
Counts every peer to peer write request of up to a 64 byte transaction of data made by IIO Part3 to the MMIO space of an IIO target. In the general case, Part3 refers to a x4 PCIe card plugged into the fourth slot of a PCIe riser card, but it could brefer to any device attached to the IIO unit using the lanes starting at lane 12 of the 16 lanes supported by the bus. |
EventSel=84H UMask=02H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_M_ACT_COUNT.WR |
Counts DRAM Page Activate commands sent on this channel due to a write request to the iMC (Memory Controller). Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS (Column Access Select) command. |
EventSel=01H UMask=02H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.ALL |
Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, so this event increments for every read and write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not. |
EventSel=04H UMask=0FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD |
Counts all CAS (Column Access Select) read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every read. This event includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not. |
EventSel=04H UMask=03H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD_REG |
Counts CAS (Column Access Select) regular read commands issued to DRAM on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every regular read. This event only counts regular reads and does not includes underfill reads due to partial write requests. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not. |
EventSel=04H UMask=01H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD_UNDERFILL |
Counts CAS (Column Access Select) underfill read commands issued to DRAM due to a partial write, on a per channel basis. CAS commands are issued to specify the address to read or write on DRAM, and this command counts underfill reads. Partial writes must be completed by first reading in the underfill from DRAM and then merging in the partial write data before writing the full line back to DRAM. This event will generally count about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ (due to a previous write request). |
EventSel=04H UMask=02H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR |
Counts all CAS (Column Address Select) commands issued to DRAM per memory channel. CAS commands are issued to specify the address to read or write on DRAM, and this event increments for every write. This event counts whether AutoPrecharge (which closes the DRAM Page automatically after a read/write) is enabled or not. |
EventSel=04H UMask=0CH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR_WMM |
Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode. |
EventSel=04H UMask=04H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS |
Counts clockticks of the fixed frequency clock of the memory controller using one of the programmable counters. |
EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.ALL |
All commands for Intel® Optane™ DC persistent memory |
EventSel=EAH UMask=01H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.RD |
All Reads - RPQ or Ufill |
EventSel=EAH UMask=02H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.UFILL_RD |
Underfill reads |
EventSel=EAH UMask=08H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.WR |
Writes |
EventSel=EAH UMask=04H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_INSERTS |
Read requests allocated in the PMM Read Pending Queue for Intel® Optane™ DC persistent memory |
EventSel=E3H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL |
Read Pending Queue Occupancy of all read requests for Intel® Optane™ DC persistent memory |
EventSel=E0H UMask=01H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_INSERTS |
Write requests allocated in the PMM Write Pending Queue for Intel® Optane™ DC persistent memory |
EventSel=E7H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL |
Write Pending Queue Occupancy of all write requests for Intel® Optane™ DC persistent memory |
EventSel=E4H UMask=01H Counter=0,1,2,3 |
| UNC_M_POWER_CHANNEL_PPD |
Counts cycles when all the ranks in the channel are in PPD (PreCharge Power Down) mode. If IBT (Input Buffer Terminators)=off is enabled, then this event counts the cycles in PPD mode. If IBT=off is not enabled, then this event counts the number of cycles when being in PPD mode could have been taken advantage of. |
EventSel=85H UMask=00H Counter=0,1,2,3 |
| UNC_M_POWER_SELF_REFRESH |
Counts the number of cycles when the iMC (memory controller) is in self-refresh and has a clock. This happens in some ACPI CPU package C-states for the sleep levels. For example, the PCU (Power Control Unit) may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Intel? Dynamic Power Technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases. |
EventSel=43H UMask=00H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PAGE_MISS |
Counts the number of explicit DRAM Precharge commands sent on this channel as a result of a DRAM page miss. This does not include the implicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include Precharge commands sent as a result of a page close counter expiration. |
EventSel=02H UMask=01H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.RD |
Counts the number of explicit DRAM Precharge commands issued on a per channel basis due to a read, so as to close the previous DRAM page, before opening the requested page. |
EventSel=02H UMask=04H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS |
Counts the number of read requests allocated into the Read Pending Queue (RPQ). This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. The requests deallocate after the read CAS command has been issued to DRAM. This event counts both Isochronous and non-Isochronous requests which were issued to the RPQ. |
EventSel=10H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY |
Counts the number of entries in the Read Pending Queue (RPQ) at each cycle. This can then be used to calculate both the average occupancy of the queue (in conjunction with the number of cycles not empty) and the average latency in the queue (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate from the RPQ after the CAS command has been issued to memory. |
EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_TAGCHK.HIT |
Tag Check; Hit |
EventSel=D3H UMask=01H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_CLEAN |
Tag Check; Clean |
EventSel=D3H UMask=02H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_DIRTY |
Tag Check; Dirty |
EventSel=D3H UMask=04H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS |
Counts the number of writes requests allocated into the Write Pending Queue (WPQ). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (Memory Controller). The write requests deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. |
EventSel=20H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY |
Counts the number of entries in the Write Pending Queue (WPQ) at each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule writes out to the memory controller and to track the requests. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC (memory controller). They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have 'posted' to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the 'not posted' filter, we can track how long writes spent in the iMC before completions were sent to the HA. The 'posted' filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. |
EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_I_CACHE_TOTAL_OCCUPANCY.MEM |
Total IRP occupancy of inbound read and write requests. This is effectively the sum of read occupancy and write occupancy. |
EventSel=0FH UMask=04H Counter=0,1 |
| UNC_I_COHERENT_OPS.PCITOM |
PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache. |
EventSel=10H UMask=10H Counter=0,1 |
| UNC_I_COHERENT_OPS.RFO |
RFO request issued by the IRP unit to the mesh with the intention of writing a partial cacheline to coherent memory. RFO is a Read For Ownership command that requests ownership of the cacheline and moves data from the mesh to IRP cache. |
EventSel=10H UMask=08H Counter=0,1 |
| UNC_I_FAF_INSERTS |
Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP. |
EventSel=18H UMask=00H Counter=0,1 |
| UNC_I_FAF_OCCUPANCY |
Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP. |
EventSel=19H UMask=00H Counter=0,1 |
| UNC_I_TRANSACTIONS.WR_PREF |
Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. |
EventSel=11H UMask=08H Counter=0,1 |
| UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN |
Counts traffic in which the M2M (Mesh to Memory) to iMC (Memory Controller) bypass was not taken |
EventSel=22H UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE |
Counts cycles when direct to core mode (which bypasses the CHA) was disabled |
EventSel=24H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2CORE_TAKEN |
Counts when messages were sent direct to core (bypassing the CHA) |
EventSel=23H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2CORE_TXN_OVERRIDE |
Counts reads in which direct to core transactions (which would have bypassed the CHA) were overridden |
EventSel=25H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS |
Counts reads in which direct to Intel® Ultra Path Interconnect (UPI) transactions (which would have bypassed the CHA) were overridden |
EventSel=28H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE |
Counts cycles when the ability to send messages direct to the Intel® Ultra Path Interconnect (bypassing the CHA) was disabled |
EventSel=27H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2UPI_TAKEN |
Counts when messages were sent direct to the Intel® Ultra Path Interconnect (bypassing the CHA) |
EventSel=26H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECT2UPI_TXN_OVERRIDE |
Counts when a read message that was sent direct to the Intel® Ultra Path Interconnect (bypassing the CHA) was overridden |
EventSel=29H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.ANY |
Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in Any State (A, I, S or unused) |
EventSel=2DH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_A |
Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state, and found the cacheline marked in the A (SnoopAll) state, indicating the cacheline is stored in another socket in any state, and we must snoop the other sockets to make sure we get the latest data. The data may be stored in any state in the local socket. |
EventSel=2DH UMask=08H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_I |
Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the I (Invalid) state indicating the cacheline is not stored in another socket, and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket. |
EventSel=2DH UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_S |
Counts when the M2M (Mesh to Memory) looks into the multi-socket cacheline Directory state , and found the cacheline marked in the S (Shared) state indicating the cacheline is either stored in another socket in the S(hared) state , and so there is no need to snoop the other sockets for the latest data. The data may be stored in any state in the local socket. |
EventSel=2DH UMask=04H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.A2I |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to I (Invalid) |
EventSel=2EH UMask=20H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.A2S |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from A (SnoopAll) to S (Shared) |
EventSel=2EH UMask=40H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.ANY |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory to a new state |
EventSel=2EH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.I2A |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to A (SnoopAll) |
EventSel=2EH UMask=04H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.I2S |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from I (Invalid) to S (Shared) |
EventSel=2EH UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.S2A |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to A (SnoopAll) |
EventSel=2EH UMask=10H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.S2I |
Counts when the M2M (Mesh to Memory) updates the multi-socket cacheline Directory state from S (Shared) to I (Invalid) |
EventSel=2EH UMask=08H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.ALL |
Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). |
EventSel=37H UMask=04H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.NORMAL |
Counts when the M2M (Mesh to Memory) issues reads to the iMC (Memory Controller). It only counts normal priority non-isochronous reads. |
EventSel=37H UMask=01H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.TO_PMM |
M2M Reads Issued to iMC; All, regardless of priority. |
EventSel=37H UMask=08H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.ALL |
Counts when the M2M (Mesh to Memory) issues writes to the iMC (Memory Controller). |
EventSel=38H UMask=10H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.NI |
M2M Writes Issued to iMC; All, regardless of priority. |
EventSel=38H UMask=80H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.PARTIAL |
Counts when the M2M (Mesh to Memory) issues partial writes to the iMC (Memory Controller). It only counts normal priority non-isochronous writes. |
EventSel=38H UMask=02H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.TO_PMM |
M2M Writes Issued to iMC; All, regardless of priority. |
EventSel=38H UMask=20H Counter=0,1,2,3 |
| UNC_M2M_PREFCAM_DEMAND_PROMOTIONS |
Counts when the M2M (Mesh to Memory) promotes a outstanding request in the prefetch queue due to a subsequent demand read request that entered the M2M with the same address. Explanatory Side Note: The Prefetch queue is made of CAM (Content Addressable Memory) |
EventSel=56H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_PREFCAM_INSERTS |
Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory |
EventSel=57H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_RxC_AD_INSERTS |
Counts when the a new entry is Received(RxC) and then added to the AD (Address Ring) Ingress Queue from the CMS (Common Mesh Stop). This is generally used for reads, and |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_RxC_AD_OCCUPANCY |
AD Ingress (from CMS) Occupancy |
EventSel=02H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_RxC_BL_INSERTS |
BL Ingress (from CMS) Allocations |
EventSel=05H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_RxC_BL_OCCUPANCY |
BL Ingress (from CMS) Occupancy |
EventSel=06H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY |
Tag Hit; Read Hit from NearMem, Dirty Line |
EventSel=2CH UMask=02H Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN |
Tag Hit; Underfill Rd Hit from NearMem, Clean Line |
EventSel=2CH UMask=04H Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY |
Tag Hit; Underfill Rd Hit from NearMem, Dirty Line |
EventSel=2CH UMask=08H Counter=0,1,2,3 |
| UNC_M2M_TxC_AD_INSERTS |
AD Egress (to CMS) Allocations |
EventSel=09H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_TxC_AD_OCCUPANCY |
AD Egress (to CMS) Occupancy |
EventSel=0AH UMask=00H Counter=0,1,2,3 |
| UNC_M2M_TxC_BL_INSERTS.ALL |
BL Egress (to CMS) Allocations; All |
EventSel=15H UMask=03H Counter=0,1,2,3 |
| UNC_M2M_TxC_BL_OCCUPANCY.ALL |
BL Egress (to CMS) Occupancy; All |
EventSel=16H UMask=03H Counter=0,1,2,3 |
| UNC_M3UPI_UPI_PREFETCH_SPAWN |
Count cases where flow control queue that sits between the Intel® Ultra Path Interconnect (UPI) and the mesh spawns a prefetch to the iMC (Memory Controller) |
EventSel=29H UMask=00H Counter=0,1,2 |
| UNC_UPI_CLOCKTICKS |
Counts clockticks of the fixed frequency clock controlling the Intel® Ultra Path Interconnect (UPI). This clock runs at1/8th the 'GT/s' speed of the UPI link. For example, a 9.6GT/s link will have a fixed Frequency of 1.2 Ghz. |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_DIRECT_ATTEMPTS.D2C |
Counts Data Response (DRS) packets that attempted to go direct to core bypassing the CHA. |
EventSel=12H UMask=01H Counter=0,1,2,3 |
| UNC_UPI_DIRECT_ATTEMPTS.D2U |
Counts Data Response (DRS) packets that attempted to go direct to Intel® Ultra Path Interconnect (UPI) bypassing the CHA . |
EventSel=12H UMask=02H Counter=0,1,2,3 |
| UNC_UPI_L1_POWER_CYCLES |
Counts cycles when the Intel® Ultra Path Interconnect (UPI) is in L1 power mode. L1 is a mode that totally shuts down the UPI link. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another, this event only coutns when both links are shutdown. |
EventSel=21H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_RxL_BYPASSED.SLOT0 |
Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency. |
EventSel=31H UMask=01H Counter=0,1,2,3 |
| UNC_UPI_RxL_BYPASSED.SLOT1 |
Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency. |
EventSel=31H UMask=02H Counter=0,1,2,3 |
| UNC_UPI_RxL_BYPASSED.SLOT2 |
Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency. |
EventSel=31H UMask=04H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_DATA |
Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) received from any of the 3 Intel® Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit. |
EventSel=03H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_NULL |
Counts null FLITs (80 bit FLow control unITs) received from any of the 3 Intel® Ultra Path Interconnect (UPI) Receive Queue slots on this UPI unit. |
EventSel=03H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.NON_DATA |
Counts protocol header and credit FLITs (80 bit FLow control unITs) received from any of the 3 UPI slots on this UPI unit. |
EventSel=03H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_RxL0P_POWER_CYCLES |
Counts cycles when the receive side (Rx) of the Intel® Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power. |
EventSel=25H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_TxL_BYPASSED |
Counts incoming FLITs (FLow control unITs) which bypassed the TxL(transmit) FLIT buffer and pass directly out the UPI Link. Generally, when data is transmitted across the Intel® Ultra Path Interconnect (UPI), it will bypass the TxQ and pass directly to the link. However, the TxQ will be used in L0p (Low Power) mode and (Link Layer Retry) LLR mode, increasing latency to transfer out to the link. |
EventSel=41H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_DATA |
Counts valid data FLITs (80 bit FLow control unITs: 64bits of data) transmitted (TxL) via any of the 3 Intel® Ultra Path Interconnect (UPI) slots on this UPI unit. |
EventSel=02H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_NULL |
Counts null FLITs (80 bit FLow control unITs) transmitted via any of the 3 Intel® Ulra Path Interconnect (UPI) slots on this UPI unit. |
EventSel=02H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.IDLE |
Counts when the Intel Ultra Path Interconnect(UPI) transmits an idle FLIT(80 bit FLow control unITs). Every UPI cycle must be sending either data FLITs, protocol/credit FLITs or idle FLITs. |
EventSel=02H UMask=47H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.NON_DATA |
Counts protocol header and credit FLITs (80 bit FLow control unITs) transmitted across any of the 3 UPI (Ultra Path Interconnect) slots on this UPI unit. |
EventSel=02H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL0P_POWER_CYCLES |
Counts cycles when the transmit side (Tx) of the Intel® Ultra Path Interconnect(UPI) is in L0p power mode. L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power. |
EventSel=27H UMask=00H Counter=0,1,2,3 |
| UNC_C_CLOCKTICKS |
This event is deprecated. Refer to new event UNC_CHA_CLOCKTICKS |
EventSel=00H UMask=00H Counter=0,1,2,3 Deprecated |
| UNC_C_FAST_ASSERTED |
This event is deprecated. Refer to new event UNC_CHA_FAST_ASSERTED.HORZ |
EventSel=A5H UMask=02H Counter=0,1,2,3 Deprecated |
| UNC_C_LLC_VICTIMS.E_STATE |
This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_E |
EventSel=37H UMask=02H Counter=0,1,2,3 Deprecated |
| UNC_C_LLC_VICTIMS.F_STATE |
This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_F |
EventSel=37H UMask=08H Counter=0,1,2,3 Deprecated |
| UNC_C_LLC_VICTIMS.M_STATE |
This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_M |
EventSel=37H UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_C_LLC_VICTIMS.S_STATE |
This event is deprecated. Refer to new event UNC_CHA_LLC_VICTIMS.TOTAL_S |
EventSel=37H UMask=04H Counter=0,1,2,3 Deprecated |
| UNC_H_CORE_SNP.CORE_GTONE |
This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.CORE_GTONE |
EventSel=33H UMask=42H Counter=0,1,2,3 Deprecated |
| UNC_H_CORE_SNP.EVICT_GTONE |
This event is deprecated. Refer to new event UNC_CHA_CORE_SNP.EVICT_GTONE |
EventSel=33H UMask=82H Counter=0,1,2,3 Deprecated |
| UNC_H_DIR_LOOKUP.NO_SNP |
This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.NO_SNP |
EventSel=53H UMask=02H Counter=0,1,2,3 Deprecated |
| UNC_H_DIR_LOOKUP.SNP |
This event is deprecated. Refer to new event UNC_CHA_DIR_LOOKUP.SNP |
EventSel=53H UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_H_DIR_UPDATE.HA |
This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.HA |
EventSel=54H UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_H_DIR_UPDATE.TOR |
This event is deprecated. Refer to new event UNC_CHA_DIR_UPDATE.TOR |
EventSel=54H UMask=02H Counter=0,1,2,3 Deprecated |
| UNC_H_HITME_HIT.EX_RDS |
This event is deprecated. Refer to new event UNC_CHA_HITME_HIT.EX_RDS |
EventSel=5FH UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_H_MISC.RFO_HIT_S |
This event is deprecated. Refer to new event UNC_CHA_MISC.RFO_HIT_S |
EventSel=39H UMask=08H Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.INVITOE_LOCAL |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_LOCAL |
EventSel=50H UMask=10H Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.INVITOE_REMOTE |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.INVITOE_REMOTE |
EventSel=50H UMask=20H Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.READS |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS |
EventSel=50H UMask=03H Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.READS_LOCAL |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.READS_LOCAL |
EventSel=50H UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.WRITES |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES |
EventSel=50H UMask=0CH Counter=0,1,2,3 Deprecated |
| UNC_H_REQUESTS.WRITES_LOCAL |
This event is deprecated. Refer to new event UNC_CHA_REQUESTS.WRITES_LOCAL |
EventSel=50H UMask=04H Counter=0,1,2,3 Deprecated |
| UNC_H_RxC_INSERTS.IRQ |
This event is deprecated. Refer to new event UNC_CHA_RxC_INSERTS.IRQ |
EventSel=13H UMask=01H Counter=0,1,2,3 Deprecated |
| UNC_H_RxC_IRQ1_REJECT.PA_MATCH |
This event is deprecated. Refer to new event UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH |
EventSel=19H UMask=80H Counter=0,1,2,3 Deprecated |
| UNC_H_RxC_OCCUPANCY.IRQ |
This event is deprecated. Refer to new event UNC_CHA_RxC_OCCUPANCY.IRQ |
EventSel=11H UMask=01H Counter=0 Deprecated |
| UNC_H_SNOOP_RESP.RSP_FWD_WB |
This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSP_FWD_WB |
EventSel=5CH UMask=20H Counter=0,1,2,3 Deprecated |
| UNC_H_SNOOP_RESP.RSPCNFLCT |
This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPCNFLCTS |
EventSel=5CH UMask=40H Counter=0,1,2,3 Deprecated |
| UNC_H_SNOOP_RESP.RSPIFWD |
This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPIFWD |
EventSel=5CH UMask=04H Counter=0,1,2,3 Deprecated |
| UNC_H_SNOOP_RESP.RSPSFWD |
This event is deprecated. Refer to new event UNC_CHA_SNOOP_RESP.RSPSFWD |
EventSel=5CH UMask=08H Counter=0,1,2,3 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
EventSel=83H UMask=04H FCMask=07H PortMask=01H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
EventSel=83H UMask=04H FCMask=07H PortMask=02H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
EventSel=83H UMask=04H FCMask=07H PortMask=04H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
EventSel=83H UMask=04H FCMask=07H PortMask=08H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
EventSel=83H UMask=01H FCMask=07H PortMask=01H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
EventSel=83H UMask=01H FCMask=07H PortMask=02H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
EventSel=83H UMask=01H FCMask=07H PortMask=04H Counter=0,1 Deprecated |
| UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3 |
This event is deprecated. Refer to new event UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
EventSel=83H UMask=01H FCMask=07H PortMask=08H Counter=0,1 Deprecated |
| UNC_UPI_DIRECT_ATTEMPTS.D2K |
This event is deprecated. Refer to new event UNC_UPI_DIRECT_ATTEMPTS.D2U |
EventSel=12H UMask=02H Counter=0,1,2,3 Deprecated |