| UNC_CHA_CLOCKTICKS |
Number of CHA clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_DIR_UPDATE.HA |
Counts only multi-socket cacheline Directory state updates memory writes issued from the HA pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_DIR_UPDATE.TOR |
Counts only multi-socket cacheline Directory state updates due to memory writes issued from the TOR pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. |
EventSel=54H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_IMC_READS_COUNT.NORMAL |
Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA. |
EventSel=59H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_IMC_WRITES_COUNT.FULL |
Counts when a normal (Non-Isochronous) full line write is issued from the CHA to the any of the memory controller channels. |
EventSel=5BH UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL |
Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_REMOTE |
Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. |
EventSel=50H UMask=20H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS |
Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) . |
EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL |
Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_REMOTE |
Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). |
EventSel=50H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES |
Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL |
Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. |
EventSel=50H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_REMOTE |
Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc). |
EventSel=50H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; All locally initiated requests from IA Cores |
EventSel=35H UMask=01H UMaskExt=00C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; CLFlush events that are initiated from the Core |
EventSel=35H UMask=01H UMaskExt=00C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD |
TOR Inserts; Code read from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD |
TOR Inserts; Data read from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C817FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_PREF |
TOR Inserts; Data read prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C897FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. |
EventSel=35H UMask=01H UMaskExt=00C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD |
TOR Inserts; Code read from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF |
TOR Inserts; Code read prefetch from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD |
TOR Inserts; Data read from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C817FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF |
TOR Inserts; Data read prefetch from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C897FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO |
TOR Inserts; Last level cache prefetch read for ownership from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00CCC7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO |
TOR Inserts; Read for ownership from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF |
TOR Inserts; Read for ownership prefetch from local IA that hits in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA |
TOR Inserts; Last level cache prefetch data read from local IA. |
EventSel=35H UMask=01H UMaskExt=00CCD7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO |
TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00CCC7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS |
TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=00C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd |
EventSel=35H UMask=01H UMaskExt=00C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF |
TOR Inserts; Code read prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd |
EventSel=35H UMask=01H UMaskExt=00C817FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory |
EventSel=35H UMask=01H UMaskExt=00C81786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory |
EventSel=35H UMask=01H UMaskExt=00C816FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=00C81686H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=00C8168AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory |
EventSel=35H UMask=01H UMaskExt=00C8178AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF |
EventSel=35H UMask=01H UMaskExt=00C897FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory |
EventSel=35H UMask=01H UMaskExt=00C896FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory |
EventSel=35H UMask=01H UMaskExt=00C8977EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE |
Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory |
EventSel=35H UMask=01H UMaskExt=00C8177EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=00C81706H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=01H UMaskExt=00C8170AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA |
TOR Inserts; Last level cache prefetch data read from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00CCD7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO |
TOR Inserts; Last level cache prefetch read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00CCC7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO |
TOR Inserts; Read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL |
TOR Inserts; Read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C806FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF |
TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL |
TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C886FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE |
TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C8877EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE |
TOR Inserts Read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C8077EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO |
TOR Inserts; Read for ownership from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF |
TOR Inserts; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=35H UMask=01H UMaskExt=00C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_SPECITOM |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent.; SpecItoM events that are initiated from the Core |
EventSel=35H UMask=01H UMaskExt=00CC57FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_CLFLUSH |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C8C3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_RFO |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C803FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM |
Inserts into the TOR from local IO with the opcode ItoM |
EventSel=35H UMask=04H UMaskExt=00CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CC42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CC437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR |
Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request. |
EventSel=35H UMask=04H UMaskExt=00CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CD42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CD437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR |
TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR |
TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_RFO |
TOR Inserts : RFOs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C803FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR |
Inserts into the TOR from local IO with the opcode RdCur |
EventSel=35H UMask=04H UMaskExt=00C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C8F2FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C8F37FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_RFO |
TOR Inserts : RFOs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00C803FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_WBMTOI |
Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=35H UMask=04H UMaskExt=00CC23FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA |
TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH |
TOR Occupancy : CLFlushes issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C8C7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD |
TOR Occupancy; Code read from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD |
TOR Occupancy; Data read from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C817FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF |
TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C897FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT |
TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD |
TOR Occupancy; Code read from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C80FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF |
TOR Occupancy; Code read prefetch from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C88FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD |
TOR Occupancy; Data read from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C817FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF |
TOR Occupancy; Data read prefetch from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C897FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO |
TOR Occupancy; Last level cache prefetch read for ownership from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00CCC7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO |
TOR Occupancy; Read for ownership from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C807FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF |
TOR Occupancy; Read for ownership prefetch from local IA that hits in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C887FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA |
TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00CCD7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO |
TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00CCC7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS |
TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD |
TOR Occupancy; Code read from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD |
Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd |
EventSel=36H UMask=01H UMaskExt=00C817FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR |
Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory |
EventSel=36H UMask=01H UMaskExt=00C81786H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL |
Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory |
EventSel=36H UMask=01H UMaskExt=00C816FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR |
TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C81686H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM |
TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C8168AH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM |
Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory |
EventSel=36H UMask=01H UMaskExt=00C8178AH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF |
TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C897FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE |
TOR Occupancy; Data read prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C8977EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE |
Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory |
EventSel=36H UMask=01H UMaskExt=00C8177EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR |
TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C81706H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM |
TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00C8170AH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA |
TOR Occupancy; Last level cache prefetch data read from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00CCD7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO |
TOR Occupancy; Last level cache prefetch read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00CCC7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO |
TOR Occupancy; Read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL |
TOR Occupancy; Read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C806FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF |
TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C887FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL |
TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C886FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE |
TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C8877EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE |
TOR Occupancy; Read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C8077EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO |
TOR Occupancy; Read for ownership from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF |
TOR Occupancy; Read for ownership prefetch from local IA that misses in the snoop filter |
EventSel=36H UMask=01H UMaskExt=00C887FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM |
TOR Occupancy : SpecItoMs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=01H UMaskExt=00CC57FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO |
TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT |
TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM |
TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00CC43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00CD43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C8F3FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_ITOM |
TOR Occupancy : ItoMs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00CC43FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS |
TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM |
TOR Occupancy : ItoMs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00CC43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR |
TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00CD43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR |
TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. |
EventSel=36H UMask=04H UMaskExt=00C8F3FFH Counter=0 |
| UNC_CXLCM_CLOCKTICKS |
Counts the number of lfclk ticks |
EventSel=01H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_CXLDP_CLOCKTICKS |
Counts the number of uclk ticks |
EventSel=01H UMask=01H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS |
Number of IIO clock cycles while the event is enabled |
EventSel=01H UMask=00H PortMask=0000H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS_FREERUN |
false |
EventSel=00H UMask=00H Counter=0 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 |
Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=0001H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 |
Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=0002H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 |
Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C0H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=0004H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 |
Data requested by the CPU : Core reading from Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=0008H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4 |
Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=0010H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5 |
Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=0020H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6 |
Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C0H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=0040H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7 |
Data requested by the CPU : Core reading from Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=0080H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0001H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0002H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0004H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 |
Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0008H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 |
Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0010H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 |
Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0020H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 |
Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0040H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 |
Data requested by the CPU : Core writing to Cards MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C0H UMask=01H FCMask=07H PortMask=0080H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=80H FCMask=07H PortMask=0001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=80H FCMask=07H PortMask=0002H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=83H UMask=80H FCMask=07H PortMask=0004H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=80H FCMask=07H PortMask=0008H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=83H UMask=80H FCMask=07H PortMask=0010H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=83H UMask=80H FCMask=07H PortMask=0020H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=83H UMask=80H FCMask=07H PortMask=0040H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7 |
Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=83H UMask=80H FCMask=07H PortMask=0080H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS |
Read request for 4 bytes made by IIO Part0-7 to Memory |
EventSel=83H UMask=04H FCMask=07H PortMask=00FFH Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=04H FCMask=07H PortMask=0001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=04H FCMask=07H PortMask=0002H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=83H UMask=04H FCMask=07H PortMask=0004H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=04H FCMask=07H PortMask=0008H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=04H FCMask=07H PortMask=0010H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=04H FCMask=07H PortMask=0020H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=83H UMask=04H FCMask=07H PortMask=0040H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 |
Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=04H FCMask=07H PortMask=0080H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS |
Write request of 4 bytes made by IIO Part0-7 to Memory |
EventSel=83H UMask=01H FCMask=07H PortMask=00FFH Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=01H FCMask=07H PortMask=0001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=01H FCMask=07H PortMask=0002H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=83H UMask=01H FCMask=07H PortMask=0004H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=01H FCMask=07H PortMask=0008H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=83H UMask=01H FCMask=07H PortMask=0010H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=83H UMask=01H FCMask=07H PortMask=0020H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=83H UMask=01H FCMask=07H PortMask=0040H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 |
Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=83H UMask=01H FCMask=07H PortMask=0080H Counter=0,1 |
| UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL |
Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. |
EventSel=85H UMask=01H FCMask=07H PortMask=0FFFH Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 |
Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 |
Number Transactions requested by the CPU : Core reading from Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=04H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 |
Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 |
Number Transactions requested by the CPU : Core writing to Cards MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=C1H UMask=01H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=80H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=80H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 |
EventSel=84H UMask=80H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=80H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 |
EventSel=84H UMask=80H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 |
EventSel=84H UMask=80H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 |
EventSel=84H UMask=80H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7 |
Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 |
EventSel=84H UMask=80H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=04H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=04H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=84H UMask=04H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=04H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=04H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=04H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=84H UMask=04H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 |
Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=04H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=01H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=01H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=84H UMask=01H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=01H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 |
EventSel=84H UMask=01H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 |
EventSel=84H UMask=01H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 |
EventSel=84H UMask=01H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 |
Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 |
EventSel=84H UMask=01H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_M_ACT_COUNT.ALL |
DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. |
EventSel=02H UMask=FFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.ALL |
DRAM RD_CAS and WR_CAS Commands. : All DRAM Read and Write actions : DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM CAS commands issued on this channel. |
EventSel=05H UMask=FFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD |
DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills. |
EventSel=05H UMask=CFH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR |
DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel. |
EventSel=05H UMask=F0H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS |
Number of DRAM DCLK clock cycles while the event is enabled |
EventSel=01H UMask=01H Counter=0,1,2,3 |
| UNC_M_HCLOCKTICKS |
Number of DRAM HCLK clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_INSERTS |
Counts number of read requests allocated in the PMM Read Pending Queue. |
EventSel=E3H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0 |
Accumulates the per cycle occupancy of the PMM Read Pending Queue. |
EventSel=E0H UMask=01H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1 |
Accumulates the per cycle occupancy of the PMM Read Pending Queue. |
EventSel=E0H UMask=02H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_INSERTS |
Counts number of write requests allocated in the PMM Write Pending Queue. |
EventSel=E7H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL |
PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM. |
EventSel=E4H UMask=03H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0 |
PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. |
EventSel=E4H UMask=01H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1 |
PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. |
EventSel=E4H UMask=02H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.ALL |
DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. |
EventSel=03H UMask=FFH Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT |
DRAM Precharge commands. Counts the number of DRAM Precharge commands sent on this channel. |
EventSel=03H UMask=88H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.RD |
DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. |
EventSel=03H UMask=11H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.WR |
DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. |
EventSel=03H UMask=22H Counter=0,1,2,3 |
| UNC_M_RDB_INSERTS.PCH0 |
Read Data Buffer Inserts |
EventSel=17H UMask=01H Counter=0,1,2,3 |
| UNC_M_RDB_INSERTS.PCH1 |
Read Data Buffer Inserts |
EventSel=17H UMask=02H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH0 |
Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. |
EventSel=10H UMask=01H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH1 |
Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. |
EventSel=10H UMask=02H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH0 |
Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. |
EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH1 |
Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. |
EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_M_TAGCHK.HIT |
2LM Tag check hit in near memory cache (DDR4) |
EventSel=D3H UMask=01H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_CLEAN |
2LM Tag check miss, no data at this line |
EventSel=D3H UMask=02H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_DIRTY |
2LM Tag check miss, existing data may be evicted to PMM |
EventSel=D3H UMask=04H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_RD_HIT |
2LM Tag check hit due to memory read |
EventSel=D3H UMask=08H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_WR_HIT |
2LM Tag check hit due to memory write |
EventSel=D3H UMask=10H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH0 |
Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. |
EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH1 |
Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. |
EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH0 |
Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. |
EventSel=82H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH1 |
Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. |
EventSel=83H UMask=00H Counter=0,1,2,3 |
| UNC_I_CLOCKTICKS |
Number of IRP clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1 |
| UNC_I_FAF_FULL |
FAF RF full |
EventSel=17H UMask=00H Counter=0,1 |
| UNC_I_FAF_INSERTS |
FAF - request insert from TC. |
EventSel=18H UMask=00H Counter=0,1 |
| UNC_I_FAF_OCCUPANCY |
FAF occupancy |
EventSel=19H UMask=00H Counter=0,1 |
| UNC_I_FAF_TRANSACTIONS |
FAF allocation -- sent to ADQ |
EventSel=16H UMask=00H Counter=0,1 |
| UNC_I_IRP_ALL.INBOUND_INSERTS |
: All Inserts Inbound (p2p + faf + cset) |
EventSel=20H UMask=01H Counter=0,1 |
| UNC_I_MISC1.LOST_FWD |
Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed |
EventSel=1FH UMask=10H Counter=0,1 |
| UNC_I_SNOOP_RESP.ALL_HIT_M |
Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache |
EventSel=12H UMask=78H Counter=0,1 |
| UNC_I_TRANSACTIONS.WR_PREF |
Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. |
EventSel=11H UMask=08H Counter=0,1 |
| UNC_M2HBM_CLOCKTICKS |
Cycles - at UCLK |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2HBM_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H UMaskExt=00800000H Counter=0,1,2,3 |
| UNC_M2HBM_DIRECTORY_LOOKUP.ANY |
Counts the number of hit data returns to egress with any directory to non persistent memory |
EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A |
Counts the number of hit data returns to egress with directory A to non persistent memory |
EventSel=20H UMask=08H Counter=0,1,2,3 |
| UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I |
Counts the number of hit data returns to egress with directory I to non persistent memory |
EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S |
Counts the number of hit data returns to egress with directory S to non persistent memory |
EventSel=20H UMask=04H Counter=0,1,2,3 |
| UNC_M2HBM_DIRECTORY_UPDATE.ANY |
Multi-socket cacheline Directory update from/to Any state |
EventSel=21H UMask=01H UMaskExt=00000003H Counter=0,1,2,3 |
| UNC_M2M_CLOCKTICKS |
Clockticks of the mesh to memory (M2M) |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2M_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H UMaskExt=800000H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.ANY |
Counts the number of hit data returns to egress with any directory to non persistent memory |
EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_A |
Counts the number of hit data returns to egress with directory A to non persistent memory |
EventSel=20H UMask=08H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_I |
Counts the number of hit data returns to egress with directory I to non persistent memory |
EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_S |
Counts the number of hit data returns to egress with directory S to non persistent memory |
EventSel=20H UMask=04H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.ANY |
Multi-socket cacheline Directory update from/to Any state |
EventSel=21H UMask=01H UMaskExt=03H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.TO_PMM |
UNC_M2M_IMC_READS.TO_PMM |
EventSel=24H UMask=20H UMaskExt=00000003H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.TO_PMM |
PMM - All Channels |
EventSel=25H UMask=80H UMaskExt=00000018H Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN |
Counts clean full line read hits (reads and RFOs). |
EventSel=1FH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY |
Counts dirty full line read hits (reads and RFOs). |
EventSel=1FH UMask=02H Counter=0,1,2,3 |
| UNC_M2P_CLOCKTICKS |
Number of M2P clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2P_CMS_CLOCKTICKS |
CMS Clockticks |
EventSel=C0H UMask=00H Counter=0,1,2,3 |
| UNC_M3UPI_CLOCKTICKS |
Number of M2UPI clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_MCHBM_CLOCKTICKS |
IMC Clockticks at DCLK frequency |
EventSel=01H UMask=01H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS |
Number of PCU PCLK Clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_P_POWER_STATE_OCCUPANCY_CORES_C0 |
Number of cores in C0 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. |
EventSel=35H UMask=00H Counter=0,1,2,3 |
| UNC_P_POWER_STATE_OCCUPANCY_CORES_C6 |
Number of cores in C6 : This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with thresholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. |
EventSel=37H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_CLOCKTICKS |
Number of UPI LL clock cycles while the event is enabled |
EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_L1_POWER_CYCLES |
Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode. |
EventSel=21H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_DATA |
Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=03H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_NULL |
Null FLITs received from any slot |
EventSel=03H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.NON_DATA |
Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=03H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_DATA |
Valid Flits Sent : All Data : Counts number of data flits across this UPI link. |
EventSel=02H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_NULL |
All Null Flits |
EventSel=02H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.NON_DATA |
Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c). |
EventSel=02H UMask=97H Counter=0,1,2,3 |