| OCR.ALL_REQUESTS.ANY_RESPONSE |
Counts all requests that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=FF0000001DFFFH |
| OCR.COREWB_M.ANY_RESPONSE |
Counts writebacks of modified cachelines that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10008H |
| OCR.COREWB_NONM.ANY_RESPONSE |
Counts writebacks of non-modified cachelines that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=11000H |
| OCR.DEMAND_CODE_RD.ANY_RESPONSE |
Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OCR.DEMAND_CODE_RD.DRAM |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1FBC000004H |
| OCR.DEMAND_CODE_RD.L3_MISS |
Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13FBFC00004H |
| OCR.DEMAND_CODE_RD.MEMSIDE_CACHE |
Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by mem side cache. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=11F80000004H |
| OCR.DEMAND_DATA_RD.ANY_RESPONSE |
Counts demand data reads that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_RD.DRAM |
Counts demand data reads that were supplied by DRAM. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1FBC000001H |
| OCR.DEMAND_DATA_RD.L3_MISS |
Counts demand data reads that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13FBFC00001H |
| OCR.DEMAND_DATA_RD.MEMSIDE_CACHE |
Counts demand data reads that were supplied by mem side cache. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=11F80000001H |
| OCR.DEMAND_RFO.ANY_RESPONSE |
Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OCR.DEMAND_RFO.DRAM |
Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1FBC000002H |
| OCR.DEMAND_RFO.L3_MISS |
Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache and were supplied by the system memory (DRAM, MSC, or MMIO). |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13FBFC00002H |
| OCR.FULL_STREAMING_WR.ANY_RESPONSE |
Counts full streaming stores (64 bytes, WCiLF) that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800000010000H |
| OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE |
Counts partial streaming stores (less than 64 bytes, WCiL) that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=400000010000H |
| OCR.STREAMING_WR.ANY_RESPONSE |
Counts streaming stores that have any type of response. |
EventSel=B7H UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |