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Alder Lake - E-Core Offcore Events

Microarchitectures

  • Intel® Microarchitecture Code Named Golden Cove and Raptor Cove (Performance Core)
  • Intel® Microarchitecture Code Named Gracemont (Efficient Core)

E-Core Offcore Events

Event Name Description Programming Info
OCR.DEMAND_DATA_RD.ANY_RESPONSE Counts demand data reads that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H
OCR.DEMAND_DATA_RD.DRAM Counts demand data reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=784000001H
OCR.DEMAND_DATA_RD.L3_MISS Counts demand data reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400001H
OCR.DEMAND_RFO.ANY_RESPONSE Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H
OCR.DEMAND_RFO.DRAM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=784000002H
OCR.DEMAND_RFO.L3_MISS Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400002H
OCR.DEMAND_CODE_RD.ANY_RESPONSE Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H
OCR.DEMAND_CODE_RD.DRAM Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=784000004H
OCR.DEMAND_CODE_RD.L3_MISS Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400004H
OCR.COREWB_M.ANY_RESPONSE Counts modified writebacks from L1 cache and L2 cache that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10008H
OCR.STREAMING_WR.ANY_RESPONSE Counts streaming stores that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H
OCR.SWPF_RD.ANY_RESPONSE Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=14000H
OCR.SWPF_RD.DRAM Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=784004000H
OCR.SWPF_RD.L3_MISS Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84404000H
OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=400000010000H
OCR.FULL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify a full 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800000010000H
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H
OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H
OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0002H
OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0004H
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H
OCR.SWPF_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C4000H
OCR.SWPF_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C4000H
OCR.SWPF_RD.L3_HIT.SNOOP_HITM Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C4000H
OCR.DEMAND_DATA_RD.L3_HIT Counts demand data reads that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H
OCR.DEMAND_RFO.L3_HIT Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0002H
OCR.DEMAND_CODE_RD.L3_HIT Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0004H
OCR.SWPF_RD.L3_HIT Counts L1 data cache software prefetches which include T0/T1/T2 and NTA (except PREFETCHW) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C4000H
OCR.DEMAND_DATA_RD.L3_MISS_LOCAL Counts demand data reads that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400001H
OCR.DEMAND_RFO.L3_MISS_LOCAL Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS] EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400002H