| INST_RETIRED.ANY |
Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. |
IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Architectural Fixed AtRetirement |
| CPU_CLK_UNHALTED.CORE |
Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| CPU_CLK_UNHALTED.THREAD |
Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. |
IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| CPU_CLK_UNHALTED.REF_TSC |
Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2. |
IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural Fixed Speculative |
| BR_INST_RETIRED.ALL_BRANCHES |
Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. |
EventSel=C4H UMask=00H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] Architectural AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES |
Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. |
EventSel=C5H UMask=00H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] Architectural AtRetirement |
| CPU_CLK_UNHALTED.CORE_P |
Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter. |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative |
| CPU_CLK_UNHALTED.REF |
This event is deprecated. Refer to new event CPU_CLK_UNHALTED.REF_TSC_P |
EventSel=3CH UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative Deprecated |
| CPU_CLK_UNHALTED.REF_TSC_P |
Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. |
EventSel=3CH UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative |
| CPU_CLK_UNHALTED.THREAD_P |
Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter. |
EventSel=3CH UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative |
| INST_RETIRED.ANY_P |
Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. |
EventSel=C0H UMask=00H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] Architectural AtRetirement |
| LONGEST_LAT_CACHE.MISS |
Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=41H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative |
| LONGEST_LAT_CACHE.REFERENCE |
Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. |
EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Architectural Speculative |
| ARITH.DIV_ACTIVE |
Counts the number of cycles when any of the floating point or integer dividers are active. |
EventSel=CDH UMask=03H CMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ARITH.FPDIV_ACTIVE |
Counts the number of cycles the floating point divider is in the loop stage. |
EventSel=CDH UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ARITH.FPDIV_UOPS |
Counts the number of floating point divider uops executed per cycle. |
EventSel=CDH UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ARITH.IDIV_ACTIVE |
Counts the number of cycles any of the two integer dividers are active. |
EventSel=CDH UMask=01H CMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ARITH.IDIV_OCCUPANCY |
Counts the number of active integer dividers per cycle. |
EventSel=CDH UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ARITH.IDIV_UOPS |
Counts the number of integer divider uops executed per cycle. |
EventSel=CDH UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| BACLEARS.ANY |
Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. |
EventSel=E6H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| BR_INST_RETIRED.COND |
Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. |
EventSel=C4H UMask=7EH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN |
Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C4H UMask=FEH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH |
Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. |
EventSel=C4H UMask=BFH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.INDIRECT |
Counts the number of near indirect JMP and near indirect CALL branch instructions retired. |
EventSel=C4H UMask=EBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.INDIRECT_CALL |
Counts the number of near indirect CALL branch instructions retired. |
EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.INDIRECT_JMP |
Counts the number of near indirect JMP branch instructions retired. |
EventSel=C4H UMask=EFH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL |
Counts the number of near CALL branch instructions retired. |
EventSel=C4H UMask=F9H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN |
Counts the number of near RET branch instructions retired. |
EventSel=C4H UMask=F7H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN |
Counts the number of near taken branch instructions retired. |
EventSel=C4H UMask=C0H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.REL_CALL |
Counts the number of near relative CALL branch instructions retired. |
EventSel=C4H UMask=FDH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.REL_JMP |
Counts the number of near relative JMP branch instructions retired. |
EventSel=C4H UMask=DFH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_INST_RETIRED.TAKEN |
Counts the number of taken branch instructions retired. |
EventSel=C4H UMask=80H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.COND |
Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C5H UMask=7EH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN |
Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. |
EventSel=C5H UMask=FEH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.INDIRECT |
Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. |
EventSel=C5H UMask=EBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL |
Counts the number of mispredicted near indirect CALL branch instructions retired. |
EventSel=C5H UMask=FBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_JMP |
Counts the number of mispredicted near indirect JMP branch instructions retired. |
EventSel=C5H UMask=EFH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN |
Counts the number of mispredicted near taken branch instructions retired. |
EventSel=C5H UMask=80H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BR_MISP_RETIRED.RETURN |
Counts the number of mispredicted near RET branch instructions retired. |
EventSel=C5H UMask=F7H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| BTCLEAR.ANY |
Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch. |
EventSel=E8H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| CORE_REJECT_L2Q.ANY |
Counts the number of core requests (demand and L1 prefetchers) rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ) but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a cores dirty eviction when the address conflicts with incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis. |
EventSel=31H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=08H UMask=0EH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=49H UMask=0EH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ICACHE.ACCESSES |
Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. |
EventSel=80H UMask=03H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ICACHE.MISSES |
Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. |
EventSel=80H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ITLB_MISSES.MISS_CAUSED_WALK |
Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs. |
EventSel=85H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ITLB_MISSES.PDE_CACHE_MISS |
Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache. |
EventSel=85H UMask=80H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| ITLB_MISSES.WALK_COMPLETED |
Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. |
EventSel=85H UMask=0EH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| L2_REJECT_XQ.ANY |
Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition, which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims). |
EventSel=30H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| L2_REQUEST.ALL |
Counts the total number of L2 Cache Accesses, includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis. |
EventSel=24H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| L2_REQUEST.HIT |
Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis. |
EventSel=24H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| L2_REQUEST.MISS |
Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis. |
EventSel=24H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_BLOCKS.ADDRESS_ALIAS |
Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. |
EventSel=03H UMask=04H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| LD_BLOCKS.DATA_UNKNOWN |
Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. |
EventSel=03H UMask=01H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| LD_HEAD.ANY |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block. |
EventSel=05H UMask=7FH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.ANY_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. |
EventSel=05H UMask=FFH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.DTLB_MISS |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss. |
EventSel=05H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.DTLB_MISS_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss. |
EventSel=05H UMask=90H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.L1_BOUND_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. |
EventSel=05H UMask=F4H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.L1_MISS |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss. |
EventSel=05H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.L1_MISS_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss. |
EventSel=05H UMask=81H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.OTHER |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases such as pipeline conflicts, fences, etc. |
EventSel=05H UMask=40H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.OTHER_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc. |
EventSel=05H UMask=C0H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.PGWALK |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk. |
EventSel=05H UMask=20H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.PGWALK_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk. |
EventSel=05H UMask=A0H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.ST_ADDR |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store data forward block. |
EventSel=05H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.ST_ADDR_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match. |
EventSel=05H UMask=84H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.WCB_FULL |
Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress. |
EventSel=05H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| LD_HEAD.WCB_FULL_AT_RET |
Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress. |
EventSel=05H UMask=82H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.DISAMBIGUATION |
Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. |
EventSel=C3H UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.FAST |
Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode. |
EventSel=C3H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.FPC_VIRTUAL_TRAP |
Counts the number of virtual traps taken. |
EventSel=C3H UMask=40H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.FP_ASSIST |
Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. |
EventSel=C3H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING |
Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. |
EventSel=C3H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.MRN_NUKE |
Counts the number of machines clears due to memory renaming. |
EventSel=C3H UMask=80H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.PAGE_FAULT |
Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. |
EventSel=C3H UMask=20H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MACHINE_CLEARS.SMC |
Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. |
EventSel=C3H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.IFETCH |
Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). |
EventSel=34H UMask=38H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.IFETCH_DRAM_HIT |
Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM). |
EventSel=34H UMask=20H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.IFETCH_L2_HIT |
Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache. |
EventSel=34H UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.IFETCH_L2_MISS |
Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache. |
EventSel=34H UMask=30H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.IFETCH_LLC_HIT |
Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M. |
EventSel=34H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.LOAD |
Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). |
EventSel=34H UMask=07H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.LOAD_DRAM_HIT |
Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM). |
EventSel=34H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.LOAD_L2_HIT |
Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache. |
EventSel=34H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.LOAD_L2_MISS |
Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache. |
EventSel=34H UMask=06H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_BOUND_STALLS.LOAD_LLC_HIT |
Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M. |
EventSel=34H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_LOAD_UOPS_RETIRED.DRAM_HIT |
Counts the number of load uops retired that hit in DRAM. |
EventSel=D1H UMask=80H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.HITM |
Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module. |
EventSel=D1H UMask=20H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_HIT |
Counts the number of load uops retired that hit in the L1 data cache. |
EventSel=D1H UMask=01H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_MISS |
Counts the number of load uops retired that miss in the L1 data cache. |
EventSel=D1H UMask=08H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_HIT |
Counts the number of load uops retired that hit in the L2 cache. |
EventSel=D1H UMask=02H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_MISS |
Counts the number of load uops retired that miss in the L2 cache. |
EventSel=D1H UMask=10H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT |
Counts the number of load uops retired that hit in the L3 cache. |
EventSel=D1H UMask=04H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED_MISC.HIT_E_F |
Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required, and non-modified data was forwarded. |
EventSel=D2H UMask=40H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_LOAD_UOPS_RETIRED_MISC.L3_MISS |
Counts the number of load uops retired that miss in the L3 cache. |
EventSel=D2H UMask=20H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_SCHEDULER_BLOCK.ALL |
Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. |
EventSel=04H UMask=07H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_SCHEDULER_BLOCK.LD_BUF |
Counts the number of cycles that uops are blocked due to a load buffer full condition. |
EventSel=04H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_SCHEDULER_BLOCK.RSV |
Counts the number of cycles that uops are blocked due to an RSV full condition. |
EventSel=04H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_SCHEDULER_BLOCK.ST_BUF |
Counts the number of cycles that uops are blocked due to a store buffer full condition. |
EventSel=04H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MEM_UOPS_RETIRED.ALL |
Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) |
EventSel=D0H UMask=83H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.ALL_LOADS |
Counts the total number of load uops retired. |
EventSel=D0H UMask=81H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.ALL_STORES |
Counts the total number of store uops retired. |
EventSel=D0H UMask=82H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024 |
Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128 |
Counts the number of tagged load uops retired that exceed the latency threshold of 128. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16 |
Counts the number of tagged load uops retired that exceed the latency threshold of 16. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048 |
Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256 |
Counts the number of tagged load uops retired that exceed the latency threshold of 256. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32 |
Counts the number of tagged load uops retired that exceed the latency threshold of 32. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4 |
Counts the number of tagged load uops retired that exceed the latency threshold of 4. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512 |
Counts the number of tagged load uops retired that exceed the latency threshold of 512. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64 |
Counts the number of tagged load uops retired that exceed the latency threshold of 64. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8 |
Counts the number of tagged load uops retired that exceed the latency threshold of 8. Only counts with PEBS enabled. |
EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=0,1 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOCK_LOADS |
Counts the number of load uops retired that performed one or more locks. |
EventSel=D0H UMask=21H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT |
Counts the number of memory uops retired that were splits. |
EventSel=D0H UMask=43H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_LOADS |
Counts the number of retired split load uops. |
EventSel=D0H UMask=41H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_STORES |
Counts the number of retired split store uops. |
EventSel=D0H UMask=42H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS |
Counts the total number of load and store uops retired that missed in the second level TLB. |
EventSel=D0H UMask=13H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS |
Counts the number of load ops retired that miss in the second Level TLB. |
EventSel=D0H UMask=11H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.STLB_MISS_STORES |
Counts the number of store ops retired that miss in the second level TLB. |
EventSel=D0H UMask=12H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MEM_UOPS_RETIRED.STORE_LATENCY |
Counts the number of stores uops retired. |
EventSel=D0H UMask=06H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement |
| MISC_RETIRED.LBR_INSERTS |
Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. This event is PDIR on GP0 and NPEBS on all other GPs [This event is alias to LBR_INSERTS.ANY] |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| MISC_RETIRED1.CL_INST |
Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. |
EventSel=E0H UMask=FFH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MISC_RETIRED1.LFENCE |
Counts the number of LFENCE instructions retired. |
EventSel=E0H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MISC_RETIRED2.KEYLOCKER_ACCESS |
Counts the number of accesses to KeyLocker cache. |
EventSel=E1H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| MISC_RETIRED2.KEYLOCKER_MISS |
Counts the number of misses to KeyLocker cache. |
EventSel=E1H UMask=11H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| SERIALIZATION.C01_MS_SCB |
Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state) |
EventSel=75H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| SERIALIZATION.COLOR_STALLS |
Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use. |
EventSel=75H UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| SERIALIZATION.NON_C01_MS_SCB |
Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE. |
EventSel=75H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BAD_SPECULATION.ALL |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. |
EventSel=73H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BAD_SPECULATION.FASTNUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears. |
EventSel=73H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS |
Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. |
EventSel=73H UMask=03H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BAD_SPECULATION.MISPREDICT |
Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts. |
EventSel=73H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BAD_SPECULATION.NUKE |
Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). |
EventSel=73H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.ALL |
Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls. |
EventSel=74H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS |
Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions. |
EventSel=74H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops. |
EventSel=74H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER |
Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops. |
EventSel=74H UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.REGISTER |
Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls). |
EventSel=74H UMask=20H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.REORDER_BUFFER |
Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls). |
EventSel=74H UMask=40H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_BE_BOUND.SERIALIZATION |
Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS). |
EventSel=74H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.ALL |
Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls. |
EventSel=71H UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_DETECT |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. |
EventSel=71H UMask=02H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_RESTEER |
Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch. |
EventSel=71H UMask=40H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.CISC |
Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS). |
EventSel=71H UMask=01H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.DECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls. |
EventSel=71H UMask=08H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH |
Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. |
EventSel=71H UMask=8DH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_LATENCY |
Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. |
EventSel=71H UMask=72H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.ICACHE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses. |
EventSel=71H UMask=20H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.ITLB |
Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses. |
EventSel=71H UMask=10H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.OTHER |
Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized. |
EventSel=71H UMask=80H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_FE_BOUND.PREDECODE |
Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes. |
EventSel=71H UMask=04H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| TOPDOWN_RETIRING.ALL |
Counts the total number of consumed retirement slots. |
EventSel=C2H UMask=00H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| UOPS_ISSUED.ANY |
Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. |
EventSel=0EH UMask=00H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative |
| UOPS_RETIRED.ALL |
Counts the total number of uops retired. |
EventSel=C2H UMask=00H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| UOPS_RETIRED.FPDIV |
Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). |
EventSel=C2H UMask=08H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| UOPS_RETIRED.IDIV |
Counts the number of integer divide uops retired. |
EventSel=C2H UMask=10H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| UOPS_RETIRED.MS |
Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. |
EventSel=C2H UMask=01H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| UOPS_RETIRED.X87 |
Counts the number of x87 uops retired, includes those in MS flows. |
EventSel=C2H UMask=02H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement |
| ARITH.DIV_OCCUPANCY |
This event is deprecated. |
EventSel=CDH UMask=03H Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative Deprecated |
| ARITH.DIV_UOPS |
This event is deprecated. |
EventSel=CDH UMask=0CH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative Deprecated |
| BR_INST_RETIRED.CALL |
This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL |
EventSel=C4H UMask=F9H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_INST_RETIRED.IND_CALL |
This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL |
EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_INST_RETIRED.JCC |
This event is deprecated. Refer to new event BR_INST_RETIRED.COND |
EventSel=C4H UMask=7EH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_INST_RETIRED.NON_RETURN_IND |
This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT |
EventSel=C4H UMask=EBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_INST_RETIRED.RETURN |
This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN |
EventSel=C4H UMask=F7H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_INST_RETIRED.TAKEN_JCC |
This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN |
EventSel=C4H UMask=FEH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_MISP_RETIRED.IND_CALL |
This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL |
EventSel=C5H UMask=FBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_MISP_RETIRED.JCC |
This event is deprecated. Refer to new event BR_MISP_RETIRED.COND |
EventSel=C5H UMask=7EH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_MISP_RETIRED.NON_RETURN_IND |
This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT |
EventSel=C5H UMask=EBH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| BR_MISP_RETIRED.TAKEN_JCC |
This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN |
EventSel=C5H UMask=FEH Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| LBR_INSERTS.ANY |
This event is deprecated. [This event is alias to MISC_RETIRED.LBR_INSERTS] |
EventSel=E4H UMask=01H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| LD_BLOCKS.4K_ALIAS |
This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS |
EventSel=03H UMask=04H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| MACHINE_CLEARS.SLOW |
This event is deprecated. |
EventSel=C3H UMask=6FH Counter=0,1,2,3,4,5 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5] Speculative Deprecated |
| MEM_UOPS_RETIRED.DTLB_MISS |
This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS |
EventSel=D0H UMask=13H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| MEM_UOPS_RETIRED.DTLB_MISS_LOADS |
This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_LOADS |
EventSel=D0H UMask=11H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement Deprecated |
| MEM_UOPS_RETIRED.DTLB_MISS_STORES |
This event is deprecated. Refer to new event MEM_UOPS_RETIRED.STLB_MISS_STORES |
EventSel=D0H UMask=12H Counter=0,1,2,3,4,5 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5] AtRetirement Deprecated |