| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=ANY_RESPONSE |
Counts demand cacheable data reads of full cache lineshave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT |
Counts demand cacheable data reads of full cache lineshit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts demand cacheable data reads of full cache linestrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts demand cacheable data reads of full cache linesmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=OUTSTANDING |
Counts demand cacheable data reads of full cache lines that are outstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000001H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=ANY_RESPONSE |
Counts demand reads for ownership (RFO) requests generated by a write to full data cache linehave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT |
Counts demand reads for ownership (RFO) requests generated by a write to full data cache linehit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts demand reads for ownership (RFO) requests generated by a write to full data cache linetrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_MISS.HITM_OTHER_CORE |
Counts demand reads for ownership (RFO) requests generated by a write to full data cache linemiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=OUTSTANDING |
Counts demand reads for ownership (RFO) requests generated by a write to full data cache lineoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000002H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=ANY_RESPONSE |
Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cachehave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT |
Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cachehit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cachetrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cachemiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=OUTSTANDING |
Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cacheoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000004H |
| OFFCORE_RESPONSE:request=COREWB: response=ANY_RESPONSE |
Counts the number of writeback transactions caused by L1 or L2 cache evictionshave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10008H |
| OFFCORE_RESPONSE:request=COREWB: response=L2_HIT |
Counts the number of writeback transactions caused by L1 or L2 cache evictionshit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40008H |
| OFFCORE_RESPONSE:request=COREWB: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts the number of writeback transactions caused by L1 or L2 cache evictionstrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L2_MISS.HITM_OTHER_CORE |
Counts the number of writeback transactions caused by L1 or L2 cache evictionsmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000008H |
| OFFCORE_RESPONSE:request=COREWB: response=OUTSTANDING |
Counts the number of writeback transactions caused by L1 or L2 cache evictionsoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000008H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=ANY_RESPONSE |
Counts data cacheline reads generated by hardware L2 cache prefetcherhave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L2_HIT |
Counts data cacheline reads generated by hardware L2 cache prefetcherhit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data cacheline reads generated by hardware L2 cache prefetchertrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts data cacheline reads generated by hardware L2 cache prefetchermiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=OUTSTANDING |
Counts data cacheline reads generated by hardware L2 cache prefetcheroutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000010H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=ANY_RESPONSE |
Counts reads for ownership (RFO) requests generated by L2 cache prefetcherhave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT |
Counts reads for ownership (RFO) requests generated by L2 cache prefetcherhit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts reads for ownership (RFO) requests generated by L2 cache prefetchertrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_MISS.HITM_OTHER_CORE |
Counts reads for ownership (RFO) requests generated by L2 cache prefetchermiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=OUTSTANDING |
Counts reads for ownership (RFO) requests generated by L2 cache prefetcheroutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000020H |
| OFFCORE_RESPONSE:request=BUS_LOCKS: response=ANY_RESPONSE |
Counts bus lock and split lock requestshave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H |
| OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT |
Counts bus lock and split lock requestshit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40400H |
| OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts bus lock and split lock requeststrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000400H |
| OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_MISS.HITM_OTHER_CORE |
Counts bus lock and split lock requestsmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000400H |
| OFFCORE_RESPONSE:request=BUS_LOCKS: response=OUTSTANDING |
Counts bus lock and split lock requestsoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000400H |
| OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=ANY_RESPONSE |
Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writeshave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=L2_HIT |
Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writeshit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40800H |
| OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writestrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000800H |
| OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=L2_MISS.HITM_OTHER_CORE |
Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writesmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000800H |
| OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=OUTSTANDING |
Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writesoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000800H |
| OFFCORE_RESPONSE:request=SW_PREFETCH: response=ANY_RESPONSE |
Counts data cache lines requests by software prefetch instructionshave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=11000H |
| OFFCORE_RESPONSE:request=SW_PREFETCH: response=L2_HIT |
Counts data cache lines requests by software prefetch instructionshit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=41000H |
| OFFCORE_RESPONSE:request=SW_PREFETCH: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data cache lines requests by software prefetch instructionstrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200001000H |
| OFFCORE_RESPONSE:request=SW_PREFETCH: response=L2_MISS.HITM_OTHER_CORE |
Counts data cache lines requests by software prefetch instructionsmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000001000H |
| OFFCORE_RESPONSE:request=SW_PREFETCH: response=OUTSTANDING |
Counts data cache lines requests by software prefetch instructionsoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000001000H |
| OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=ANY_RESPONSE |
Counts data cache line reads generated by hardware L1 data cache prefetcherhave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=12000H |
| OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT |
Counts data cache line reads generated by hardware L1 data cache prefetcherhit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=42000H |
| OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data cache line reads generated by hardware L1 data cache prefetchertrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200002000H |
| OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts data cache line reads generated by hardware L1 data cache prefetchermiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000002000H |
| OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=OUTSTANDING |
Counts data cache line reads generated by hardware L1 data cache prefetcheroutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000002000H |
| OFFCORE_RESPONSE:request=STREAMING_STORES: response=ANY_RESPONSE |
Counts any data writes to uncacheable write combining (USWC) memory regionhave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=14800H |
| OFFCORE_RESPONSE:request=STREAMING_STORES: response=L2_HIT |
Counts any data writes to uncacheable write combining (USWC) memory regionhit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=44800H |
| OFFCORE_RESPONSE:request=STREAMING_STORES: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts any data writes to uncacheable write combining (USWC) memory regiontrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200004800H |
| OFFCORE_RESPONSE:request=STREAMING_STORES: response=L2_MISS.HITM_OTHER_CORE |
Counts any data writes to uncacheable write combining (USWC) memory regionmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000004800H |
| OFFCORE_RESPONSE:request=STREAMING_STORES: response=OUTSTANDING |
Counts any data writes to uncacheable write combining (USWC) memory regionoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000004800H |
| OFFCORE_RESPONSE:request=ANY_REQUEST: response=ANY_RESPONSE |
Counts requests to the uncore subsystemhave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H |
| OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT |
Counts requests to the uncore subsystemhit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=48000H |
| OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts requests to the uncore subsystemtrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200008000H |
| OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_MISS.HITM_OTHER_CORE |
Counts requests to the uncore subsystemmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000008000H |
| OFFCORE_RESPONSE:request=ANY_REQUEST: response=OUTSTANDING |
Counts requests to the uncore subsystemoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000008000H |
| OFFCORE_RESPONSE:request=ANY_PF_DATA_RD: response=ANY_RESPONSE |
Counts data reads generated by L1 or L2 prefetchershave any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13010H |
| OFFCORE_RESPONSE:request=ANY_PF_DATA_RD: response=L2_HIT |
Counts data reads generated by L1 or L2 prefetchershit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=43010H |
| OFFCORE_RESPONSE:request=ANY_PF_DATA_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data reads generated by L1 or L2 prefetcherstrue miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200003010H |
| OFFCORE_RESPONSE:request=ANY_PF_DATA_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts data reads generated by L1 or L2 prefetchersmiss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000003010H |
| OFFCORE_RESPONSE:request=ANY_PF_DATA_RD: response=OUTSTANDING |
Counts data reads generated by L1 or L2 prefetchersoutstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000003010H |
| OFFCORE_RESPONSE:request=ANY_DATA_RD: response=ANY_RESPONSE |
Counts data reads (demand & prefetch)have any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13091H |
| OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT |
Counts data reads (demand & prefetch)hit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=43091H |
| OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data reads (demand & prefetch)true miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200003091H |
| OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_MISS.HITM_OTHER_CORE |
Counts data reads (demand & prefetch)miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000003091H |
| OFFCORE_RESPONSE:request=ANY_DATA_RD: response=OUTSTANDING |
Counts data reads (demand & prefetch)outstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000003091H |
| OFFCORE_RESPONSE:request=ANY_RFO: response=ANY_RESPONSE |
Counts reads for ownership (RFO) requests (demand & prefetch)have any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10022H |
| OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT |
Counts reads for ownership (RFO) requests (demand & prefetch)hit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40022H |
| OFFCORE_RESPONSE:request=ANY_RFO: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts reads for ownership (RFO) requests (demand & prefetch)true miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000022H |
| OFFCORE_RESPONSE:request=ANY_RFO: response=L2_MISS.HITM_OTHER_CORE |
Counts reads for ownership (RFO) requests (demand & prefetch)miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000022H |
| OFFCORE_RESPONSE:request=ANY_RFO: response=OUTSTANDING |
Counts reads for ownership (RFO) requests (demand & prefetch)outstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000022H |
| OFFCORE_RESPONSE:request=ANY_READ: response=ANY_RESPONSE |
Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)have any transaction responses from the uncore subsystem. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=132B7H |
| OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT |
Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)hit the L2 cache. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=432B7H |
| OFFCORE_RESPONSE:request=ANY_READ: response=L2_MISS.SNOOP_MISS_OR_NO_SNOOP_NEEDED |
Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)true miss for the L2 cache with a snoop miss in the other processor module. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000032B7H |
| OFFCORE_RESPONSE:request=ANY_READ: response=L2_MISS.HITM_OTHER_CORE |
Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)miss the L2 cache with a snoop hit in the other processor module, data forwarding is required. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000032B7H |
| OFFCORE_RESPONSE:request=ANY_READ: response=OUTSTANDING |
Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch)outstanding, per cycle, from the time of the L2 miss to when any response is received. |
EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=40000032B7H |