| INST_RETIRED.ANY |
Instructions retired. |
IA32_FIXED_CTR0 Architectural, Fixed |
| CPU_CLK_UNHALTED.CORE |
Core cycles when core is not halted |
IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.REF |
Reference cycles when core is not halted. |
IA32_FIXED_CTR2 Architectural, Fixed |
| BR_INST_RETIRED.ANY |
Retired branch instructions. |
EventSel=C4H UMask=00H CMask=0 Counter=0,1 Architectural |
| BR_INST_RETIRED.MISPRED |
Retired mispredicted branch instructions (precise event). |
EventSel=C5H UMask=00H CMask=0 Counter=0,1 Architectural |
| CPU_CLK_UNHALTED.BUS |
Bus cycles when core is not halted |
EventSel=3CH UMask=01H CMask=0 Counter=0,1 Architectural |
| CPU_CLK_UNHALTED.CORE_P |
Core cycles when core is not halted |
EventSel=3CH UMask=00H CMask=0 Counter=0,1 Architectural |
| INST_RETIRED.ANY_P |
Instructions retired (precise event). |
EventSel=C0H UMask=00H CMask=0 Counter=0,1 Architectural |
| L2_RQSTS.SELF.DEMAND.I_STATE |
L2 cache demand requests from this core that missed the L2 |
EventSel=2EH UMask=41H CMask=0 Counter=0,1 Architectural |
| L2_RQSTS.SELF.DEMAND.MESI |
L2 cache demand requests from this core |
EventSel=2EH UMask=4FH CMask=0 Counter=0,1 Architectural |
| BACLEARS.ANY |
BACLEARS asserted. |
EventSel=E6H UMask=01H CMask=0 Counter=0,1 |
| BOGUS_BR |
Bogus branches |
EventSel=E4H UMask=01H CMask=0 Counter=0,1 |
| BR_INST_DECODED |
Branch instructions decoded |
EventSel=E0H UMask=01H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.ANY1 |
Retired branch instructions. |
EventSel=C4H UMask=0FH CMask=0 Counter=0,1 |
| BR_INST_RETIRED.MISPRED.PS |
Retired mispredicted branch instructions. |
EventSel=C5H UMask=00H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.MISPRED_NOT_TAKEN |
Retired branch instructions that were mispredicted not-taken. |
EventSel=C4H UMask=02H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.MISPRED_TAKEN |
Retired branch instructions that were mispredicted taken. |
EventSel=C4H UMask=08H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.PRED_NOT_TAKEN |
Retired branch instructions that were predicted not-taken. |
EventSel=C4H UMask=01H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.PRED_TAKEN |
Retired branch instructions that were predicted taken. |
EventSel=C4H UMask=04H CMask=0 Counter=0,1 |
| BR_INST_RETIRED.TAKEN |
Retired taken branch instructions. |
EventSel=C4H UMask=0CH CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.COND |
All macro conditional branch instructions. |
EventSel=88H UMask=01H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.COND_TAKEN |
Only taken macro conditional branch instructions |
EventSel=88H UMask=41H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.DIR_CALL |
All non-indirect calls |
EventSel=88H UMask=10H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.IND |
All indirect branches that are not calls. |
EventSel=88H UMask=04H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.IND_CALL |
All indirect calls, including both register and memory indirect. |
EventSel=88H UMask=20H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.RET |
All indirect branches that have a return mnemonic |
EventSel=88H UMask=08H CMask=0 Counter=0,1 |
| BR_INST_TYPE_RETIRED.UNCOND |
All macro unconditional branch instructions, excluding calls and indirects |
EventSel=88H UMask=02H CMask=0 Counter=0,1 |
| BR_MISSP_TYPE_RETIRED.COND |
Mispredicted cond branch instructions retired |
EventSel=89H UMask=01H CMask=0 Counter=0,1 |
| BR_MISSP_TYPE_RETIRED.COND_TAKEN |
Mispredicted and taken cond branch instructions retired |
EventSel=89H UMask=11H CMask=0 Counter=0,1 |
| BR_MISSP_TYPE_RETIRED.IND |
Mispredicted ind branches that are not calls |
EventSel=89H UMask=02H CMask=0 Counter=0,1 |
| BR_MISSP_TYPE_RETIRED.IND_CALL |
Mispredicted indirect calls, including both register and memory indirect. |
EventSel=89H UMask=08H CMask=0 Counter=0,1 |
| BR_MISSP_TYPE_RETIRED.RETURN |
Mispredicted return branches |
EventSel=89H UMask=04H CMask=0 Counter=0,1 |
| BUS_BNR_DRV.ALL_AGENTS |
Number of Bus Not Ready signals asserted. |
EventSel=61H UMask=20H CMask=0 Counter=0,1 |
| BUS_BNR_DRV.THIS_AGENT |
Number of Bus Not Ready signals asserted. |
EventSel=61H UMask=00H CMask=0 Counter=0,1 |
| BUS_DATA_RCV.SELF |
Bus cycles while processor receives data. |
EventSel=64H UMask=40H CMask=0 Counter=0,1 |
| BUS_DRDY_CLOCKS.ALL_AGENTS |
Bus cycles when data is sent on the bus. |
EventSel=62H UMask=20H CMask=0 Counter=0,1 |
| BUS_DRDY_CLOCKS.THIS_AGENT |
Bus cycles when data is sent on the bus. |
EventSel=62H UMask=00H CMask=0 Counter=0,1 |
| BUS_HIT_DRV.ALL_AGENTS |
HIT signal asserted. |
EventSel=7AH UMask=20H CMask=0 Counter=0,1 |
| BUS_HIT_DRV.THIS_AGENT |
HIT signal asserted. |
EventSel=7AH UMask=00H CMask=0 Counter=0,1 |
| BUS_HITM_DRV.ALL_AGENTS |
HITM signal asserted. |
EventSel=7BH UMask=20H CMask=0 Counter=0,1 |
| BUS_HITM_DRV.THIS_AGENT |
HITM signal asserted. |
EventSel=7BH UMask=00H CMask=0 Counter=0,1 |
| BUS_IO_WAIT.SELF |
IO requests waiting in the bus queue. |
EventSel=7FH UMask=40H CMask=0 Counter=0,1 |
| BUS_LOCK_CLOCKS.ALL_AGENTS |
Bus cycles when a LOCK signal is asserted. |
EventSel=63H UMask=E0H CMask=0 Counter=0,1 |
| BUS_LOCK_CLOCKS.SELF |
Bus cycles when a LOCK signal is asserted. |
EventSel=63H UMask=40H CMask=0 Counter=0,1 |
| BUS_REQUEST_OUTSTANDING.ALL_AGENTS |
Outstanding cacheable data read bus requests duration. |
EventSel=60H UMask=E0H CMask=0 Counter=0,1 |
| BUS_REQUEST_OUTSTANDING.SELF |
Outstanding cacheable data read bus requests duration. |
EventSel=60H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_ANY.ALL_AGENTS |
All bus transactions. |
EventSel=70H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_ANY.SELF |
All bus transactions. |
EventSel=70H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_BRD.ALL_AGENTS |
Burst read bus transactions. |
EventSel=65H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_BRD.SELF |
Burst read bus transactions. |
EventSel=65H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_BURST.ALL_AGENTS |
Burst (full cache-line) bus transactions. |
EventSel=6EH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_BURST.SELF |
Burst (full cache-line) bus transactions. |
EventSel=6EH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_DEF.ALL_AGENTS |
Deferred bus transactions. |
EventSel=6DH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_DEF.SELF |
Deferred bus transactions. |
EventSel=6DH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_IFETCH.ALL_AGENTS |
Instruction-fetch bus transactions. |
EventSel=68H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_IFETCH.SELF |
Instruction-fetch bus transactions. |
EventSel=68H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_INVAL.ALL_AGENTS |
Invalidate bus transactions. |
EventSel=69H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_INVAL.SELF |
Invalidate bus transactions. |
EventSel=69H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_IO.ALL_AGENTS |
IO bus transactions. |
EventSel=6CH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_IO.SELF |
IO bus transactions. |
EventSel=6CH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_MEM.ALL_AGENTS |
Memory bus transactions. |
EventSel=6FH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_MEM.SELF |
Memory bus transactions. |
EventSel=6FH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_P.ALL_AGENTS |
Partial bus transactions. |
EventSel=6BH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_P.SELF |
Partial bus transactions. |
EventSel=6BH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_PWR.ALL_AGENTS |
Partial write bus transaction. |
EventSel=6AH UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_PWR.SELF |
Partial write bus transaction. |
EventSel=6AH UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_RFO.ALL_AGENTS |
RFO bus transactions. |
EventSel=66H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_RFO.SELF |
RFO bus transactions. |
EventSel=66H UMask=40H CMask=0 Counter=0,1 |
| BUS_TRANS_WB.ALL_AGENTS |
Explicit writeback bus transactions. |
EventSel=67H UMask=E0H CMask=0 Counter=0,1 |
| BUS_TRANS_WB.SELF |
Explicit writeback bus transactions. |
EventSel=67H UMask=40H CMask=0 Counter=0,1 |
| BUSQ_EMPTY.SELF |
Bus queue is empty. |
EventSel=7DH UMask=40H CMask=0 Counter=0,1 |
| CYCLES_DIV_BUSY |
Cycles the divider is busy. |
EventSel=14H UMask=01H CMask=0 Counter=0,1 |
| CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED |
Cycles during which instruction fetches are stalled. |
EventSel=86H UMask=01H CMask=0 Counter=0,1 |
| CYCLES_INT_MASKED.CYCLES_INT_MASKED |
Cycles during which interrupts are disabled. |
EventSel=C6H UMask=01H CMask=0 Counter=0,1 |
| CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED |
Cycles during which interrupts are pending and disabled. |
EventSel=C6H UMask=02H CMask=0 Counter=0,1 |
| DATA_TLB_MISSES.DTLB_MISS |
Memory accesses that missed the DTLB. |
EventSel=08H UMask=07H CMask=0 Counter=0,1 |
| DATA_TLB_MISSES.DTLB_MISS_LD |
DTLB misses due to load operations. |
EventSel=08H UMask=05H CMask=0 Counter=0,1 |
| DATA_TLB_MISSES.DTLB_MISS_ST |
DTLB misses due to store operations. |
EventSel=08H UMask=06H CMask=0 Counter=0,1 |
| DATA_TLB_MISSES.L0_DTLB_MISS_LD |
L0 DTLB misses due to load operations. |
EventSel=08H UMask=09H CMask=0 Counter=0,1 |
| DATA_TLB_MISSES.L0_DTLB_MISS_ST |
L0 DTLB misses due to store operations |
EventSel=08H UMask=0AH CMask=0 Counter=0,1 |
| DECODE_STALL.IQ_FULL |
Decode stall due to IQ full |
EventSel=87H UMask=02H CMask=0 Counter=0,1 |
| DECODE_STALL.PFB_EMPTY |
Decode stall due to PFB empty |
EventSel=87H UMask=01H CMask=0 Counter=0,1 |
| DISPATCH_BLOCKED.ANY |
Memory cluster signals to block micro-op dispatch for any reason |
EventSel=09H UMask=20H CMask=0 Counter=0,1 |
| DIV.AR |
Divide operations retired |
EventSel=13H UMask=81H CMask=0 Counter=0,1 |
| DIV.S |
Divide operations executed. |
EventSel=13H UMask=01H CMask=0 Counter=0,1 |
| EIST_TRANS |
Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions |
EventSel=3AH UMask=00H CMask=0 Counter=0,1 |
| EXT_SNOOP.ALL_AGENTS.ANY |
External snoops. |
EventSel=77H UMask=2BH CMask=0 Counter=0,1 |
| EXT_SNOOP.ALL_AGENTS.CLEAN |
External snoops. |
EventSel=77H UMask=21H CMask=0 Counter=0,1 |
| EXT_SNOOP.ALL_AGENTS.HIT |
External snoops. |
EventSel=77H UMask=22H CMask=0 Counter=0,1 |
| EXT_SNOOP.ALL_AGENTS.HITM |
External snoops. |
EventSel=77H UMask=28H CMask=0 Counter=0,1 |
| EXT_SNOOP.THIS_AGENT.ANY |
External snoops. |
EventSel=77H UMask=0BH CMask=0 Counter=0,1 |
| EXT_SNOOP.THIS_AGENT.CLEAN |
External snoops. |
EventSel=77H UMask=01H CMask=0 Counter=0,1 |
| EXT_SNOOP.THIS_AGENT.HIT |
External snoops. |
EventSel=77H UMask=02H CMask=0 Counter=0,1 |
| EXT_SNOOP.THIS_AGENT.HITM |
External snoops. |
EventSel=77H UMask=08H CMask=0 Counter=0,1 |
| FP_ASSIST.AR |
Floating point assists for retired operations. |
EventSel=11H UMask=81H CMask=0 Counter=0,1 |
| FP_ASSIST.S |
Floating point assists. |
EventSel=11H UMask=01H CMask=0 Counter=0,1 |
| HW_INT_RCV |
Hardware interrupts received. |
EventSel=C8H UMask=00H CMask=0 Counter=0,1 |
| ICACHE.ACCESSES |
Instruction fetches. |
EventSel=80H UMask=03H CMask=0 Counter=0,1 |
| ICACHE.HIT |
Icache hit |
EventSel=80H UMask=01H CMask=0 Counter=0,1 |
| ICACHE.MISSES |
Icache miss |
EventSel=80H UMask=02H CMask=0 Counter=0,1 |
| ITLB.FLUSH |
ITLB flushes. |
EventSel=82H UMask=04H CMask=0 Counter=0,1 |
| ITLB.HIT |
ITLB hits. |
EventSel=82H UMask=01H CMask=0 Counter=0,1 |
| ITLB.MISSES |
ITLB misses. |
EventSel=82H UMask=02H CMask=0 Counter=0,1 |
| L1D_CACHE.ALL_CACHE_REF |
L1 Data Cacheable reads and writes |
EventSel=40H UMask=A3H CMask=0 Counter=0,1 |
| L1D_CACHE.ALL_REF |
L1 Data reads and writes |
EventSel=40H UMask=83H CMask=0 Counter=0,1 |
| L1D_CACHE.EVICT |
Modified cache lines evicted from the L1 data cache |
EventSel=40H UMask=10H CMask=0 Counter=0,1 |
| L1D_CACHE.LD |
L1 Cacheable Data Reads |
EventSel=40H UMask=A1H CMask=0 Counter=0,1 |
| L1D_CACHE.REPL |
L1 Data line replacements |
EventSel=40H UMask=08H CMask=0 Counter=0,1 |
| L1D_CACHE.REPLM |
Modified cache lines allocated in the L1 data cache |
EventSel=40H UMask=48H CMask=0 Counter=0,1 |
| L1D_CACHE.ST |
L1 Cacheable Data Writes |
EventSel=40H UMask=A2H CMask=0 Counter=0,1 |
| L2_ADS.SELF |
Cycles L2 address bus is in use. |
EventSel=21H UMask=40H CMask=0 Counter=0,1 |
| L2_DATA_RQSTS.SELF.E_STATE |
All data requests from the L1 data cache |
EventSel=2CH UMask=44H CMask=0 Counter=0,1 |
| L2_DATA_RQSTS.SELF.I_STATE |
All data requests from the L1 data cache |
EventSel=2CH UMask=41H CMask=0 Counter=0,1 |
| L2_DATA_RQSTS.SELF.M_STATE |
All data requests from the L1 data cache |
EventSel=2CH UMask=48H CMask=0 Counter=0,1 |
| L2_DATA_RQSTS.SELF.MESI |
All data requests from the L1 data cache |
EventSel=2CH UMask=4FH CMask=0 Counter=0,1 |
| L2_DATA_RQSTS.SELF.S_STATE |
All data requests from the L1 data cache |
EventSel=2CH UMask=42H CMask=0 Counter=0,1 |
| L2_DBUS_BUSY.SELF |
Cycles the L2 cache data bus is busy. |
EventSel=22H UMask=40H CMask=0 Counter=0,1 |
| L2_DBUS_BUSY_RD.SELF |
Cycles the L2 transfers data to the core. |
EventSel=23H UMask=40H CMask=0 Counter=0,1 |
| L2_IFETCH.SELF.E_STATE |
L2 cacheable instruction fetch requests |
EventSel=28H UMask=44H CMask=0 Counter=0,1 |
| L2_IFETCH.SELF.I_STATE |
L2 cacheable instruction fetch requests |
EventSel=28H UMask=41H CMask=0 Counter=0,1 |
| L2_IFETCH.SELF.M_STATE |
L2 cacheable instruction fetch requests |
EventSel=28H UMask=48H CMask=0 Counter=0,1 |
| L2_IFETCH.SELF.MESI |
L2 cacheable instruction fetch requests |
EventSel=28H UMask=4FH CMask=0 Counter=0,1 |
| L2_IFETCH.SELF.S_STATE |
L2 cacheable instruction fetch requests |
EventSel=28H UMask=42H CMask=0 Counter=0,1 |
| L2_LD.SELF.ANY.E_STATE |
L2 cache reads |
EventSel=29H UMask=74H CMask=0 Counter=0,1 |
| L2_LD.SELF.ANY.I_STATE |
L2 cache reads |
EventSel=29H UMask=71H CMask=0 Counter=0,1 |
| L2_LD.SELF.ANY.M_STATE |
L2 cache reads |
EventSel=29H UMask=78H CMask=0 Counter=0,1 |
| L2_LD.SELF.ANY.MESI |
L2 cache reads |
EventSel=29H UMask=7FH CMask=0 Counter=0,1 |
| L2_LD.SELF.ANY.S_STATE |
L2 cache reads |
EventSel=29H UMask=72H CMask=0 Counter=0,1 |
| L2_LD.SELF.DEMAND.E_STATE |
L2 cache reads |
EventSel=29H UMask=44H CMask=0 Counter=0,1 |
| L2_LD.SELF.DEMAND.I_STATE |
L2 cache reads |
EventSel=29H UMask=41H CMask=0 Counter=0,1 |
| L2_LD.SELF.DEMAND.M_STATE |
L2 cache reads |
EventSel=29H UMask=48H CMask=0 Counter=0,1 |
| L2_LD.SELF.DEMAND.MESI |
L2 cache reads |
EventSel=29H UMask=4FH CMask=0 Counter=0,1 |
| L2_LD.SELF.DEMAND.S_STATE |
L2 cache reads |
EventSel=29H UMask=42H CMask=0 Counter=0,1 |
| L2_LD.SELF.PREFETCH.E_STATE |
L2 cache reads |
EventSel=29H UMask=54H CMask=0 Counter=0,1 |
| L2_LD.SELF.PREFETCH.I_STATE |
L2 cache reads |
EventSel=29H UMask=51H CMask=0 Counter=0,1 |
| L2_LD.SELF.PREFETCH.M_STATE |
L2 cache reads |
EventSel=29H UMask=58H CMask=0 Counter=0,1 |
| L2_LD.SELF.PREFETCH.MESI |
L2 cache reads |
EventSel=29H UMask=5FH CMask=0 Counter=0,1 |
| L2_LD.SELF.PREFETCH.S_STATE |
L2 cache reads |
EventSel=29H UMask=52H CMask=0 Counter=0,1 |
| L2_LD_IFETCH.SELF.E_STATE |
All read requests from L1 instruction and data caches |
EventSel=2DH UMask=44H CMask=0 Counter=0,1 |
| L2_LD_IFETCH.SELF.I_STATE |
All read requests from L1 instruction and data caches |
EventSel=2DH UMask=41H CMask=0 Counter=0,1 |
| L2_LD_IFETCH.SELF.M_STATE |
All read requests from L1 instruction and data caches |
EventSel=2DH UMask=48H CMask=0 Counter=0,1 |
| L2_LD_IFETCH.SELF.MESI |
All read requests from L1 instruction and data caches |
EventSel=2DH UMask=4FH CMask=0 Counter=0,1 |
| L2_LD_IFETCH.SELF.S_STATE |
All read requests from L1 instruction and data caches |
EventSel=2DH UMask=42H CMask=0 Counter=0,1 |
| L2_LINES_IN.SELF.ANY |
L2 cache misses. |
EventSel=24H UMask=70H CMask=0 Counter=0,1 |
| L2_LINES_IN.SELF.DEMAND |
L2 cache misses. |
EventSel=24H UMask=40H CMask=0 Counter=0,1 |
| L2_LINES_IN.SELF.PREFETCH |
L2 cache misses. |
EventSel=24H UMask=50H CMask=0 Counter=0,1 |
| L2_LINES_OUT.SELF.ANY |
L2 cache lines evicted. |
EventSel=26H UMask=70H CMask=0 Counter=0,1 |
| L2_LINES_OUT.SELF.DEMAND |
L2 cache lines evicted. |
EventSel=26H UMask=40H CMask=0 Counter=0,1 |
| L2_LINES_OUT.SELF.PREFETCH |
L2 cache lines evicted. |
EventSel=26H UMask=50H CMask=0 Counter=0,1 |
| L2_LOCK.SELF.E_STATE |
L2 locked accesses |
EventSel=2BH UMask=44H CMask=0 Counter=0,1 |
| L2_LOCK.SELF.I_STATE |
L2 locked accesses |
EventSel=2BH UMask=41H CMask=0 Counter=0,1 |
| L2_LOCK.SELF.M_STATE |
L2 locked accesses |
EventSel=2BH UMask=48H CMask=0 Counter=0,1 |
| L2_LOCK.SELF.MESI |
L2 locked accesses |
EventSel=2BH UMask=4FH CMask=0 Counter=0,1 |
| L2_LOCK.SELF.S_STATE |
L2 locked accesses |
EventSel=2BH UMask=42H CMask=0 Counter=0,1 |
| L2_M_LINES_IN.SELF |
L2 cache line modifications. |
EventSel=25H UMask=40H CMask=0 Counter=0,1 |
| L2_M_LINES_OUT.SELF.ANY |
Modified lines evicted from the L2 cache |
EventSel=27H UMask=70H CMask=0 Counter=0,1 |
| L2_M_LINES_OUT.SELF.DEMAND |
Modified lines evicted from the L2 cache |
EventSel=27H UMask=40H CMask=0 Counter=0,1 |
| L2_M_LINES_OUT.SELF.PREFETCH |
Modified lines evicted from the L2 cache |
EventSel=27H UMask=50H CMask=0 Counter=0,1 |
| L2_NO_REQ.SELF |
Cycles no L2 cache requests are pending |
EventSel=32H UMask=40H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.ANY.E_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=74H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.ANY.I_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=71H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.ANY.M_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=78H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.ANY.MESI |
Rejected L2 cache requests |
EventSel=30H UMask=7FH CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.ANY.S_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=72H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.DEMAND.E_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=44H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.DEMAND.I_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=41H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.DEMAND.M_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=48H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.DEMAND.MESI |
Rejected L2 cache requests |
EventSel=30H UMask=4FH CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.DEMAND.S_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=42H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=54H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=51H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=58H CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.PREFETCH.MESI |
Rejected L2 cache requests |
EventSel=30H UMask=5FH CMask=0 Counter=0,1 |
| L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE |
Rejected L2 cache requests |
EventSel=30H UMask=52H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.ANY.E_STATE |
L2 cache requests |
EventSel=2EH UMask=74H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.ANY.I_STATE |
L2 cache requests |
EventSel=2EH UMask=71H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.ANY.M_STATE |
L2 cache requests |
EventSel=2EH UMask=78H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.ANY.MESI |
L2 cache requests |
EventSel=2EH UMask=7FH CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.ANY.S_STATE |
L2 cache requests |
EventSel=2EH UMask=72H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.DEMAND.E_STATE |
L2 cache requests |
EventSel=2EH UMask=44H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.DEMAND.M_STATE |
L2 cache requests |
EventSel=2EH UMask=48H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.DEMAND.S_STATE |
L2 cache requests |
EventSel=2EH UMask=42H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.PREFETCH.E_STATE |
L2 cache requests |
EventSel=2EH UMask=54H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.PREFETCH.I_STATE |
L2 cache requests |
EventSel=2EH UMask=51H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.PREFETCH.M_STATE |
L2 cache requests |
EventSel=2EH UMask=58H CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.PREFETCH.MESI |
L2 cache requests |
EventSel=2EH UMask=5FH CMask=0 Counter=0,1 |
| L2_RQSTS.SELF.PREFETCH.S_STATE |
L2 cache requests |
EventSel=2EH UMask=52H CMask=0 Counter=0,1 |
| L2_ST.SELF.E_STATE |
L2 store requests |
EventSel=2AH UMask=44H CMask=0 Counter=0,1 |
| L2_ST.SELF.I_STATE |
L2 store requests |
EventSel=2AH UMask=41H CMask=0 Counter=0,1 |
| L2_ST.SELF.M_STATE |
L2 store requests |
EventSel=2AH UMask=48H CMask=0 Counter=0,1 |
| L2_ST.SELF.MESI |
L2 store requests |
EventSel=2AH UMask=4FH CMask=0 Counter=0,1 |
| L2_ST.SELF.S_STATE |
L2 store requests |
EventSel=2AH UMask=42H CMask=0 Counter=0,1 |
| MACHINE_CLEARS.SMC |
Self-Modifying Code detected. |
EventSel=C3H UMask=01H CMask=0 Counter=0,1 |
| MACRO_INSTS.ALL_DECODED |
All Instructions decoded |
EventSel=AAH UMask=03H CMask=0 Counter=0,1 |
| MACRO_INSTS.CISC_DECODED |
CISC macro instructions decoded |
EventSel=AAH UMask=02H CMask=0 Counter=0,1 |
| MACRO_INSTS.NON_CISC_DECODED |
Non-CISC macro instructions decoded |
EventSel=AAH UMask=01H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.DTLB_MISS |
Retired loads that miss the DTLB (precise event). |
EventSel=CBH UMask=04H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.DTLB_MISS.PS |
Retired loads that miss the DTLB (precise event). |
EventSel=CBH UMask=04H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.L2_HIT |
Retired loads that hit the L2 cache (precise event). |
EventSel=CBH UMask=01H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.L2_HIT.PS |
Retired loads that hit the L2 cache (precise event). |
EventSel=CBH UMask=81H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.L2_MISS |
Retired loads that miss the L2 cache |
EventSel=CBH UMask=02H CMask=0 Counter=0,1 |
| MEM_LOAD_RETIRED.L2_MISS.PS |
Retired loads that miss the L2 cache (precise event). |
EventSel=CBH UMask=82H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.BUBBLE |
Nonzero segbase 1 bubble |
EventSel=05H UMask=97H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.LD_BUBBLE |
Nonzero segbase load 1 bubble |
EventSel=05H UMask=91H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.LD_SPLIT |
Load splits |
EventSel=05H UMask=09H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.LD_SPLIT.AR |
Load splits (At Retirement) |
EventSel=05H UMask=89H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.RMW_BUBBLE |
Nonzero segbase ld-op-st 1 bubble |
EventSel=05H UMask=94H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.RMW_SPLIT |
ld-op-st splits |
EventSel=05H UMask=8CH CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.SPLIT |
Memory references that cross an 8-byte boundary. |
EventSel=05H UMask=0FH CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.SPLIT.AR |
Memory references that cross an 8-byte boundary (At Retirement) |
EventSel=05H UMask=8FH CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.ST_BUBBLE |
Nonzero segbase store 1 bubble |
EventSel=05H UMask=92H CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.ST_SPLIT |
Store splits |
EventSel=05H UMask=0AH CMask=0 Counter=0,1 |
| MISALIGN_MEM_REF.ST_SPLIT.AR |
Store splits (Ar Retirement) |
EventSel=05H UMask=8AH CMask=0 Counter=0,1 |
| MUL.AR |
Multiply operations retired |
EventSel=12H UMask=81H CMask=0 Counter=0,1 |
| MUL.S |
Multiply operations executed. |
EventSel=12H UMask=01H CMask=0 Counter=0,1 |
| PAGE_WALKS.CYCLES |
Duration of page-walks in core cycles |
EventSel=0CH UMask=03H CMask=0 Counter=0,1 |
| PAGE_WALKS.D_SIDE_CYCLES |
Duration of D-side only page walks |
EventSel=0CH UMask=01H CMask=0 Counter=0,1 |
| PAGE_WALKS.D_SIDE_WALKS |
Number of D-side only page walks |
EventSel=0CH UMask=01H AnyThread=1 CMask=0 Counter=0,1 |
| PAGE_WALKS.I_SIDE_CYCLES |
Duration of I-Side page walks |
EventSel=0CH UMask=02H CMask=0 Counter=0,1 |
| PAGE_WALKS.I_SIDE_WALKS |
Number of I-Side page walks |
EventSel=0CH UMask=02H AnyThread=1 CMask=0 Counter=0,1 |
| PAGE_WALKS.WALKS |
Number of page-walks executed. |
EventSel=0CH UMask=03H AnyThread=1 CMask=0 Counter=0,1 |
| PREFETCH.HW_PREFETCH |
L1 hardware prefetch request |
EventSel=07H UMask=10H CMask=0 Counter=0,1 |
| PREFETCH.PREFETCHNTA |
Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed |
EventSel=07H UMask=88H CMask=0 Counter=0,1 |
| PREFETCH.PREFETCHT0 |
Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed. |
EventSel=07H UMask=81H CMask=0 Counter=0,1 |
| PREFETCH.PREFETCHT1 |
Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed. |
EventSel=07H UMask=82H CMask=0 Counter=0,1 |
| PREFETCH.PREFETCHT2 |
Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed. |
EventSel=07H UMask=84H CMask=0 Counter=0,1 |
| PREFETCH.SOFTWARE_PREFETCH |
Any Software prefetch |
EventSel=07H UMask=0FH CMask=0 Counter=0,1 |
| PREFETCH.SOFTWARE_PREFETCH.AR |
Any Software prefetch |
EventSel=07H UMask=8FH CMask=0 Counter=0,1 |
| PREFETCH.SW_L2 |
Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed |
EventSel=07H UMask=86H CMask=0 Counter=0,1 |
| REISSUE.ANY |
Micro-op reissues for any cause |
EventSel=03H UMask=7FH CMask=0 Counter=0,1 |
| REISSUE.ANY.AR |
Micro-op reissues for any cause (At Retirement) |
EventSel=03H UMask=FFH CMask=0 Counter=0,1 |
| REISSUE.OVERLAP_STORE |
Micro-op reissues on a store-load collision |
EventSel=03H UMask=01H CMask=0 Counter=0,1 |
| REISSUE.OVERLAP_STORE.AR |
Micro-op reissues on a store-load collision (At Retirement) |
EventSel=03H UMask=81H CMask=0 Counter=0,1 |
| RESOURCE_STALLS.DIV_BUSY |
Cycles issue is stalled due to div busy. |
EventSel=DCH UMask=02H CMask=0 Counter=0,1 |
| SEGMENT_REG_LOADS.ANY |
Number of segment register loads. |
EventSel=06H UMask=80H CMask=0 Counter=0,1 |
| SIMD_ASSIST |
SIMD assists invoked. |
EventSel=CDH UMask=00H CMask=0 Counter=0,1 |
| SIMD_COMP_INST_RETIRED.PACKED_SINGLE |
Retired computational Streaming SIMD Extensions (SSE) packed-single instructions. |
EventSel=CAH UMask=01H CMask=0 Counter=0,1 |
| SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE |
Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions. |
EventSel=CAH UMask=08H CMask=0 Counter=0,1 |
| SIMD_COMP_INST_RETIRED.SCALAR_SINGLE |
Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions. |
EventSel=CAH UMask=02H CMask=0 Counter=0,1 |
| SIMD_INST_RETIRED.PACKED_SINGLE |
Retired Streaming SIMD Extensions (SSE) packed-single instructions. |
EventSel=C7H UMask=01H CMask=0 Counter=0,1 |
| SIMD_INST_RETIRED.SCALAR_DOUBLE |
Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions. |
EventSel=C7H UMask=08H CMask=0 Counter=0,1 |
| SIMD_INST_RETIRED.SCALAR_SINGLE |
Retired Streaming SIMD Extensions (SSE) scalar-single instructions. |
EventSel=C7H UMask=02H CMask=0 Counter=0,1 |
| SIMD_INST_RETIRED.VECTOR |
Retired Streaming SIMD Extensions 2 (SSE2) vector instructions. |
EventSel=C7H UMask=10H CMask=0 Counter=0,1 |
| SIMD_INSTR_RETIRED |
SIMD Instructions retired. |
EventSel=CEH UMask=00H CMask=0 Counter=0,1 |
| SIMD_SAT_INSTR_RETIRED |
Saturated arithmetic instructions retired. |
EventSel=CFH UMask=00H CMask=0 Counter=0,1 |
| SIMD_SAT_UOP_EXEC.AR |
SIMD saturated arithmetic micro-ops retired. |
EventSel=B1H UMask=80H CMask=0 Counter=0,1 |
| SIMD_SAT_UOP_EXEC.S |
SIMD saturated arithmetic micro-ops executed. |
EventSel=B1H UMask=00H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR |
SIMD packed arithmetic micro-ops retired |
EventSel=B3H UMask=A0H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.ARITHMETIC.S |
SIMD packed arithmetic micro-ops executed |
EventSel=B3H UMask=20H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.LOGICAL.AR |
SIMD packed logical micro-ops retired |
EventSel=B3H UMask=90H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.LOGICAL.S |
SIMD packed logical micro-ops executed |
EventSel=B3H UMask=10H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.MUL.AR |
SIMD packed multiply micro-ops retired |
EventSel=B3H UMask=81H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.MUL.S |
SIMD packed multiply micro-ops executed |
EventSel=B3H UMask=01H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.PACK.AR |
SIMD packed micro-ops retired |
EventSel=B3H UMask=84H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.PACK.S |
SIMD packed micro-ops executed |
EventSel=B3H UMask=04H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.SHIFT.AR |
SIMD packed shift micro-ops retired |
EventSel=B3H UMask=82H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.SHIFT.S |
SIMD packed shift micro-ops executed |
EventSel=B3H UMask=02H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.UNPACK.AR |
SIMD unpacked micro-ops retired |
EventSel=B3H UMask=88H CMask=0 Counter=0,1 |
| SIMD_UOP_TYPE_EXEC.UNPACK.S |
SIMD unpacked micro-ops executed |
EventSel=B3H UMask=08H CMask=0 Counter=0,1 |
| SIMD_UOPS_EXEC.AR |
SIMD micro-ops retired (excluding stores). |
EventSel=B0H UMask=80H CMask=0 Counter=0,1 |
| SIMD_UOPS_EXEC.S |
SIMD micro-ops executed (excluding stores). |
EventSel=B0H UMask=00H CMask=0 Counter=0,1 |
| SNOOP_STALL_DRV.ALL_AGENTS |
Bus stalled for snoops. |
EventSel=7EH UMask=E0H CMask=0 Counter=0,1 |
| SNOOP_STALL_DRV.SELF |
Bus stalled for snoops. |
EventSel=7EH UMask=40H CMask=0 Counter=0,1 |
| STORE_FORWARDS.GOOD |
Good store forwards |
EventSel=02H UMask=81H CMask=0 Counter=0,1 |
| THERMAL_TRIP |
Number of thermal trips |
EventSel=3BH UMask=C0H CMask=0 Counter=0,1 |
| UOPS.MS_CYCLES |
This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ. |
EventSel=A9H UMask=01H CMask=01H Counter=0,1 |
| UOPS_RETIRED.ANY |
Micro-ops retired. |
EventSel=C2H UMask=10H CMask=0 Counter=0,1 |
| UOPS_RETIRED.STALLED_CYCLES |
Cycles no micro-ops retired. |
EventSel=C2H UMask=10H Invert=1 CMask=1 Counter=0,1 |
| UOPS_RETIRED.STALLS |
Periods no micro-ops retired. |
EventSel=C2H UMask=10H EdgeDetect=1 Invert=1 CMask=1 Counter=0,1 |
| X87_COMP_OPS_EXE.ANY.AR |
Floating point computational micro-ops retired. |
EventSel=10H UMask=81H CMask=0 Counter=0,1 |
| X87_COMP_OPS_EXE.ANY.S |
Floating point computational micro-ops executed. |
EventSel=10H UMask=01H CMask=0 Counter=0,1 |
| X87_COMP_OPS_EXE.FXCH.AR |
FXCH uops retired. |
EventSel=10H UMask=82H CMask=0 Counter=0,1 |
| X87_COMP_OPS_EXE.FXCH.S |
FXCH uops executed. |
EventSel=10H UMask=02H CMask=0 Counter=0,1 |