| GMCH_AB0_REQUESTS.RD_32B_ANY |
Counts the number of AB0 read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_32B_CH0 |
Counts the number of AB0 read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_32B_CH1 |
Counts the number of AB0 read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_64B_ANY |
Counts the number of AB0 read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_64B_CH0 |
Counts the number of AB0 read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_64B_CH1 |
Counts the number of AB0 read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_PARTIAL_ANY |
Counts the number of AB0 partial read requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of AB0 partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of AB0 partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_32B_ANY |
Counts the number of AB0 write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_32B_CH0 |
Counts the number of AB0 write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_32B_CH1 |
Counts the number of AB0 write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_64B_ANY |
Counts the number of AB0 write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_64B_CH0 |
Counts the number of AB0 write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_64B_CH1 |
Counts the number of AB0 write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_PARTIAL_ANY |
Counts the number of AB0 partial write requests |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of AB0 partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB0_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of AB0 partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_32B_ANY |
Counts the number of AB1 read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_32B_CH0 |
Counts the number of AB1 read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_32B_CH1 |
Counts the number of AB1 read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_64B_ANY |
Counts the number of AB1 read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_64B_CH0 |
Counts the number of AB1 read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_64B_CH1 |
Counts the number of AB1 read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_PARTIAL_ANY |
Counts the number of AB1 partial read requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of AB1 partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of AB1 partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_32B_ANY |
Counts the number of AB1 write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_32B_CH0 |
Counts the number of AB1 write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_32B_CH1 |
Counts the number of AB1 write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_64B_ANY |
Counts the number of AB1 write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_64B_CH0 |
Counts the number of AB1 write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_64B_CH1 |
Counts the number of AB1 write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_PARTIAL_ANY |
Counts the number of AB1 partial write requests |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of AB1 partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_AB1_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of AB1 partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQDOWN_HA_REQ |
Counts when Aunit request queue allocated for reqdown_ha_req |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQDOWN_RSP0 |
Counts when Aunit request queue allocated for reqdown_rsp0 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQDOWN_RSP1 |
Counts when Aunit request queue allocated for reqdown_rsp1 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQUP_CMD0 |
Counts when Aunit request queue allocated for requp_cmd0 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQUP_CMD1 |
Counts when Aunit request queue allocated for requp_cmd1 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQUP_DATA0 |
Counts when Aunit request queue allocated for requp_data0 |
EventSel=00H UMask=00H |
| GMCH_AUNIT_QUEUE_ENTRIES_ADDED.REQUP_DATA1 |
Counts when Aunit request queue allocated for requp_data1 |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_32B_ANY |
Counts the 32 byte read requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_32B_CH0 |
Counts the 32 byte read requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_32B_CH1 |
Counts the 32 byte read requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_64B_ANY |
Counts the 64 byte read requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_64B_CH0 |
Counts the 64 byte read requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_64B_CH1 |
Counts the 64 byte read requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_PARTIAL_ANY |
Counts the partial read requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_PARTIAL_CH0 |
Counts the partial read requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.RD_PARTIAL_CH1 |
Counts the partial read requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_32B_ANY |
Counts the 32 byte write requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_32B_CH0 |
Counts the 32 byte write requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_32B_CH1 |
Counts the 32 byte write requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_64B_ANY |
Counts the 64 byte write requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_64B_CH0 |
Counts the 64 byte write requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_64B_CH1 |
Counts the 64 byte write requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_PARTIAL_ANY |
Counts the partial write requests entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_PARTIAL_CH0 |
Counts the partial write requests to channel 0 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_B_ALL_REQUESTS.WR_PARTIAL_CH1 |
Counts the partial write requests to channel 1 entering the Bunit. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.AB0 |
Counts when bunit request queue allocated for AB0 |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.AB1 |
Counts when bunit request queue allocated for AB1 |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.GB0 |
Counts when bunit request queue allocated for GB0 |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.GB1 |
Counts when bunit request queue allocated for GB1 |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.HOST |
Counts when bunit request queue allocated for host |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.IB |
Counts when bunit request queue allocated for IB |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_ADDED.PB |
Counts when bunit request queue allocated for PB |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.AB0 |
Counts the number of request queue entries occupied for breq_queue_AB0, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.AB1 |
Counts the number of request queue entries occupied for breq_queue_AB1, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.GB0 |
Counts the number of request queue entries occupied for breq_queue_GB0, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.GB1 |
Counts the number of request queue entries occupied for breq_queue_GB1, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.HOST |
Counts the number of request queue entries occupied for breq_queue_host, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.IB |
Counts the number of request queue entries occupied for breq_queue_IB, each clock. |
EventSel=00H UMask=00H |
| GMCH_BUNIT_REQ_QUEUE_ENTRIES_OCCUPIED.PB |
Counts the number of request queue entries occupied for breq_queue_PB, each clock. |
EventSel=00H UMask=00H |
| GMCH_C_STATE_CYCLES.C2 |
Counts the number of cycles in C2 state |
EventSel=00H UMask=00H |
| GMCH_C_STATE_CYCLES.C2.POPUP |
Counts the cycles in Pop-Up C2 state |
EventSel=00H UMask=00H |
| GMCH_C_STATE_CYCLES.C4 |
Counts the cycles in C4 state |
EventSel=00H UMask=00H |
| GMCH_C_STATE_CYCLES.C6 |
Counts the cycles in C6 state |
EventSel=00H UMask=00H |
| GMCH_C_STATE_CYCLES.EXT_STPCLK |
Counts the cycles in External STPCLK |
EventSel=00H UMask=00H |
| GMCH_C_STATE_TRANSITION_CYCLES.C2 |
Cycles taken for C2 transition. Count cycles between SCL LVL2 read request and last message sent by P unit. |
EventSel=00H UMask=00H |
| GMCH_C_STATE_TRANSITION_CYCLES.C4 |
Cycles taken for C4 transition. Count cycles between SCL LVL4 read request and last message sent by P unit. |
EventSel=00H UMask=00H |
| GMCH_C_STATE_TRANSITION_CYCLES.C6 |
Cycles taken for C6 transition. Count cycles between SCL LVL6 read request and last message sent by P unit. |
EventSel=00H UMask=00H |
| GMCH_CORE_CLKS |
Counts the number of GMCH core clocks |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.ACTIVATE |
Counts the number of DRAM activates. a DRAM page is activated or opened before issued a read or write command if the page is not already opened. |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.ENTER_PWRDOWN |
Counts the number of DRAM power down entries, which places the DRAM in power saving mode. |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.ENTER_SELF_REFRESH.DEEP |
Counts the number of deep self refresh entries. |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.ENTER_SELF_REFRESH.SHALLOW |
Counts the number of shallow self refresh entries. |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.EXIT_SELF_REFRESH_OR_PWRDOWN |
Counts the number of self refresh/power down exits. |
EventSel=00H UMask=00H |
| GMCH_DRAM_COMMANDS.REFRESH |
Counts the number of DRAM refreshes, a DRAM command send periodically to refresh DRAM memory. |
EventSel=00H UMask=00H |
| GMCH_DRAM_OPEN_PAGES |
Counts the number of DRAM pages open each cycle. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.PAGE_EMPTY |
Counts the number of DRAM Page Empty, a new request address is not within any of the opened pages in any bank. A new page will be opened. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.PAGE_HIT |
Counts the number of DRAM Page Hits, a new request address is within an already opened page |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.PAGE_MISS |
Counts the number of DRAM Page Misses, a new request address is within the same bank but not within an already opened page. The old page needs to close before the new page can be opened. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.WITHIN_ADDR_RANGE |
Counts the number of DRAM Page Hit/Miss/Empty within address range. Limit the Hit/Miss/Empty address compare to within a specified range |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.WITHIN_ADDR_RANGE_BANK |
Counts the DRAM Page Hit/Miss/Empty within bank. Limit the Hit/Miss/Empty address compare to within a selected bank. Use registers GMCH_PERF_BANK_SEL as documented in next section to set the bank. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.WITHIN_ADDR_RANGE_BANK_SELECT |
DRAM Page Hit/Miss/Empty from selectedsource. Limit the Hit/Miss/Empty address compare to within a select source. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PAGE_STATUS.WITHIN_ADDR_RANGE_SELECT |
DRAM Page Hit/Miss/Empty within bank. Limit the Hit/Miss/Empty address compare to within a selected bank. Use registers GMCH_PERF_BANK_SEL as documented in next section to set the bank. |
EventSel=00H UMask=00H |
| GMCH_DRAM_POWER_SAVE.CYCLES_PWRDOWN |
DRAM Power Down Mode. Counts every cycle DRAM is in power down mode. |
EventSel=00H UMask=00H |
| GMCH_DRAM_POWER_SAVE.CYCLES_SELF_REFRESH.DEEP |
DRAM Self Refresh - Deep Mode. Counts every cycle DRAM is in Deep Self Refresh mode. |
EventSel=00H UMask=00H |
| GMCH_DRAM_POWER_SAVE.CYCLES_SELF_REFRESH.SHALLOW |
DRAM Self Refresh - Shallow Mode. Counts every cycle DRAM is in shallow Self Refresh mode. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PRECHARGE.ALL |
Counts the number of DRAM Precharge-all events, A single precharge-all (PREALL) cmd closes all open pages in a rank. PREALL is issued when DRAM needs to be refreshed or needs to go into any of the power down modes. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PRECHARGE.PAGE_CLOSE |
Counts the number of DRAM page close precharges, a DRAM command issued to CLOSE a page due to page idle timer expiration. |
EventSel=00H UMask=00H |
| GMCH_DRAM_PRECHARGE.PAGE_MISS |
Counts the number of precharges (PRE) that were issued because there was a page miss. Page miss refers to a situation in which a page is currently open and different page from the same bank needs to open. The new page experiences a page miss. Closing of the old page is done by issuing a PRE. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.RD_32B |
Counts the number of read 32 byte requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.RD_64B |
Counts the number of read 64 byte requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.RD_ANY |
Counts the number of read requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.WR_32B |
Counts the number of write 32 byte requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.WR_64B |
Counts the number of write 64 byte requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_REQ_TYPE.WR_ANY |
Counts the number of write requests to DRAM. |
EventSel=00H UMask=00H |
| GMCH_DRAM_SCHED_SEQUENCE.RD_RD |
Counts the occurances of the specific sequence: any read followed by read. |
EventSel=00H UMask=00H |
| GMCH_DRAM_SCHED_SEQUENCE.RD_WR |
Counts the occurances of the specific sequence: any read followed by write. |
EventSel=00H UMask=00H |
| GMCH_DRAM_SCHED_SEQUENCE.RDWR_WRRD_SAME_RANKBANK_DIFF_PAGE |
Rd/wr followed by rd/wr, Same rank & bank, diff page. The above ""op followed by op"" sequences, further qualified by both being in the same rank and bank but different page. Needs to be combined with one of the masks above. |
EventSel=00H UMask=00H |
| GMCH_DRAM_SCHED_SEQUENCE.WR_RD |
Counts the occurances of the specific sequence: any write followed by read. |
EventSel=00H UMask=00H |
| GMCH_DRAM_SCHED_SEQUENCE.WR_WR |
Counts the occurances of the specific sequence: any read followed by read. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.BOTH_EMPTY |
Ch0 & Ch1 are Empty. This should count only if we have at least 1 valid request (RD or WR) in Bunit. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH0_EMPTY |
Ch0 Empty. This should count only if we have at least 1 valid request (RD or WR) in Bunit. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH0_EMPTY_CH1_NOT_EMPTY |
Ch0 is Empty while Ch1 is Not Empty. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH0_FULL |
Ch0 Full. If a ready request is blocked due to the full queue. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH1_EMPTY |
Ch1 Empty. This should count only if we have at least 1 valid request (RD or WR) in Bunit. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH1_EMPTY_CH0_NOT_EMPTY |
Ch1 is Empty while Ch0 is Not Empty. |
EventSel=00H UMask=00H |
| GMCH_DUAL_CHANNEL_QUEUES.CH1_FULL |
Ch1 Full. If a ready request is blocked due to the full queue. |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_32B_ANY |
Counts the number of GB0 read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_32B_CH0 |
Counts the number of GB0 read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_32B_CH1 |
Counts the number of GB0 read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_64B_ANY |
Counts the number of GB0 read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_64B_CH0 |
Counts the number of GB0 read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_64B_CH1 |
Counts the number of GB0 read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_PARTIAL_ANY |
Counts the number of GB0 partial read requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of GB0 partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of GB0 partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_32B_ANY |
Counts the number of GB0 write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_32B_CH0 |
Counts the number of GB0 write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_32B_CH1 |
Counts the number of GB0 write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_64B_ANY |
Counts the number of GB0 write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_64B_CH0 |
Counts the number of GB0 write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_64B_CH1 |
Counts the number of GB0 write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_PARTIAL_ANY |
Counts the number of GB0 partial write requests |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of GB0 partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB0_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of GB0 partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_32B_ANY |
Counts the number of GB1 read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_32B_CH0 |
Counts the number of GB1 read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_32B_CH1 |
Counts the number of GB1 read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_64B_ANY |
Counts the number of GB1 read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_64B_CH0 |
Counts the number of GB1 read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_64B_CH1 |
Counts the number of GB1 read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_PARTIAL_ANY |
Counts the number of GB1 partial read requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of GB1 partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of GB1 partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_32B_ANY |
Counts the number of GB1 write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_32B_CH0 |
Counts the number of GB1 write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_32B_CH1 |
Counts the number of GB1 write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_64B_ANY |
Counts the number of GB1 write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_64B_CH0 |
Counts the number of GB1 write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_64B_CH1 |
Counts the number of GB1 write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_PARTIAL_ANY |
Counts the number of GB1 partial write requests |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of GB1 partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_GB1_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of GB1 partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_GFX_ALL_AND_STALLS.RD |
Read request from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_ALL_AND_STALLS.RD_STALLED |
Read request from GFX stalled by GVD |
EventSel=00H UMask=00H |
| GMCH_GFX_ALL_AND_STALLS.WR |
Write request from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_ALL_AND_STALLS.WR_STALLED |
Write request from GFX stalled by GVD |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.BURST_MASKED_WR_ALL |
Counts the burst mode masked write requests from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.BURST_NONMASKED_WR_ALL |
Counts the burst mode non-masked write requests from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.BURST_RD_ALL |
Counts the burst mode read requests from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.NONBURST_MASKED_WR_ALL |
Counts the non-burst mode masked write requests from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.NONBURST_NONMASKED_WR_ALL |
Counts the non-burst mode non-masked write requests from GFX |
EventSel=00H UMask=00H |
| GMCH_GFX_MEM_REQUEST.NONBURST_RD_ALL |
Counts the non-burst mode read requests from GFX |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_32B_ANY |
Counts the number of HB read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_32B_CH0 |
Counts the number of HB read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_32B_CH1 |
Counts the number of HB read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_64B_ANY |
Counts the number of HB read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_64B_CH0 |
Counts the number of HB read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_64B_CH1 |
Counts the number of HB read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_PARTIAL_ANY |
Counts the number of HB partial read requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of HB partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of HB partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_32B_ANY |
Counts the number of HB write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_32B_CH0 |
Counts the number of HB write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_32B_CH1 |
Counts the number of HB write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_64B_ANY |
Counts the number of HB write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_64B_CH0 |
Counts the number of HB write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_64B_CH1 |
Counts the number of HB write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_PARTIAL_ANY |
Counts the number of HB partial write requests |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of HB partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_HB_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of HB partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_32B_ANY |
Counts the number of IB read 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_32B_CH0 |
Counts the number of IB read 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_32B_CH1 |
Counts the number of IB read 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_64B_ANY |
Counts the number of IB read 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_64B_CH0 |
Counts the number of IB read 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_64B_CH1 |
Counts the number of IB read 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_PARTIAL_ANY |
Counts the number of IB partial read requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_PARTIAL_CH0 |
Counts the number of IB partial read requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.RD_PARTIAL_CH1 |
Counts the number of IB partial read requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_32B_ANY |
Counts the number of IB write 32 byte requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_32B_CH0 |
Counts the number of IB write 32 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_32B_CH1 |
Counts the number of IB write 32 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_64B_ANY |
Counts the number of IB write 64 byte requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_64B_CH0 |
Counts the number of IB write 64 byte requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_64B_CH1 |
Counts the number of IB write 64 byte requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_PARTIAL_ANY |
Counts the number of IB partial write requests |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_PARTIAL_CH0 |
Counts the number of IB partial write requests to channel 0 |
EventSel=00H UMask=00H |
| GMCH_IB_REQUESTS.WR_PARTIAL_CH1 |
Counts the number of IB partial write requests to channel 1 |
EventSel=00H UMask=00H |
| GMCH_IUNIT_REQUEST.RD_32B |
32B read requests on IB interface |
EventSel=00H UMask=00H |
| GMCH_IUNIT_REQUEST.RD_64B |
64B read requests on IB interface |
EventSel=00H UMask=00H |
| GMCH_IUNIT_REQUEST.WR_32B |
32B write requests on IB interface |
EventSel=00H UMask=00H |
| GMCH_IUNIT_REQUEST.WR_64B |
64B write requests on IB interface |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_DRAM.ANY |
This event counts partial write requests to DRAM. This event can be used to count the number of combined requests. Subtracting this event from Event 0x0 gives us the number of combined requests. |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_DRAM.CH0 |
This event counts partial write requests to DRAM channel 0. |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_DRAM.CH1 |
This event counts partial write requests to DRAM channel 1. |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.AB0 |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.AB1 |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.ANY |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.GB0 |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.GB1 |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.HB |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.IB |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_PARTIAL_WR_REQ.PB |
The event counts partial write requests from different sources. It is useful to see the effect of the write-combining which occurs in the Bunit SRAM, which affects DRAM bandwidth and utilization. To also check if it was a good investment to add the combining (the byte enables). |
EventSel=00H UMask=00H |
| GMCH_WR_FLUSH.ANY |
Count Write Flushes, which happens when the number of writes exceeds the high watermark level. |
EventSel=00H UMask=00H |
| GMCH_WR_FLUSH.CH0 |
Count Write Flushes, which happens when the number of writes exceeds the high watermark level. Request on Channel 0. This should be used in conjunction with the other masks. |
EventSel=00H UMask=00H |
| GMCH_WR_FLUSH.CH1 |
Count Write Flushes, which happens when the number of writes exceeds the high watermark level. Request on Channel 1. This should be used in conjunction with the other masks. |
EventSel=00H UMask=00H |