11th Generation Intel® Core™ Processor
This section provides reference for hardware events that can be monitored for the CPU(s):
Event Name Description Additional Info EventType
CORE CoreOnly
INST_RETIRED.ANY Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. IA32_FIXED_CTR0
PEBS:[PreciseEventingIP]
Architectural, Fixed, AtRetirement
CoreOnly
CPU_CLK_UNHALTED.THREAD Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. IA32_FIXED_CTR1
PEBS:[NonPreciseEventingIP]
Architectural, Fixed, Speculative
CoreOnly
CPU_CLK_UNHALTED.REF_TSC Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. IA32_FIXED_CTR2
PEBS:[NonPreciseEventingIP]
Architectural, Fixed, Speculative
CoreOnly
TOPDOWN.SLOTS Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). IA32_FIXED_CTR3
PEBS:[NonPreciseEventingIP]
Architectural, Fixed, Speculative
CoreOnly
BR_INST_RETIRED.ALL_BRANCHES Counts all branch instructions retired. EventSel=C4H UMask=00H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, AtRetirement
CoreOnly
BR_MISP_RETIRED.ALL_BRANCHES Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. EventSel=C5H UMask=00H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, AtRetirement
CoreOnly
CPU_CLK_UNHALTED.REF_XCLK Counts core crystal clock cycles when the thread is unhalted. EventSel=3CH UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, Speculative
CoreOnly
CPU_CLK_UNHALTED.THREAD_P This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. EventSel=3CH UMask=00H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, Speculative
CoreOnly
INST_RETIRED.ANY_P Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. EventSel=C0H UMask=00H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, AtRetirement
CoreOnly
LONGEST_LAT_CACHE.MISS Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. EventSel=2EH UMask=41H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, Speculative
CoreOnly
TOPDOWN.SLOTS_P Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. EventSel=A4H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Architectural, Speculative
CoreOnly
ARITH.DIVIDER_ACTIVE Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. EventSel=14H UMask=09H CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
ASSISTS.ANY Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists. EventSel=C1H UMask=07H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
ASSISTS.FP Counts all microcode Floating Point assists. EventSel=C1H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
BACLEARS.ANY Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. EventSel=E6H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BR_INST_RETIRED.COND Counts conditional branch instructions retired. EventSel=C4H UMask=11H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.COND_NTAKEN Counts not taken branch instructions retired. EventSel=C4H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.COND_TAKEN Counts taken conditional branch instructions retired. EventSel=C4H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.FAR_BRANCH Counts far branch instructions retired. EventSel=C4H UMask=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.INDIRECT Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. EventSel=C4H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.NEAR_CALL Counts both direct and indirect near call instructions retired. EventSel=C4H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.NEAR_RETURN Counts return instructions retired. EventSel=C4H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_INST_RETIRED.NEAR_TAKEN Counts taken branch instructions retired. EventSel=C4H UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.COND Counts mispredicted conditional branch instructions retired. EventSel=C5H UMask=11H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.COND_NTAKEN Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. EventSel=C5H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.COND_TAKEN Counts taken conditional mispredicted branch instructions retired. EventSel=C5H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.INDIRECT Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch). EventSel=C5H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.INDIRECT_CALL Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. EventSel=C5H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
BR_MISP_RETIRED.NEAR_TAKEN Counts number of near branch instructions retired that were mispredicted and taken. EventSel=C5H UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
CORE_POWER.LVL0_TURBO_LICENSE Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. EventSel=28H UMask=07H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CORE_POWER.LVL1_TURBO_LICENSE Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. EventSel=28H UMask=18H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CORE_POWER.LVL2_TURBO_LICENSE Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions. EventSel=28H UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CPU_CLK_UNHALTED.DISTRIBUTED This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. EventSel=ECH UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted. EventSel=3CH UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
CPU_CLK_UNHALTED.REF_DISTRIBUTED This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. EventSel=3CH UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding. EventSel=A3H UMask=08H CMask=8
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss demand load is outstanding. EventSel=A3H UMask=01H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an outstanding load. EventSel=A3H UMask=10H CMask=16
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding. EventSel=A3H UMask=0CH CMask=12
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss demand load is outstanding. EventSel=A3H UMask=05H CMask=5
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLE_ACTIVITY.STALLS_L3_MISS Execution stalls while L3 cache miss demand load is outstanding. EventSel=A3H UMask=06H CMask=6
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLE_ACTIVITY.STALLS_MEM_ANY Execution stalls while memory subsystem has an outstanding load. EventSel=A3H UMask=14H CMask=20
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls. EventSel=A3H UMask=04H CMask=4
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
DSB2MITE_SWITCHES.COUNT Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions. EventSel=ABH UMask=02H EdgeDetect=1 CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DSB2MITE_SWITCHES.PENALTY_CYCLES Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE. EventSel=ABH UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.STLB_HIT Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). EventSel=08H UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. EventSel=08H UMask=10H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. EventSel=08H UMask=0EH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. EventSel=08H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED_4K Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. EventSel=08H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_PENDING Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. EventSel=08H UMask=10H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.STLB_HIT Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). EventSel=49H UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. EventSel=49H UMask=10H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. EventSel=49H UMask=0EH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 2M/4M pages. The page walks can end with or without a page fault. EventSel=49H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED_4K Counts page walks completed due to demand data stores whose address translations missed in the TLB and were mapped to 4K pages. The page walks can end with or without a page fault. EventSel=49H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_PENDING Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. EventSel=49H UMask=10H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EXE_ACTIVITY.1_PORTS_UTIL Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty. EventSel=A6H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.2_PORTS_UTIL Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. EventSel=A6H UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.3_PORTS_UTIL Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty. EventSel=A6H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.4_PORTS_UTIL Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty. EventSel=A6H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.BOUND_ON_LOADS Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle. EventSel=A6H UMask=21H CMask=5
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.BOUND_ON_STORES Counts cycles where the Store Buffer was full and no loads caused an execution stall. EventSel=A6H UMask=40H CMask=2
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
EXE_ACTIVITY.EXE_BOUND_0_PORTS Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load. EventSel=A6H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.SCALAR_DOUBLE Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FP_ARITH_INST_RETIRED.SCALAR_SINGLE Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. EventSel=C7H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.ANY_DSB_MISS Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.DSB_MISS Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=11H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.ITLB_MISS Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=14H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.L1I_MISS Counts retired Instructions who experienced Instruction L1 Cache true miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=12H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.L2_MISS Counts retired Instructions who experienced Instruction L2 Cache true miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=13H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_1 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500106H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_128 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=508006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_16 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=501006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_2 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500206H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=100206H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_256 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=510006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_32 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=502006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_4 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500406H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_512 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=520006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_64 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=504006H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.LATENCY_GE_8 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500806H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
FRONTEND_RETIRED.STLB_MISS Counts retired Instructions that experienced STLB (2nd level TLB) true miss. EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=15H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
ICACHE_16B.IFDATA_STALL Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. EventSel=80H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE_64B.IFTAG_HIT Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses. EventSel=83H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE_64B.IFTAG_MISS Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses. EventSel=83H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE_64B.IFTAG_STALL Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. EventSel=83H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.DSB_CYCLES_ANY Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. EventSel=79H UMask=08H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.DSB_CYCLES_OK Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). EventSel=79H UMask=08H CMask=5
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.DSB_UOPS Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. EventSel=79H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MITE_CYCLES_ANY Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). EventSel=79H UMask=04H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MITE_CYCLES_OK Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). EventSel=79H UMask=04H CMask=5
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MITE_UOPS Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). EventSel=79H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MS_CYCLES_ANY Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. EventSel=79H UMask=30H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. EventSel=79H UMask=30H EdgeDetect=1 CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ.MS_UOPS Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS. EventSel=79H UMask=30H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
IDQ_UOPS_NOT_DELIVERED.CORE Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. EventSel=9CH UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. EventSel=9CH UMask=01H CMask=5
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. EventSel=9CH UMask=01H Invert=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
ILD_STALL.LCP Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. EventSel=87H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
INST_DECODED.DECODERS Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions. EventSel=55H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
INST_RETIRED.NOP Number of all retired NOP instructions. EventSel=C0H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
INST_RETIRED.PREC_DIST A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0. IA32_FIXED_CTR0
PEBS:[PreciseEventingIP]
Fixed, AtRetirement
CoreOnly
INT_MISC.ALL_RECOVERY_CYCLES Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall. EventSel=0DH UMask=03H CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
INT_MISC.CLEAR_RESTEER_CYCLES Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. EventSel=0DH UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
INT_MISC.RECOVERY_CYCLES Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event. EventSel=0DH UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
INT_MISC.UOP_DROPPING Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons EventSel=0DH UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
ITLB_MISSES.STLB_HIT Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). EventSel=85H UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. EventSel=85H UMask=10H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. EventSel=85H UMask=0EH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED_2M_4M Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. EventSel=85H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED_4K Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. EventSel=85H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_PENDING Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. EventSel=85H UMask=10H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D.REPLACEMENT Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. EventSel=51H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D_PEND_MISS.FB_FULL Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. EventSel=48H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D_PEND_MISS.FB_FULL_PERIODS Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. EventSel=48H UMask=02H EdgeDetect=1 CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D_PEND_MISS.L2_STALL Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. EventSel=48H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D_PEND_MISS.PENDING Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. EventSel=48H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L1D_PEND_MISS.PENDING_CYCLES Counts duration of L1D miss outstanding in cycles. EventSel=48H UMask=01H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_LINES_IN.ALL Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. EventSel=F1H UMask=1FH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_LINES_OUT.NON_SILENT Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 EventSel=F2H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_LINES_OUT.SILENT Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event. EventSel=F2H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.ALL_CODE_RD Counts the total number of L2 code requests. EventSel=24H UMask=E4H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.ALL_DEMAND_DATA_RD Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. EventSel=24H UMask=E1H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.ALL_RFO Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. EventSel=24H UMask=E2H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.CODE_RD_HIT Counts L2 cache hits when fetching instructions, code reads. EventSel=24H UMask=C4H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.CODE_RD_MISS Counts L2 cache misses when fetching instructions. EventSel=24H UMask=24H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.DEMAND_DATA_RD_HIT Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. EventSel=24H UMask=C1H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.DEMAND_DATA_RD_MISS Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. EventSel=24H UMask=21H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.MISS Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. EventSel=24H UMask=3FH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.REFERENCES Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. EventSel=24H UMask=FFH
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.RFO_HIT Counts the RFO (Read-for-Ownership) requests that hit L2 cache. EventSel=24H UMask=C2H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.RFO_MISS Counts the RFO (Read-for-Ownership) requests that miss L2 cache. EventSel=24H UMask=22H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.SWPF_HIT Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. EventSel=24H UMask=C8H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_RQSTS.SWPF_MISS Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. EventSel=24H UMask=28H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_TRANS.L2_WB Counts L2 writebacks that access L2 cache. EventSel=F0H UMask=40H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LD_BLOCKS.NO_SR Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. EventSel=03H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LD_BLOCKS.STORE_FORWARD Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide. EventSel=03H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LD_BLOCKS_PARTIAL.ADDRESS_ALIAS Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address. EventSel=07H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LOAD_HIT_PREFETCH.SWPF Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. EventSel=4CH UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LOCK_CYCLES.CACHE_LOCK_DURATION This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION). EventSel=63H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LSD.CYCLES_ACTIVE Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). EventSel=A8H UMask=01H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LSD.CYCLES_OK Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). EventSel=A8H UMask=01H CMask=5
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LSD.UOPS Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). EventSel=A8H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.COUNT Counts the number of machine clears (nukes) of any type. EventSel=C3H UMask=01H EdgeDetect=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
MACHINE_CLEARS.MEMORY_ORDERING Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture EventSel=C3H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
MACHINE_CLEARS.SMC Counts self-modifying code (SMC) detected, which causes a machine clear. EventSel=C3H UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
MEM_INST_RETIRED.ALL_LOADS Counts all retired load instructions. This event accounts for SW prefetch instructions for loads. EventSel=D0H UMask=81H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.ALL_STORES Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores. EventSel=D0H UMask=82H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.ANY Counts all retired memory instructions - loads and stores. EventSel=D0H UMask=83H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.LOCK_LOADS Counts retired load instructions with locked access. EventSel=D0H UMask=21H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.SPLIT_LOADS Counts retired load instructions that split across a cacheline boundary. EventSel=D0H UMask=41H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.SPLIT_STORES Counts retired store instructions that split across a cacheline boundary. EventSel=D0H UMask=42H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.STLB_MISS_LOADS Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). EventSel=D0H UMask=11H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_INST_RETIRED.STLB_MISS_STORES Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). EventSel=D0H UMask=12H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD). EventSel=D2H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. EventSel=D2H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD). EventSel=D2H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE Counts retired load instructions whose data sources were hits in L3 without snoops required. EventSel=D2H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.FB_HIT Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. EventSel=D1H UMask=40H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L1_HIT Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. EventSel=D1H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L1_MISS Counts retired load instructions with at least one uop that missed in the L1 cache. EventSel=D1H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L2_HIT Counts retired load instructions with L2 cache hits as data sources. EventSel=D1H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L2_MISS Counts retired load instructions missed L2 cache as data sources. EventSel=D1H UMask=10H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L3_HIT Counts retired load instructions with at least one uop that hit in the L3 cache. EventSel=D1H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_LOAD_RETIRED.L3_MISS Counts retired load instructions with at least one uop that missed in the L3 cache. EventSel=D1H UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MISC_RETIRED.LBR_INSERTS Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT. EventSel=CCH UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
MISC_RETIRED.PAUSE_INST Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products. EventSel=CCH UMask=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
AtRetirement
CoreOnly
OFFCORE_REQUESTS.ALL_DATA_RD Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. EventSel=B0H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS.ALL_REQUESTS Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.. EventSel=B0H UMask=80H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS.DEMAND_DATA_RD Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. EventSel=B0H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS.DEMAND_RFO Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. EventSel=B0H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Demand Data Read requests who miss L3 cache. EventSel=B0H UMask=10H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. EventSel=60H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. EventSel=60H UMask=08H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). EventSel=60H UMask=01H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. EventSel=60H UMask=04H CMask=1
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core. EventSel=60H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue. EventSel=60H UMask=01H CMask=6
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion. EventSel=60H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
RESOURCE_STALLS.SB Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end. EventSel=A2H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
RESOURCE_STALLS.SCOREBOARD Counts cycles where the pipeline is stalled due to serializing operations. EventSel=A2H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
RS_EVENTS.EMPTY_CYCLES Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses) EventSel=5EH UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
RS_EVENTS.EMPTY_END Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) EventSel=5EH UMask=01H EdgeDetect=1 Invert=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
RTM_RETIRED.ABORTED Counts the number of times RTM abort was triggered. EventSel=C9H UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.ABORTED_EVENTS Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt). EventSel=C9H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.ABORTED_MEM Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts). EventSel=C9H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.ABORTED_MEMTYPE Counts the number of times an RTM execution aborted due to incompatible memory type. EventSel=C9H UMask=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.ABORTED_UNFRIENDLY Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions. EventSel=C9H UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.COMMIT Counts the number of times RTM commit succeeded. EventSel=C9H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
RTM_RETIRED.START Counts the number of times we entered an RTM region. Does not count nested transactions. EventSel=C9H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
SQ_MISC.SQ_FULL Counts the cycles for which the thread is active and the superQ cannot take any more entries. EventSel=F4H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
SW_PREFETCH_ACCESS.NTA Counts the number of PREFETCHNTA instructions executed. EventSel=32H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
SW_PREFETCH_ACCESS.PREFETCHW Counts the number of PREFETCHW instructions executed. EventSel=32H UMask=08H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
SW_PREFETCH_ACCESS.T0 Counts the number of PREFETCHT0 instructions executed. EventSel=32H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
SW_PREFETCH_ACCESS.T1_T2 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. EventSel=32H UMask=04H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TLB_FLUSH.DTLB_THREAD Counts the number of DTLB flush attempts of the thread-specific entries. EventSel=BDH UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TLB_FLUSH.STLB_ANY Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.). EventSel=BDH UMask=20H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN.BACKEND_BOUND_SLOTS Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources. EventSel=A4H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
TOPDOWN.BR_MISPREDICT_SLOTS Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction. EventSel=A4H UMask=08H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
TX_EXEC.MISC2 Counts Unfriendly TSX abort triggered by a vzeroupper instruction. EventSel=5DH UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
TX_EXEC.MISC3 Counts Unfriendly TSX abort triggered by a nest count that is too deep. EventSel=5DH UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
TX_MEM.ABORT_CAPACITY_READ Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads EventSel=54H UMask=80H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TX_MEM.ABORT_CAPACITY_WRITE Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes. EventSel=54H UMask=02H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TX_MEM.ABORT_CONFLICT Counts the number of times a TSX line had a cache conflict. EventSel=54H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
UOPS_DECODED.DEC0 Uops exclusively fetched by decoder 0 EventSel=56H UMask=01H
Counter=0,1,2,3 CounterHTOff=0,1,2,3
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_0 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0. EventSel=A1H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_1 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1. EventSel=A1H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_2_3 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3. EventSel=A1H UMask=04H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_4_9 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9. EventSel=A1H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_5 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5. EventSel=A1H UMask=20H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_6 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6. EventSel=A1H UMask=40H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_DISPATCHED.PORT_7_8 Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8. EventSel=A1H UMask=80H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CORE Counts the number of uops executed from any thread. EventSel=B1H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CORE_CYCLES_GE_1 Counts cycles when at least 1 micro-op is executed from any thread on physical core. EventSel=B1H UMask=02H CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CORE_CYCLES_GE_2 Counts cycles when at least 2 micro-ops are executed from any thread on physical core. EventSel=B1H UMask=02H CMask=2
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CORE_CYCLES_GE_3 Counts cycles when at least 3 micro-ops are executed from any thread on physical core. EventSel=B1H UMask=02H CMask=3
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CORE_CYCLES_GE_4 Counts cycles when at least 4 micro-ops are executed from any thread on physical core. EventSel=B1H UMask=02H CMask=4
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CYCLES_GE_1 Cycles where at least 1 uop was executed per-thread. EventSel=B1H UMask=01H CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CYCLES_GE_2 Cycles where at least 2 uops were executed per-thread. EventSel=B1H UMask=01H CMask=2
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CYCLES_GE_3 Cycles where at least 3 uops were executed per-thread. EventSel=B1H UMask=01H CMask=3
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.CYCLES_GE_4 Cycles where at least 4 uops were executed per-thread. EventSel=B1H UMask=01H CMask=4
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.STALL_CYCLES Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. EventSel=B1H UMask=01H Invert=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.THREAD Counts the number of uops to be executed per-thread each cycle. EventSel=B1H UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_EXECUTED.X87 Counts the number of x87 uops executed. EventSel=B1H UMask=10H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_ISSUED.ANY Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS). EventSel=0EH UMask=01H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_ISSUED.STALL_CYCLES Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread. EventSel=0EH UMask=01H Invert=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_ISSUED.VECTOR_WIDTH_MISMATCH Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to “Mixing Intel AVX and Intel SSE Code” section of the Optimization Guide. EventSel=0EH UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
Speculative
CoreOnly
UOPS_RETIRED.SLOTS Counts the retirement slots used each cycle. EventSel=C2H UMask=02H
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
UOPS_RETIRED.STALL_CYCLES This event counts cycles without actually retired uops. EventSel=C2H UMask=02H Invert=1 CMask=1
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
UOPS_RETIRED.TOTAL_CYCLES Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event. EventSel=C2H UMask=02H Invert=1 CMask=10
Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
AtRetirement
CoreOnly
UNCORE Uncore
UNC_ARB_TRK_OCCUPANCY.ALL Each cycle count number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from it's allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. EventSel=80H UMask=01H
Counter=0
Uncore
UNC_MC0_RDCAS_COUNT_FREERUN Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=1
Uncore
UNC_MC0_TOTAL_REQCOUNT_FREERUN Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=0
Uncore
UNC_MC0_WRCAS_COUNT_FREERUN Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=2
Uncore
UNC_MC1_RDCAS_COUNT_FREERUN Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=4
Uncore
UNC_MC1_TOTAL_REQCOUNT_FREERUN Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=3
Uncore
UNC_MC1_WRCAS_COUNT_FREERUN Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=5
Uncore
UNC_MC0_RDCAS_COUNT_FREERUN Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=1
Uncore
UNC_MC0_TOTAL_REQCOUNT_FREERUN Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=0
Uncore
UNC_MC0_WRCAS_COUNT_FREERUN Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=2
Uncore
UNC_MC1_RDCAS_COUNT_FREERUN Counts every read (RdCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=4
Uncore
UNC_MC1_TOTAL_REQCOUNT_FREERUN Counts every 64B read and write request entering the Memory Controller to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=3
Uncore
UNC_MC1_WRCAS_COUNT_FREERUN Counts every write (WrCAS) issued by the Memory Controller to DRAM (sum of all channels). All requests result in 64 byte data transfers from DRAM.
Errata: 0
EventSel=00H UMask=00H
Counter=5
Uncore
OFFCORE Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H Offcore
OCR.STREAMING_WR.ANY_RESPONSE OCR.STREAMING_WR.ANY_RESPONSE EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H Offcore