| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. | IA32_FIXED_CTR0 PEBS:[PreciseEventingIP] Architectural, Fixed, AtRetirement |
| CPU_CLK_UNHALTED.THREAD | Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. | IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.REF_TSC | Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. | IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| TOPDOWN.SLOTS | Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). | IA32_FIXED_CTR3 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| BR_INST_RETIRED.ALL_BRANCHES | Counts all branch instructions retired. | EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES | Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. | EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| CPU_CLK_UNHALTED.THREAD_P | This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. | EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| INST_RETIRED.ANY_P | Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. | EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=1,2,3,4,5,6,7] Architectural, AtRetirement |
| LONGEST_LAT_CACHE.MISS | LONGEST_LAT_CACHE.MISS | EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| TOPDOWN.SLOTS_P | Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. | EventSel=A4H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| AMX_OPS_RETIRED.BF16 | AMX_OPS_RETIRED.BF16 | EventSel=CEH UMask=02H Counter=0 CounterHTOff=0 PEBS:[Counter=0] AtRetirement |
| AMX_OPS_RETIRED.INT8 | AMX_OPS_RETIRED.INT8 | EventSel=CEH UMask=01H Counter=0 CounterHTOff=0 PEBS:[Counter=0] AtRetirement |
| ARITH.DIV_ACTIVE | Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. | EventSel=B0H UMask=09H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_ACTIVE | ARITH.FPDIV_ACTIVE | EventSel=B0H UMask=01H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.IDIV_ACTIVE | This event counts the cycles the integer divider is busy. | EventSel=B0H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.ANY | Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists. | EventSel=C1H UMask=1FH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.FP | Counts all microcode Floating Point assists. | EventSel=C1H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.PAGE_FAULT | ASSISTS.PAGE_FAULT | EventSel=C1H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.SSE_AVX_MIX | ASSISTS.SSE_AVX_MIX | EventSel=C1H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BR_INST_RETIRED.COND | Counts conditional branch instructions retired. | EventSel=C4H UMask=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_NTAKEN | Counts not taken branch instructions retired. | EventSel=C4H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN | Counts taken conditional branch instructions retired. | EventSel=C4H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH | Counts far branch instructions retired. | EventSel=C4H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT | Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. | EventSel=C4H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL | Counts both direct and indirect near call instructions retired. | EventSel=C4H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN | Counts return instructions retired. | EventSel=C4H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN | Counts taken branch instructions retired. | EventSel=C4H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND | Counts mispredicted conditional branch instructions retired. | EventSel=C5H UMask=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_NTAKEN | Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. | EventSel=C5H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN | Counts taken conditional mispredicted branch instructions retired. | EventSel=C5H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT | Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. | EventSel=C5H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL | Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. | EventSel=C5H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN | Counts number of near branch instructions retired that were mispredicted and taken. | EventSel=C5H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.RET | This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. | EventSel=C5H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| CPU_CLK_UNHALTED.C0_WAIT | Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction. | EventSel=ECH UMask=70H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.C01 | Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. | EventSel=ECH UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.C02 | Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. | EventSel=ECH UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.DISTRIBUTED | This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. | EventSel=ECH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE | Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted. | EventSel=3CH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.PAUSE | CPU_CLK_UNHALTED.PAUSE | EventSel=ECH UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.PAUSE_INST | CPU_CLK_UNHALTED.PAUSE_INST | EventSel=ECH UMask=40H EdgeDetect=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.REF_DISTRIBUTED | This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. | EventSel=3CH UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] Speculative |
| CYCLE_ACTIVITY.CYCLES_L1D_MISS | Cycles while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=08H CMask=8 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.CYCLES_L2_MISS | Cycles while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=01H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.CYCLES_MEM_ANY | Cycles while memory subsystem has an outstanding load. | EventSel=A3H UMask=10H CMask=16 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CYCLE_ACTIVITY.STALLS_L1D_MISS | Execution stalls while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=0CH CMask=12 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_L2_MISS | Execution stalls while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=05H CMask=5 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_L3_MISS | Execution stalls while L3 cache miss demand load is outstanding. | EventSel=A3H UMask=06H CMask=6 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_TOTAL | Total execution stalls. | EventSel=A3H UMask=04H CMask=4 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DECODE.LCP | Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. | EventSel=87H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DSB2MITE_SWITCHES.PENALTY_CYCLES | Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE. | EventSel=61H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.STLB_HIT | Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). | EventSel=12H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. | EventSel=12H UMask=10H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=12H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_1G | Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=12H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=12H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=12H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_PENDING | Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. | EventSel=12H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.STLB_HIT | Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). | EventSel=13H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. | EventSel=13H UMask=10H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=13H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_1G | Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=13H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=13H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=13H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_PENDING | Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. | EventSel=13H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| EXE.AMX_BUSY | Counts the cycles where the AMX (Advance Matrix Extension) unit is busy performing an operation. | EventSel=B7H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.1_PORTS_UTIL | Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.2_PORTS_UTIL | Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.3_PORTS_UTIL | Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.4_PORTS_UTIL | Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.BOUND_ON_LOADS | Execution stalls while memory subsystem has an outstanding load. | EventSel=A6H UMask=21H CMask=33 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.BOUND_ON_STORES | Counts cycles where the Store Buffer was full and no loads caused an execution stall. | EventSel=A6H UMask=40H CMask=2 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.EXE_BOUND_0_PORTS | Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load. | EventSel=A6H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_ARITH_DISPATCHED.PORT_0 | FP_ARITH_DISPATCHED.PORT_0 | EventSel=B3H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_ARITH_DISPATCHED.PORT_1 | FP_ARITH_DISPATCHED.PORT_1 | EventSel=B3H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_ARITH_DISPATCHED.PORT_5 | FP_ARITH_DISPATCHED.PORT_5 | EventSel=B3H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE | Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE | Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE | Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE | Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE | Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE | Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.SCALAR_DOUBLE | Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.SCALAR_SINGLE | Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.128B_PACKED_HALF | FP_ARITH_INST_RETIRED2.128B_PACKED_HALF | EventSel=CFH UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.256B_PACKED_HALF | FP_ARITH_INST_RETIRED2.256B_PACKED_HALF | EventSel=CFH UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.512B_PACKED_HALF | FP_ARITH_INST_RETIRED2.512B_PACKED_HALF | EventSel=CFH UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF | FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF | EventSel=CFH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.SCALAR | FP_ARITH_INST_RETIRED2.SCALAR | EventSel=CFH UMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.SCALAR_HALF | FP_ARITH_INST_RETIRED2.SCALAR_HALF | EventSel=CFH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED2.VECTOR | FP_ARITH_INST_RETIRED2.VECTOR | EventSel=CFH UMask=1CH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ANY_DSB_MISS | Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.DSB_MISS | Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS | Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=14H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.L1I_MISS | Counts retired Instructions who experienced Instruction L1 Cache true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=12H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.L2_MISS | Counts retired Instructions who experienced Instruction L2 Cache true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=13H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_1 | Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=600106H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_128 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=608006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_16 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=601006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2 | Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=600206H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 | Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=100206H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_256 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=610006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_32 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=602006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_4 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=600406H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_512 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=620006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_64 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=604006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_8 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=600806H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.MS_FLOWS | FRONTEND_RETIRED.MS_FLOWS | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.STLB_MISS | Counts retired Instructions that experienced STLB (2nd level TLB) true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=15H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.UNKNOWN_BRANCH | FRONTEND_RETIRED.UNKNOWN_BRANCH | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=17H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| ICACHE_DATA.STALLS | Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity. | EventSel=80H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ICACHE_TAG.STALLS | Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. | EventSel=83H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_CYCLES_ANY | Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. | EventSel=79H UMask=08H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_CYCLES_OK | Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=08H CMask=6 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_UOPS | Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. | EventSel=79H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_CYCLES_ANY | Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_CYCLES_OK | Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H CMask=6 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_UOPS | Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MS_CYCLES_ANY | Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. | EventSel=79H UMask=20H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MS_SWITCHES | Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. | EventSel=79H UMask=20H EdgeDetect=1 CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MS_UOPS | Counts the total number of uops delivered by the Microcode Sequencer (MS). | EventSel=79H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CORE | Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE | Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H CMask=6 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK | Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H Invert=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INST_DECODED.DECODERS | Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions. | EventSel=75H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| INST_RETIRED.MACRO_FUSED | INST_RETIRED.MACRO_FUSED | EventSel=C0H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=1,2,3,4,5,6,7] AtRetirement |
| INST_RETIRED.NOP | Number of all retired NOP instructions. | EventSel=C0H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=1,2,3,4,5,6,7] AtRetirement |
| INST_RETIRED.PREC_DIST | A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0. | IA32_FIXED_CTR0 PEBS:[PreciseEventingIP] Fixed, AtRetirement |
| INST_RETIRED.REP_ITERATION | INST_RETIRED.REP_ITERATION | EventSel=C0H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=1,2,3,4,5,6,7] AtRetirement |
| INT_MISC.CLEAR_RESTEER_CYCLES | Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. | EventSel=ADH UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.MBA_STALLS | INT_MISC.MBA_STALLS | EventSel=ADH UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.RECOVERY_CYCLES | Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event. | EventSel=ADH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.UNKNOWN_BRANCH_CYCLES | INT_MISC.UNKNOWN_BRANCH_CYCLES | EventSel=ADH UMask=40H MSR_PEBS_FRONTEND(3F7H)=07H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.UOP_DROPPING | Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons | EventSel=ADH UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_VEC_RETIRED.128BIT | INT_VEC_RETIRED.128BIT | EventSel=E7H UMask=13H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.256BIT | INT_VEC_RETIRED.256BIT | EventSel=E7H UMask=ACH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.ADD_128 | Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions. | EventSel=E7H UMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.ADD_256 | Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions. | EventSel=E7H UMask=0CH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.MUL_256 | INT_VEC_RETIRED.MUL_256 | EventSel=E7H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.SHUFFLES | INT_VEC_RETIRED.SHUFFLES | EventSel=E7H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.VNNI_128 | INT_VEC_RETIRED.VNNI_128 | EventSel=E7H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INT_VEC_RETIRED.VNNI_256 | INT_VEC_RETIRED.VNNI_256 | EventSel=E7H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| ITLB_MISSES.STLB_HIT | Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). | EventSel=11H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. | EventSel=11H UMask=10H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=11H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=11H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=11H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_PENDING | Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. | EventSel=11H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D.HWPF_MISS | L1D.HWPF_MISS | EventSel=51H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D.REPLACEMENT | Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. | EventSel=51H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.FB_FULL | Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.FB_FULL_PERIODS | Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=02H EdgeDetect=1 CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.L2_STALLS | Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.PENDING | Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. | EventSel=48H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.PENDING_CYCLES | Counts duration of L1D miss outstanding in cycles. | EventSel=48H UMask=01H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_IN.ALL | Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. | EventSel=25H UMask=1FH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_OUT.NON_SILENT | L2_LINES_OUT.NON_SILENT | EventSel=26H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_OUT.SILENT | Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event. | EventSel=26H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_CODE_RD | Counts the total number of L2 code requests. | EventSel=24H UMask=E4H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_DEMAND_DATA_RD | Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. | EventSel=24H UMask=E1H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_DEMAND_MISS | Counts demand requests that miss L2 cache. | EventSel=24H UMask=27H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_DEMAND_REFERENCES | Counts demand requests to L2 cache. | EventSel=24H UMask=E7H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_HWPF | L2_RQSTS.ALL_HWPF | EventSel=24H UMask=F0H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_RFO | Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. | EventSel=24H UMask=E2H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.CODE_RD_HIT | Counts L2 cache hits when fetching instructions, code reads. | EventSel=24H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.CODE_RD_MISS | Counts L2 cache misses when fetching instructions. | EventSel=24H UMask=24H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_HIT | Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. | EventSel=24H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_MISS | Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. | EventSel=24H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.HWPF_MISS | L2_RQSTS.HWPF_MISS | EventSel=24H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.MISS | Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. | EventSel=24H UMask=3FH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.REFERENCES | Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. | EventSel=24H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.RFO_HIT | Counts the RFO (Read-for-Ownership) requests that hit L2 cache. | EventSel=24H UMask=C2H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.RFO_MISS | Counts the RFO (Read-for-Ownership) requests that miss L2 cache. | EventSel=24H UMask=22H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.SWPF_HIT | Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. | EventSel=24H UMask=C8H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.SWPF_MISS | Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. | EventSel=24H UMask=28H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS.ADDRESS_ALIAS | Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address. | EventSel=03H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS.NO_SR | Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. | EventSel=03H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS.STORE_FORWARD | Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide. | EventSel=03H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LOAD_HIT_PREFETCH.SWPF | Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. | EventSel=4CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LSD.CYCLES_ACTIVE | Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). | EventSel=A8H UMask=01H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LSD.CYCLES_OK | Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). | EventSel=A8H UMask=01H CMask=6 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LSD.UOPS | Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). | EventSel=A8H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.COUNT | Counts the number of machine clears (nukes) of any type. | EventSel=C3H UMask=01H EdgeDetect=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING | Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture | EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SMC | Counts self-modifying code (SMC) detected, which causes a machine clear. | EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_INST_RETIRED.ALL_LOADS | Counts all retired load instructions. This event accounts for SW prefetch instructions for loads. | EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.ALL_STORES | Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores. | EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.ANY | Counts all retired memory instructions - loads and stores. | EventSel=D0H UMask=83H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.LOCK_LOADS | Counts retired load instructions with locked access. | EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.SPLIT_LOADS | Counts retired load instructions that split across a cacheline boundary. | EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.SPLIT_STORES | Counts retired store instructions that split across a cacheline boundary. | EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_LOADS | Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). | EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_STORES | Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). | EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_COMPLETED.L1_MISS_ANY | Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) | EventSel=43H UMask=FDH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD | Counts retired load instructions whose data sources were HitM responses from shared L3. | EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS | Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. | EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD | Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. | EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE | Counts retired load instructions whose data sources were hits in L3 without snoops required. | EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM | Retired load instructions which data sources missed L3 but serviced from local DRAM. | EventSel=D3H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM | MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM | EventSel=D3H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD | Retired load instructions whose data sources was forwarded from a remote cache. | EventSel=D3H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM | MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM | EventSel=D3H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM | Counts retired load instructions with remote Intel® Optane™ DC persistent memory as the data source and the data request missed L3. | EventSel=D3H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_MISC_RETIRED.UC | Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). | EventSel=D4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.FB_HIT | Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. | EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L1_HIT | Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. | EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L1_MISS | Counts retired load instructions with at least one uop that missed in the L1 cache. | EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L2_HIT | Counts retired load instructions with L2 cache hits as data sources. | EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L2_MISS | Counts retired load instructions missed L2 cache as data sources. | EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L3_HIT | Counts retired load instructions with at least one uop that hit in the L3 cache. | EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L3_MISS | Counts retired load instructions with at least one uop that missed in the L3 cache. | EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.LOCAL_PMM | Counts retired load instructions with local Intel® Optane™ DC persistent memory as the data source and the data request missed L3. | EventSel=D1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_STORE_RETIRED.L2_HIT | MEM_STORE_RETIRED.L2_HIT | EventSel=44H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.STORE_SAMPLE | Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 | EventSel=CDH UMask=02H Counter=0 CounterHTOff=0 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0] AtRetirement |
| MEM_UOP_RETIRED.ANY | Number of retired micro-operations (uops) for load or store memory accesses | EventSel=E5H UMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEMORY_ACTIVITY.CYCLES_L1D_MISS | Cycles while L1 cache miss demand load is outstanding. | EventSel=47H UMask=02H CMask=2 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MEMORY_ACTIVITY.STALLS_L1D_MISS | Execution stalls while L1 cache miss demand load is outstanding. | EventSel=47H UMask=03H CMask=3 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MEMORY_ACTIVITY.STALLS_L2_MISS | MEMORY_ACTIVITY.STALLS_L2_MISS | EventSel=47H UMask=05H CMask=5 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MEMORY_ACTIVITY.STALLS_L3_MISS | MEMORY_ACTIVITY.STALLS_L3_MISS | EventSel=47H UMask=09H CMask=9 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MISC_RETIRED.LBR_INSERTS | Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT. | EventSel=CCH UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISC2_RETIRED.LFENCE | MISC2_RETIRED.LFENCE | EventSel=E0H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| OFFCORE_REQUESTS.ALL_REQUESTS | OFFCORE_REQUESTS.ALL_REQUESTS | EventSel=21H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.DATA_RD | Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. | EventSel=21H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.DEMAND_DATA_RD | Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. | EventSel=21H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD | OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD | EventSel=20H UMask=08H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO | OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO | EventSel=20H UMask=04H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DATA_RD | OFFCORE_REQUESTS_OUTSTANDING.DATA_RD | EventSel=20H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| RESOURCE_STALLS.SB | Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end. | EventSel=A2H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RESOURCE_STALLS.SCOREBOARD | Counts cycles where the pipeline is stalled due to serializing operations. | EventSel=A2H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RS_EMPTY.CYCLES | Counts cycles during which the reservation station (RS) is empty for this logical processor. | EventSel=A5H UMask=07H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RTM_RETIRED.ABORTED | Counts the number of times RTM abort was triggered. | EventSel=C9H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_EVENTS | Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt). | EventSel=C9H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_MEM | Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts). | EventSel=C9H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_MEMTYPE | Counts the number of times an RTM execution aborted due to incompatible memory type. | EventSel=C9H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_UNFRIENDLY | Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions. | EventSel=C9H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.COMMIT | Counts the number of times RTM commit succeeded. | EventSel=C9H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.START | Counts the number of times we entered an RTM region. Does not count nested transactions. | EventSel=C9H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| SW_PREFETCH_ACCESS.NTA | Counts the number of PREFETCHNTA instructions executed. | EventSel=40H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.PREFETCHW | Counts the number of PREFETCHW instructions executed. | EventSel=40H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.T0 | Counts the number of PREFETCHT0 instructions executed. | EventSel=40H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.T1_T2 | Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. | EventSel=40H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TOPDOWN.BACKEND_BOUND_SLOTS | Number of slots in TMA method where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources. | EventSel=A4H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN.BAD_SPEC_SLOTS | Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations. | EventSel=A4H UMask=04H Counter=0 CounterHTOff=0 PEBS:[NonPreciseEventingIP, Counter=0] Speculative |
| TOPDOWN.BR_MISPREDICT_SLOTS | Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of specualtive operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction. | EventSel=A4H UMask=08H Counter=0 CounterHTOff=0 PEBS:[NonPreciseEventingIP, Counter=0] Speculative |
| TOPDOWN.MEMORY_BOUND_SLOTS | TOPDOWN.MEMORY_BOUND_SLOTS | EventSel=A4H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TX_MEM.ABORT_CAPACITY_READ | Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads | EventSel=54H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TX_MEM.ABORT_CAPACITY_WRITE | Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes. | EventSel=54H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TX_MEM.ABORT_CONFLICT | Counts the number of times a TSX line had a cache conflict. | EventSel=54H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| UOPS_DECODED.DEC0_UOPS | UOPS_DECODED.DEC0_UOPS | EventSel=76H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| UOPS_DISPATCHED.PORT_0 | Number of uops dispatch to execution port 0. | EventSel=B2H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_1 | Number of uops dispatch to execution port 1. | EventSel=B2H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_2_3_10 | Number of uops dispatch to execution ports 2, 3 and 10 | EventSel=B2H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_4_9 | Number of uops dispatch to execution ports 4 and 9 | EventSel=B2H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_5_11 | Number of uops dispatch to execution ports 5 and 11 | EventSel=B2H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_6 | Number of uops dispatch to execution port 6. | EventSel=B2H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_7_8 | Number of uops dispatch to execution ports 7 and 8. | EventSel=B2H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE | Counts the number of uops executed from any thread. | EventSel=B1H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_1 | Counts cycles when at least 1 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_2 | Counts cycles when at least 2 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=2 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_3 | Counts cycles when at least 3 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=3 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_4 | Counts cycles when at least 4 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=4 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_1 | Cycles where at least 1 uop was executed per-thread. | EventSel=B1H UMask=01H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_2 | Cycles where at least 2 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=2 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_3 | Cycles where at least 3 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=3 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_4 | Cycles where at least 4 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=4 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.STALLS | Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. | EventSel=B1H UMask=01H Invert=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.THREAD | Counts the number of uops to be executed per-thread each cycle. | EventSel=B1H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.X87 | Counts the number of x87 uops executed. | EventSel=B1H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_ISSUED.ANY | Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS). | EventSel=AEH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.CYCLES | Counts cycles where at least one uop has retired. | EventSel=C2H UMask=02H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.HEAVY | Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count. | EventSel=C2H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.MS | UOPS_RETIRED.MS | EventSel=C2H UMask=04H MSR_PEBS_FRONTEND(3F7H)=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.SLOTS | Counts the retirement slots used each cycle. | EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.STALLS | This event counts cycles without actually retired uops. | EventSel=C2H UMask=02H Invert=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| XQ.FULL_CYCLES | XQ.FULL_CYCLES | EventSel=2DH UMask=01H CMask=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ARITH.DIVIDER_ACTIVE | This event is deprecated. Refer to new event ARITH.DIV_ACTIVE | EventSel=B0H UMask=09H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative, Deprecated |
| ARITH.FP_DIVIDER_ACTIVE | This event is deprecated. Refer to new event ARITH.FPDIV_ACTIVE | EventSel=B0H UMask=01H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative, Deprecated |
| ARITH.INT_DIVIDER_ACTIVE | This event is deprecated. Refer to new event ARITH.IDIV_ACTIVE | EventSel=B0H UMask=08H CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative, Deprecated |
| L1D_PEND_MISS.L2_STALL | This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS | EventSel=48H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative, Deprecated |
| OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD | This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD | EventSel=20H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative, Deprecated |
| UOPS_EXECUTED.STALL_CYCLES | This event is deprecated. Refer to new event UOPS_EXECUTED.STALLS | EventSel=B1H UMask=01H Invert=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative, Deprecated |
| UOPS_RETIRED.STALL_CYCLES | This event is deprecated. Refer to new event UOPS_RETIRED.STALLS | EventSel=C2H UMask=02H Invert=1 CMask=1 Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| UNCORE | ||
| UNC_U_CLOCKTICKS | Clockticks in the UBOX using a dedicated 48-bit Fixed Counter when the UBOX is not idle. | MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_CHA_CLOCKTICKS | Number of CHA clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE | Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. | EventSel=50H UMask=30H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL | Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). | EventSel=50H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_REMOTE | Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). | EventSel=50H UMask=02H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL | Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. | EventSel=50H UMask=04H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_REMOTE | Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc). | EventSel=50H UMask=08H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode CRd | EventSel=35H UMask=01H UMaskExt=00C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd | EventSel=35H UMask=01H UMaskExt=00C817FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory | EventSel=35H UMask=01H UMaskExt=00C81786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory | EventSel=35H UMask=01H UMaskExt=00C816FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory | EventSel=35H UMask=01H UMaskExt=00C8178AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF | EventSel=35H UMask=01H UMaskExt=00C897FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target local memory | EventSel=35H UMask=01H UMaskExt=00C896FEH FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRD_PREF, and target remote memory | EventSel=35H UMask=01H UMaskExt=00C8977EH FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE | Inserts into the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and target remote memory | EventSel=35H UMask=01H UMaskExt=00C8177EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM | Inserts into the TOR from local IO with the opcode ItoM | EventSel=35H UMask=04H UMaskExt=00CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR | Inserts into the TOR from local IO devices with the opcode ItoMCacheNears. This event indicates a partial write request. | EventSel=35H UMask=04H UMaskExt=00CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR | Inserts into the TOR from local IO with the opcode RdCur | EventSel=35H UMask=04H UMaskExt=00C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD | Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd | EventSel=36H UMask=01H UMaskExt=00C817FEH FCMask=00H PortMask=00H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR | Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target DDR memory | EventSel=36H UMask=01H UMaskExt=00C81786H FCMask=00H PortMask=00H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL | Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target local memory | EventSel=36H UMask=01H UMaskExt=00C816FEH FCMask=00H PortMask=00H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM | Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target PMM memory | EventSel=36H UMask=01H UMaskExt=00C8178AH FCMask=00H PortMask=00H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE | Number of cycles for elements in the TOR from local IA cores which miss the LLC and snoop filter with the opcode DRd, and which target remote memory | EventSel=36H UMask=01H UMaskExt=00C8177EH FCMask=00H PortMask=00H Counter=0 |
| UNC_IIO_CLOCKTICKS | Number of IIO clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H FCMask=00H PortMask=0000H Counter=0,1,2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0002H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0004H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0008H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0010H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0020H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0040H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=01H UMaskExt=00000000H FCMask=07H PortMask=0080H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0002H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0004H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0008H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to stack, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0010H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0020H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 1 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0040H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7 | Data requested of the CPU : Card writing to another Card (same or different stack) : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0080H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0001H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0002H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0004H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0008H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0010H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0020H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0040H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7 | Number Transactions requested of the CPU : Card writing to another Card (same or different stack) : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=84H UMask=02H UMaskExt=00000000H FCMask=07H PortMask=0080H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD | DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Read CAS commands issued on this channel. This includes underfills. | EventSel=05H UMask=CFH UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD_REG | DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills). | EventSel=05H UMask=C1H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD_UNDERFILL | DRAM RD_CAS and WR_CAS Commands. : Underfill Read Issued : DRAM RD_CAS and WR_CAS Commands | EventSel=05H UMask=C4H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR | DRAM RD_CAS and WR_CAS Commands : Counts the total number of DRAM Write CAS commands issued on this channel. | EventSel=05H UMask=F0H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS | Number of DRAM DCLK clock cycles while the event is enabled | EventSel=01H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_HCLOCKTICKS | Number of DRAM HCLK clock cycles while the event is enabled | EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_INSERTS | Counts number of read requests allocated in the PMM Read Pending Queue. | EventSel=E3H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0 | Accumulates the per cycle occupancy of the PMM Read Pending Queue. | EventSel=E0H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1 | Accumulates the per cycle occupancy of the PMM Read Pending Queue. | EventSel=E0H UMask=02H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_INSERTS | Counts number of write requests allocated in the PMM Write Pending Queue. | EventSel=E7H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL | PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the Write Pending Queue to the PMM DIMM. | EventSel=E4H UMask=03H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0 | PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. | EventSel=E4H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1 | PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. | EventSel=E4H UMask=02H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH0 | Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. | EventSel=10H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH1 | Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. | EventSel=10H UMask=02H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH0 | Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. | EventSel=80H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH1 | Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. | EventSel=81H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH0 | Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. | EventSel=20H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH1 | Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. | EventSel=20H UMask=02H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH0 | Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. | EventSel=82H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH1 | Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. | EventSel=83H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_I_CLOCKTICKS | Number of IRP clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1 |
| UNC_M2M_CLOCKTICKS | Clockticks of the mesh to memory (M2M) | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M2P_CLOCKTICKS | Number of M2P clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M3UPI_CLOCKTICKS | Number of M2UPI clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS | Number of PCU PCLK Clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_UPI_CLOCKTICKS | Number of UPI LL clock cycles while the event is enabled | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_DATA | Valid Flits Sent : All Data : Counts number of data flits across this UPI link. | EventSel=02H UMask=0FH UMaskExt=00000000H Counter=0,1,2,3 |
| OFFCORE | ||
| OCR.DEMAND_DATA_RD.ANY_RESPONSE | OCR.DEMAND_DATA_RD.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_RFO.ANY_RESPONSE | OCR.DEMAND_RFO.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FFC0002H |
| OCR.DEMAND_CODE_RD.ANY_RESPONSE | OCR.DEMAND_CODE_RD.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OCR.HWPF_L1D.ANY_RESPONSE | OCR.HWPF_L1D.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H |
| OCR.STREAMING_WR.ANY_RESPONSE | OCR.STREAMING_WR.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OCR.READS_TO_CORE.ANY_RESPONSE | OCR.READS_TO_CORE.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FFC4477H |
| OCR.HWPF_L3.ANY_RESPONSE | OCR.HWPF_L3.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=12380H |
| OCR.DEMAND_DATA_RD.L3_HIT | OCR.DEMAND_DATA_RD.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0001H |
| OCR.DEMAND_RFO.L3_HIT | OCR.DEMAND_RFO.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT | OCR.DEMAND_CODE_RD.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0004H |
| OCR.READS_TO_CORE.L3_HIT | OCR.READS_TO_CORE.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F003C4477H |
| OCR.STREAMING_WR.L3_HIT | OCR.STREAMING_WR.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80080800H |
| OCR.HWPF_L3.L3_HIT | OCR.HWPF_L3.L3_HIT | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80082380H |
| OCR.STREAMING_WR.L3_MISS_LOCAL | OCR.STREAMING_WR.L3_MISS_LOCAL | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000800H |
| OCR.HWPF_L3.L3_MISS_LOCAL | OCR.HWPF_L3.L3_MISS_LOCAL | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84002380H |
| OCR.READS_TO_CORE.L3_MISS_LOCAL | OCR.READS_TO_CORE.L3_MISS_LOCAL | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F04C04477H |
| OCR.READS_TO_CORE.REMOTE | OCR.READS_TO_CORE.REMOTE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F33004477H |
| OCR.HWPF_L3.REMOTE | OCR.HWPF_L3.REMOTE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=90002380H |
| OCR.DEMAND_DATA_RD.L3_MISS | OCR.DEMAND_DATA_RD.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00001H |
| OCR.DEMAND_CODE_RD.L3_MISS | OCR.DEMAND_CODE_RD.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00004H |
| OCR.DEMAND_RFO.L3_MISS | OCR.DEMAND_RFO.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FC00002H |
| OCR.READS_TO_CORE.L3_MISS | OCR.READS_TO_CORE.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FC04477H |
| OCR.STREAMING_WR.L3_MISS | OCR.STREAMING_WR.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=94000800H |
| OCR.HWPF_L3.L3_MISS | OCR.HWPF_L3.L3_MISS | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=94002380H |
| OCR.DEMAND_DATA_RD.LOCAL_DRAM | OCR.DEMAND_DATA_RD.LOCAL_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000001H |
| OCR.DEMAND_RFO.LOCAL_DRAM | OCR.DEMAND_RFO.LOCAL_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000002H |
| OCR.DEMAND_CODE_RD.LOCAL_DRAM | OCR.DEMAND_CODE_RD.LOCAL_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000004H |
| OCR.READS_TO_CORE.LOCAL_DRAM | OCR.READS_TO_CORE.LOCAL_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104004477H |
| OCR.DEMAND_DATA_RD.REMOTE_DRAM | OCR.DEMAND_DATA_RD.REMOTE_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=730000001H |
| OCR.READS_TO_CORE.REMOTE_DRAM | OCR.READS_TO_CORE.REMOTE_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=730004477H |
| OCR.DEMAND_DATA_RD.DRAM | OCR.DEMAND_DATA_RD.DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000001H |
| OCR.DEMAND_RFO.DRAM | OCR.DEMAND_RFO.DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000002H |
| OCR.DEMAND_CODE_RD.DRAM | OCR.DEMAND_CODE_RD.DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000004H |
| OCR.READS_TO_CORE.DRAM | OCR.READS_TO_CORE.DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C004477H |
| OCR.DEMAND_DATA_RD.REMOTE_PMM | OCR.DEMAND_DATA_RD.REMOTE_PMM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703000001H |
| OCR.READS_TO_CORE.REMOTE_PMM | OCR.READS_TO_CORE.REMOTE_PMM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703004477H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD | OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD | OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C4477H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD | OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H |
| OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=830000001H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD | OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C4477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=830004477H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM | OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM | OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1030000001H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM | OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM | OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM | OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C4477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM | OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1030004477H |
| OCR.DEMAND_DATA_RD.SNC_DRAM | OCR.DEMAND_DATA_RD.SNC_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000001H |
| OCR.DEMAND_RFO.SNC_DRAM | OCR.DEMAND_RFO.SNC_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000002H |
| OCR.DEMAND_CODE_RD.SNC_DRAM | OCR.DEMAND_CODE_RD.SNC_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000004H |
| OCR.READS_TO_CORE.SNC_DRAM | OCR.READS_TO_CORE.SNC_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708004477H |
| OCR.DEMAND_DATA_RD.SNC_CACHE.HITM | OCR.DEMAND_DATA_RD.SNC_CACHE.HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000001H |
| OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD | OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000001H |
| OCR.DEMAND_RFO.SNC_CACHE.HITM | OCR.DEMAND_RFO.SNC_CACHE.HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000002H |
| OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD | OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000002H |
| OCR.DEMAND_CODE_RD.SNC_CACHE.HITM | OCR.DEMAND_CODE_RD.SNC_CACHE.HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000004H |
| OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD | OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000004H |
| OCR.READS_TO_CORE.SNC_CACHE.HITM | OCR.READS_TO_CORE.SNC_CACHE.HITM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008004477H |
| OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD | OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808004477H |
| OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM | OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=70C004477H |
| OCR.READS_TO_CORE.LOCAL_SOCKET_PMM | OCR.READS_TO_CORE.LOCAL_SOCKET_PMM | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=700C04477H |
| OCR.HWPF_L2.ANY_RESPONSE | OCR.HWPF_L2.ANY_RESPONSE | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10070H |
| OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET | OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=70CC04477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD | OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1830004477H |
| OCR.READS_TO_CORE.REMOTE_MEMORY | OCR.READS_TO_CORE.REMOTE_MEMORY | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=733004477H |
| OCR.RFO_TO_CORE.L3_HIT_M | OCR.RFO_TO_CORE.L3_HIT_M | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1F80040022H |
| OCR.WRITE_ESTIMATE.MEMORY | OCR.WRITE_ESTIMATE.MEMORY | EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=FBFF80822H |