Intel Atom® Processors based on SnowRidge microarchitecture
This section provides reference for hardware events that can be monitored for the CPU(s):
Event Name Description Additional Info EventType
CORE CoreOnly
INST_RETIRED.ANY Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. IA32_FIXED_CTR0
PEBS:[PreciseEventingIP, PDISTCounter=0]
Architectural, Fixed, AtRetirement
CoreOnly
CPU_CLK_UNHALTED.CORE Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. IA32_FIXED_CTR1
PEBS:[NonPreciseEventingIP]
Architectural, Fixed, Speculative
CoreOnly
CPU_CLK_UNHALTED.REF_TSC Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2. IA32_FIXED_CTR2
PEBS:[NonPreciseEventingIP]
Architectural, Fixed, Speculative
CoreOnly
BR_INST_RETIRED.ALL_BRANCHES Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. EventSel=C4H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
Architectural, AtRetirement
CoreOnly
BR_MISP_RETIRED.ALL_BRANCHES Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. EventSel=C5H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
Architectural, AtRetirement
CoreOnly
CPU_CLK_UNHALTED.CORE_P Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter. EventSel=3CH UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Architectural, Speculative
CoreOnly
CPU_CLK_UNHALTED.REF Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2. EventSel=3CH UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Architectural, Speculative
CoreOnly
CPU_CLK_UNHALTED.REF_TSC_P Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. EventSel=3CH UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Architectural, Speculative
CoreOnly
INST_RETIRED.ANY_P Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. EventSel=C0H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
Architectural, AtRetirement
CoreOnly
LONGEST_LAT_CACHE.MISS Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. EventSel=2EH UMask=41H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Architectural, Speculative
CoreOnly
LONGEST_LAT_CACHE.REFERENCE Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. EventSel=2EH UMask=4FH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Architectural, Speculative
CoreOnly
BACLEARS.ANY Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. EventSel=E6H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BACLEARS.COND Counts the number of BACLEARS due to a conditional jump. EventSel=E6H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BACLEARS.INDIRECT Counts the number of BACLEARS due to an indirect branch. EventSel=E6H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BACLEARS.RETURN Counts the number of BACLEARS due to a return branch. EventSel=E6H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BACLEARS.UNCOND Counts the number of BACLEARS due to a direct, unconditional jump. EventSel=E6H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BR_INST_RETIRED.CALL Counts the number of near CALL branch instructions retired. EventSel=C4H UMask=F9H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.FAR_BRANCH Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. EventSel=C4H UMask=BFH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.IND_CALL Counts the number of near indirect CALL branch instructions retired. EventSel=C4H UMask=FBH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.JCC Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. EventSel=C4H UMask=7EH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.NON_RETURN_IND Counts the number of near indirect JMP and near indirect CALL branch instructions retired. EventSel=C4H UMask=EBH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.REL_CALL Counts the number of near relative CALL branch instructions retired. EventSel=C4H UMask=FDH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.RETURN Counts the number of near RET branch instructions retired. EventSel=C4H UMask=F7H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_INST_RETIRED.TAKEN_JCC Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. EventSel=C4H UMask=FEH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_MISP_RETIRED.IND_CALL Counts the number of mispredicted near indirect CALL branch instructions retired. EventSel=C5H UMask=FBH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_MISP_RETIRED.JCC Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. EventSel=C5H UMask=7EH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_MISP_RETIRED.NON_RETURN_IND Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. EventSel=C5H UMask=EBH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_MISP_RETIRED.RETURN Counts the number of mispredicted near RET branch instructions retired. EventSel=C5H UMask=F7H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BR_MISP_RETIRED.TAKEN_JCC Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. EventSel=C5H UMask=FEH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BTCLEAR.ANY Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch. EventSel=E8H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BUS_LOCK.BLOCK_CYCLES Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis. EventSel=63H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BUS_LOCK.LOCK_CYCLES Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis. EventSel=63H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
BUS_LOCK.SELF_LOCKS Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis. EventSel=63H UMask=00H EdgeDetect=1
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CORE_REJECT_L2Q.ANY Counts the number of (demand and L1 prefetchers) core requests rejected by the L2 queue (L2Q) due to a full or nearly full condition, which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the External Queue (XQ), but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to ensure fairness between cores, or to delay a core’s dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event). Counts on a per core basis. EventSel=31H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLES_DIV_BUSY.FPDIV Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider. EventSel=CDH UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
CYCLES_DIV_BUSY.IDIV Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider. EventSel=CDH UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DECODE_RESTRICTION.PREDECODE_WRONG Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction. EventSel=E9H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DL1.DIRTY_EVICTION Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back. EventSel=51H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.PDE_CACHE_MISS Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache. EventSel=08H UMask=80H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for all page sizes. Will result in a DTLB write from STLB. EventSel=08H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=08H UMask=0EH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED_1G Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=08H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=08H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=08H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_LOAD_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for demand loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. EventSel=08H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.PDE_CACHE_MISS Counts the number of page walks due to stores that miss the PDE (Page Directory Entry) cache. EventSel=49H UMask=80H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB. EventSel=49H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=49H UMask=0EH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED_1G Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=49H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=49H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=49H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
DTLB_STORE_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. EventSel=49H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EPT.EPDE_HIT Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EPT.EPDE_MISS Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EPT.EPDPE_HIT Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EPT.EPDPE_MISS Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
EPT.WALK_PENDING Counts the number of page walks outstanding for an Extended Page table walk including GTLB hits per cycle. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
HW_INTERRUPTS.MASKED Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not. EventSel=CBH UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
HW_INTERRUPTS.PENDING_AND_MASKED Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APIC’s Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) – because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important. EventSel=CBH UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
HW_INTERRUPTS.RECEIVED Counts the number of hardware interrupts received by the processor. EventSel=CBH UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE.ACCESSES Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. EventSel=80H UMask=03H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE.HIT Counts the number of requests that hit in the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. EventSel=80H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ICACHE.MISSES Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. EventSel=80H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB.FILLS Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB. EventSel=81H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.PDE_CACHE_MISS Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache. EventSel=85H UMask=80H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB. EventSel=85H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=85H UMask=0EH
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED_1G Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that page fault.
Errata: https://hsdes.intel.com/appstore/article/#/2207773177
EventSel=85H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=85H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=85H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
ITLB_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). EventSel=85H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_REJECT_XQ.ANY Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims). EventSel=30H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_REQUEST.ALL Counts the total number of L2 Cache Accesses, includes hits, misses, rejects – front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only. Counts on a per core basis. EventSel=24H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_REQUEST.HIT Counts the number of L2 Cache accesses that resulted in a hit from a front door request only (does not include rejects or recycles), Counts on a per core basis. EventSel=24H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_REQUEST.MISS Counts the number of L2 Cache accesses that resulted in a miss from a front door request only (does not include rejects or recycles). Counts on a per core basis. EventSel=24H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
L2_REQUEST.REJECTS Counts the number of L2 Cache accesses that miss the L2 and get BBL reject – short and long rejects (includes those counted in L2_reject_XQ.any). Counts on a per core basis. EventSel=24H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
LD_BLOCKS.4K_ALIAS Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. EventSel=03H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
LD_BLOCKS.ALL Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks). EventSel=03H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
LD_BLOCKS.DATA_UNKNOWN Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. EventSel=03H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
LD_BLOCKS.DTLB_MISS Counts the number of retired loads that are blocked due to a first level TLB miss. EventSel=03H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
LD_BLOCKS.STORE_FORWARD Counts the number of retired loads that are blocked because its address partially overlapped with an older store. EventSel=03H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MACHINE_CLEARS.ANY Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist. EventSel=C3H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.DISAMBIGUATION Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. EventSel=C3H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.FP_ASSIST Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. EventSel=C3H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.MEMORY_ORDERING Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. EventSel=C3H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.PAGE_FAULT Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. EventSel=C3H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MACHINE_CLEARS.SMC Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. EventSel=C3H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.IFETCH Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). EventSel=34H UMask=38H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.IFETCH_DRAM_HIT Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM). EventSel=34H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.IFETCH_L2_HIT Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache. EventSel=34H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.IFETCH_LLC_HIT Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M. EventSel=34H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.LOAD Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM). EventSel=34H UMask=07H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.LOAD_DRAM_HIT Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM). EventSel=34H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.LOAD_L2_HIT Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache. EventSel=34H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.LOAD_LLC_HIT Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M. EventSel=34H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_BOUND_STALLS.STORE_BUFFER_FULL Counts the number of cycles the core is stalled due to a store buffer being full. EventSel=34H UMask=40H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
MEM_LOAD_UOPS_RETIRED.DRAM_HIT Counts the number of load uops retired that hit in DRAM.
Errata: https://hsdes.intel.com/appstore/article/#/1707187406 https://hsdes.intel.com/appstore/article/#/1707187405
EventSel=D1H UMask=80H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.HITM Counts the number of load uops retired that hit in the L3 cache, in which a snoop was required and modified data was forwarded from another core or module.
Errata: https://hsdes.intel.com/appstore/article/#/1707187406
EventSel=D1H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.L1_HIT Counts the number of load uops retired that hit in the L1 data cache. EventSel=D1H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.L1_MISS Counts the number of load uops retired that miss in the L1 data cache. EventSel=D1H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.L2_HIT Counts the number of load uops retired that hit in the L2 cache. EventSel=D1H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.L2_MISS Counts the number of load uops retired that miss in the L2 cache. EventSel=D1H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_LOAD_UOPS_RETIRED.L3_HIT Counts the number of load uops retired that hit in the L3 cache. EventSel=D1H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.ALL Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST) EventSel=D0H UMask=83H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.ALL_LOADS Counts the total number of load uops retired. EventSel=D0H UMask=81H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.ALL_STORES Counts the total number of store uops retired. EventSel=D0H UMask=82H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.DTLB_MISS Counts the number of memory uops retired that missed in the second level TLB. EventSel=D0H UMask=13H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.DTLB_MISS_LOADS Counts the number of load uops retired that miss in the second Level TLB. EventSel=D0H UMask=11H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.DTLB_MISS_STORES Counts the number of store uops retired that miss in the second level TLB. EventSel=D0H UMask=12H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.LOCK_LOADS Counts the number of load uops retired that performed one or more locks. EventSel=D0H UMask=21H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.SPLIT Counts the number of memory uops retired that were splits. EventSel=D0H UMask=43H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.SPLIT_LOADS Counts the number of retired split load uops. EventSel=D0H UMask=41H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MEM_UOPS_RETIRED.SPLIT_STORES Counts the number of retired split store uops. EventSel=D0H UMask=42H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MISALIGN_MEM_REF.LOAD_PAGE_SPLIT Counts the number of misaligned load uops that are 4K page splits. EventSel=13H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
MISALIGN_MEM_REF.STORE_PAGE_SPLIT Counts the number of misaligned store uops that are 4K page splits. EventSel=13H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
TOPDOWN_BAD_SPECULATION.ALL Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. EventSel=73H UMask=06H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BAD_SPECULATION.FASTNUKE Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears. EventSel=73H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. EventSel=73H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BAD_SPECULATION.MISPREDICT Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts. EventSel=73H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.ALL Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls. EventSel=74H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions. EventSel=74H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops. EventSel=74H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops. EventSel=74H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.REGISTER Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls). EventSel=74H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.REORDER_BUFFER Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls). EventSel=74H UMask=40H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_BE_BOUND.SERIALIZATION Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS). EventSel=74H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.ALL Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls. EventSel=71H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.BRANCH_DETECT Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. EventSel=71H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.BRANCH_RESTEER Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch. EventSel=71H UMask=40H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.CISC Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS). EventSel=71H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.DECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.
Errata: https://hsdes.intel.com/appstore/article/#/1707048210
EventSel=71H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.ICACHE Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.
Errata: https://hsdes.intel.com/appstore/article/#/1707048210
EventSel=71H UMask=20H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.ITLB Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.
Errata: https://hsdes.intel.com/appstore/article/#/1707048210
EventSel=71H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.OTHER Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized. EventSel=71H UMask=80H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_FE_BOUND.PREDECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes. EventSel=71H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
TOPDOWN_RETIRING.ALL Counts the total number of consumed retirement slots. EventSel=C2H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
UOPS_ISSUED.ANY Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. EventSel=0EH UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative
CoreOnly
UOPS_RETIRED.ALL Counts the total number of uops retired. EventSel=C2H UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
UOPS_RETIRED.FPDIV Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). EventSel=C2H UMask=08H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
UOPS_RETIRED.IDIV Counts the number of integer divide uops retired. EventSel=C2H UMask=10H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
UOPS_RETIRED.MS Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. EventSel=C2H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
UOPS_RETIRED.X87 Counts the number of x87 uops retired, includes those in MS flows. EventSel=C2H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
AtRetirement
CoreOnly
BUS_LOCK.ALL This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS EventSel=63H UMask=00H EdgeDetect=1
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
BUS_LOCK.CYCLES_OTHER_BLOCK This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES EventSel=63H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
BUS_LOCK.CYCLES_SELF_BLOCK This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES EventSel=63H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
C0_STALLS.LOAD_DRAM_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT EventSel=34H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
C0_STALLS.LOAD_L2_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT EventSel=34H UMask=01H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
C0_STALLS.LOAD_LLC_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT EventSel=34H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
CYCLES_DIV_BUSY.ANY This event is deprecated. EventSel=CDH UMask=00H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
TOPDOWN_BAD_SPECULATION.MONUKE This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE EventSel=73H UMask=02H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
TOPDOWN_BE_BOUND.STORE_BUFFER This event is deprecated. EventSel=74H UMask=04H
Counter=0,1,2,3 CounterHTOff=NA
PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
Speculative, Deprecated
CoreOnly
UNCORE Uncore
UNC_M_HCLOCKTICKS Half clockticks for IMC MSR_UNC_PERF_FIXED_CTR
Fixed
Uncore
UNC_U_CLOCKTICKS Clockticks in the UBOX using a dedicated 48-bit Fixed Counter MSR_UNC_PERF_FIXED_CTR
Fixed
Uncore
UNC_CHA_CLOCKTICKS Clockticks of the uncore caching and home agent (CHA) EventSel=00H UMask=00H
Counter=0,1,2,3
Uncore
UNC_CHA_CMS_CLOCKTICKS CMS Clockticks EventSel=C0H UMask=00H
Uncore
UNC_CHA_IMC_READS_COUNT.NORMAL Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA. EventSel=59H UMask=01H
Uncore
UNC_CHA_IMC_WRITES_COUNT.FULL Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels. EventSel=5BH UMask=01H
Uncore
UNC_CHA_LLC_LOOKUP.DATA_READ Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions EventSel=34H UMask=FFH UMaskExt=1BC1H
Counter=0,1,2,3
Uncore
UNC_CHA_LLC_VICTIMS.ALL Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. EventSel=37H UMask=0FH UMaskExt=00H
Counter=0,1,2,3
Uncore
UNC_CHA_REQUESTS.READS Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) . EventSel=50H UMask=03H
Counter=0,1,2,3
Uncore
UNC_CHA_REQUESTS.WRITES Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. EventSel=50H UMask=0CH
Counter=0,1,2,3
Uncore
UNC_CHA_SF_EVICTION.E_STATE Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. EventSel=3DH UMask=02H
Uncore
UNC_CHA_SF_EVICTION.M_STATE Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. EventSel=3DH UMask=01H
Uncore
UNC_CHA_SF_EVICTION.S_STATE Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. EventSel=3DH UMask=04H
Uncore
UNC_CHA_TOR_INSERTS.IA TOR Inserts : All requests from iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C001FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_CLFLUSH TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C8C7FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_CRD TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C80FFFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_DRD_OPT TOR Inserts : DRd_Opts issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C827FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF TOR Inserts : DRd_Opt_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C8A7FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C001FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_CRD TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C80FFDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C88FFDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C827FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C8A7FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_RFO TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C807FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C887FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C001FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_CRD TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C80FFEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C88FFEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C827FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C8A7FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR TOR Inserts; Data read from local IA that misses in the snoop filter EventSel=35H UMask=01H UMaskExt=C867FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR TOR Inserts; Data read from local IA that misses in the snoop filter EventSel=35H UMask=01H UMaskExt=C86FFEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_RFO TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C807FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C887FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF TOR Inserts : UCRdFs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C877DEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_WCIL TOR Inserts : WCiLs issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C86FFEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_WCILF TOR Inserts : WCiLF issued by iA Cores that Missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C867FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_MISS_WIL TOR Inserts : WiLs issued by iA Cores that Missed LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C87FDEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_RFO TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C807FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IA_RFO_PREF TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=01H UMaskExt=C887FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO TOR Inserts : All requests from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C001FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_HIT TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C001FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_HIT_ITOM TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CC43FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CD43FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C8F3FDH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_ITOM TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CC43FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CD43FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_MISS TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C001FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_MISS_ITOM TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CC43FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=CD43FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C8F3FEH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_INSERTS.IO_PCIRDCUR TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=35H UMask=04H UMaskExt=C8F3FFH
Counter=0,1,2,3
Uncore
UNC_CHA_TOR_OCCUPANCY.IA TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C001FFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_CRD TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C80FFFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT TOR Occupancy : DRd_Opts issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C827FFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF TOR Occupancy : DRd_Opt_Prefs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C8A7FFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_HIT TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C001FDH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT TOR Occupancy : DRd_Opts issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C827FDH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF TOR Occupancy : DRd_Opt_Prefs issued by iA Cores that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C8A7FDH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_MISS TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C001FEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C80FFEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT TOR Occupancy : DRd_Opt issued by iA Cores that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C827FEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C807FEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IA_RFO TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=01H UMaskExt=C807FFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IO TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=04H UMaskExt=C001FFH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IO_HIT TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=04H UMaskExt=C001FDH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IO_MISS TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=04H UMaskExt=C001FEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=04H UMaskExt=C8F3FEH
Counter=0
Uncore
UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. EventSel=36H UMask=04H UMaskExt=C8F3FFH
Counter=0
Uncore
UNC_IIO_CLOCKTICKS Clockticks of the integrated IO (IIO) traffic controller EventSel=01H UMask=00H
Counter=0,1,2,3
Uncore
UNC_IIO_CLOCKTICKS_FREERUN Free running counter that increments for integrated IO (IIO) traffic controller clockticks EventSel=00H UMask=00H UMaskExt=00H FCMask=00H PortMask=00H
Counter=0
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS PCIe Completion Buffer Inserts of completions with data : Part 0-7 EventSel=C2H UMask=03H FCMask=04H PortMask=FFH
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=C2H UMask=03H FCMask=04H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 EventSel=C2H UMask=03H FCMask=04H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 EventSel=C2H UMask=03H FCMask=04H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 EventSel=C2H UMask=03H FCMask=04H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4 PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 EventSel=C2H UMask=03H FCMask=04H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5 PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 EventSel=C2H UMask=03H FCMask=04H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 EventSel=C2H UMask=03H FCMask=04H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7 PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 EventSel=C2H UMask=03H FCMask=04H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS PCIe Completion Buffer Occupancy : Part 0-7 EventSel=D5H UMask=FFH FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0 PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=D5H UMask=01H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1 PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 EventSel=D5H UMask=02H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2 PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 EventSel=D5H UMask=04H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3 PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 EventSel=D5H UMask=08H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4 PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 EventSel=D5H UMask=10H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5 PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 EventSel=D5H UMask=20H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6 PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 EventSel=D5H UMask=40H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7 PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 EventSel=D5H UMask=80H FCMask=04H PortMask=00H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=C0H UMask=04H FCMask=07H PortMask=01H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 EventSel=C0H UMask=04H FCMask=07H PortMask=02H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=C0H UMask=04H FCMask=07H PortMask=04H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 EventSel=C0H UMask=04H FCMask=07H PortMask=08H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=C0H UMask=04H FCMask=07H PortMask=10H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 EventSel=C0H UMask=04H FCMask=07H PortMask=20H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=C0H UMask=04H FCMask=07H PortMask=40H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7 Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 EventSel=C0H UMask=04H FCMask=07H PortMask=80H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=C0H UMask=01H FCMask=07H PortMask=01H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 EventSel=C0H UMask=01H FCMask=07H PortMask=02H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=C0H UMask=01H FCMask=07H PortMask=04H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 EventSel=C0H UMask=01H FCMask=07H PortMask=08H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=C0H UMask=01H FCMask=07H PortMask=10H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 EventSel=C0H UMask=01H FCMask=07H PortMask=20H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=C0H UMask=01H FCMask=07H PortMask=40H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 EventSel=C0H UMask=01H FCMask=07H PortMask=80H
Counter=2,3
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=83H UMask=80H FCMask=07H PortMask=01H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=83H UMask=80H FCMask=07H PortMask=02H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=83H UMask=80H FCMask=07H PortMask=04H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=83H UMask=80H FCMask=07H PortMask=08H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=83H UMask=80H FCMask=07H PortMask=10H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=83H UMask=80H FCMask=07H PortMask=20H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=83H UMask=80H FCMask=07H PortMask=40H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7 Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=83H UMask=80H FCMask=07H PortMask=80H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=83H UMask=04H FCMask=07H PortMask=01H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=83H UMask=04H FCMask=07H PortMask=02H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=83H UMask=04H FCMask=07H PortMask=04H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=83H UMask=04H FCMask=07H PortMask=08H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=83H UMask=04H FCMask=07H PortMask=10H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=83H UMask=04H FCMask=07H PortMask=20H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=83H UMask=04H FCMask=07H PortMask=40H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=83H UMask=04H FCMask=07H PortMask=80H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=83H UMask=01H FCMask=07H PortMask=01H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=83H UMask=01H FCMask=07H PortMask=02H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=83H UMask=01H FCMask=07H PortMask=04H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=83H UMask=01H FCMask=07H PortMask=08H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=83H UMask=01H FCMask=07H PortMask=10H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=83H UMask=01H FCMask=07H PortMask=20H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=83H UMask=01H FCMask=07H PortMask=40H
Counter=0,1
Uncore
UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=83H UMask=01H FCMask=07H PortMask=80H
Counter=0,1
Uncore
UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. EventSel=85H UMask=01H FCMask=07H PortMask=FFH
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=C1H UMask=04H FCMask=07H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 EventSel=C1H UMask=04H FCMask=07H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=C1H UMask=04H FCMask=07H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 EventSel=C1H UMask=04H FCMask=07H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=C1H UMask=04H FCMask=07H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 EventSel=C1H UMask=04H FCMask=07H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=C1H UMask=04H FCMask=07H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 EventSel=C1H UMask=04H FCMask=07H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=C1H UMask=01H FCMask=07H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 EventSel=C1H UMask=01H FCMask=07H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=C1H UMask=01H FCMask=07H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 EventSel=C1H UMask=01H FCMask=07H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=C1H UMask=01H FCMask=07H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 EventSel=C1H UMask=01H FCMask=07H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=C1H UMask=01H FCMask=07H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 EventSel=C1H UMask=01H FCMask=07H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=84H UMask=80H FCMask=07H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=84H UMask=80H FCMask=07H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=84H UMask=80H FCMask=07H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=84H UMask=80H FCMask=07H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=84H UMask=80H FCMask=07H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=84H UMask=80H FCMask=07H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=84H UMask=80H FCMask=07H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7 Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=84H UMask=80H FCMask=07H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=84H UMask=04H FCMask=07H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=84H UMask=04H FCMask=07H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=84H UMask=04H FCMask=07H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=84H UMask=04H FCMask=07H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=84H UMask=04H FCMask=07H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=84H UMask=04H FCMask=07H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=84H UMask=04H FCMask=07H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=84H UMask=04H FCMask=07H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 EventSel=84H UMask=01H FCMask=07H PortMask=01H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 EventSel=84H UMask=01H FCMask=07H PortMask=02H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 EventSel=84H UMask=01H FCMask=07H PortMask=04H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 EventSel=84H UMask=01H FCMask=07H PortMask=08H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 EventSel=84H UMask=01H FCMask=07H PortMask=10H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 EventSel=84H UMask=01H FCMask=07H PortMask=20H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 EventSel=84H UMask=01H FCMask=07H PortMask=40H
Counter=0,1,2,3
Uncore
UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 EventSel=84H UMask=01H FCMask=07H PortMask=80H
Counter=0,1,2,3
Uncore
UNC_M_ACT_COUNT.ALL DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. EventSel=01H UMask=0BH
Counter=0,1,2,3
Uncore
UNC_M_CAS_COUNT.ALL Counts the total number of DRAM CAS commands issued on this channel. EventSel=04H UMask=3FH
Counter=0,1,2,3
Uncore
UNC_M_CAS_COUNT.RD Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills. EventSel=04H UMask=0FH
Counter=0,1,2,3
Uncore
UNC_M_CAS_COUNT.WR Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel. EventSel=04H UMask=30H
Counter=0,1,2,3
Uncore
UNC_M_CLOCKTICKS Clockticks of the integrated memory controller (IMC) EventSel=00H UMask=00H
Counter=0,1,2,3
Uncore
UNC_M_DRAM_REFRESH.HIGH Number of DRAM Refreshes Issued : Counts the number of refreshes issued. EventSel=45H UMask=04H
Counter=0,1,2,3
Uncore
UNC_M_DRAM_REFRESH.OPPORTUNISTIC Number of DRAM Refreshes Issued : Counts the number of refreshes issued. EventSel=45H UMask=01H
Counter=0,1,2,3
Uncore
UNC_M_DRAM_REFRESH.PANIC Number of DRAM Refreshes Issued : Counts the number of refreshes issued. EventSel=45H UMask=02H
Counter=0,1,2,3
Uncore
UNC_M_PRE_COUNT.ALL DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. EventSel=02H UMask=1CH
Counter=0,1,2,3
Uncore
UNC_M_PRE_COUNT.PGT DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Prechages from Page Table EventSel=02H UMask=10H
Counter=0,1,2,3
Uncore
UNC_M_PRE_COUNT.RD DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler EventSel=02H UMask=04H
Counter=0,1,2,3
Uncore
UNC_M_PRE_COUNT.WR DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler EventSel=02H UMask=08H
Counter=0,1,2,3
Uncore
UNC_M_RPQ_INSERTS.PCH0 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. EventSel=10H UMask=01H
Counter=0,1,2,3
Uncore
UNC_M_RPQ_INSERTS.PCH1 Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. EventSel=10H UMask=02H
Counter=0,1,2,3
Uncore
UNC_M_RPQ_OCCUPANCY_PCH0 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. EventSel=80H UMask=00H
Counter=0,1,2,3
Uncore
UNC_M_RPQ_OCCUPANCY_PCH1 Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. EventSel=81H UMask=00H
Counter=0,1,2,3
Uncore
UNC_M_WPQ_INSERTS.PCH0 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. EventSel=20H UMask=01H
Counter=0,1,2,3
Uncore
UNC_M_WPQ_INSERTS.PCH1 Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. EventSel=20H UMask=02H
Counter=0,1,2,3
Uncore
UNC_M_WPQ_OCCUPANCY_PCH0 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. EventSel=82H UMask=00H
Counter=0,1,2,3
Uncore
UNC_M_WPQ_OCCUPANCY_PCH1 Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happenning in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. EventSel=83H UMask=00H
Counter=0,1,2,3
Uncore
UNC_I_CACHE_TOTAL_OCCUPANCY.MEM Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy. EventSel=0FH UMask=04H
Counter=0,1
Uncore
UNC_I_CLOCKTICKS Clockticks of the IO coherency tracker (IRP) EventSel=01H UMask=00H
Counter=0,1
Uncore
UNC_I_COHERENT_OPS.PCITOM PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache. EventSel=10H UMask=10H
Counter=0,1
Uncore
UNC_I_COHERENT_OPS.WBMTOI Coherent Ops : WbMtoI : Counts the number of coherency related operations servied by the IRP EventSel=10H UMask=40H
Counter=0,1
Uncore
UNC_I_FAF_FULL FAF RF full EventSel=17H UMask=00H
Counter=0,1
Uncore
UNC_I_FAF_INSERTS Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP. EventSel=18H UMask=00H
Counter=0,1
Uncore
UNC_I_FAF_OCCUPANCY Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP. EventSel=19H UMask=00H
Counter=0,1
Uncore
UNC_I_FAF_TRANSACTIONS FAF allocation -- sent to ADQ EventSel=16H UMask=00H
Counter=0,1
Uncore
UNC_I_IRP_ALL.INBOUND_INSERTS : All Inserts Inbound (p2p + faf + cset) EventSel=20H UMask=01H
Counter=0,1
Uncore
UNC_I_MISC1.LOST_FWD Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed EventSel=1FH UMask=10H
Counter=0,1
Uncore
UNC_I_SNOOP_RESP.ALL_HIT_M Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache EventSel=12H UMask=78H
Counter=0,1
Uncore
UNC_I_TRANSACTIONS.WR_PREF Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. EventSel=11H UMask=08H
Counter=0,1
Uncore
UNC_M2M_CLOCKTICKS Clockticks of the mesh to memory (M2M) EventSel=00H UMask=00H
Uncore
UNC_M2M_CMS_CLOCKTICKS CMS Clockticks EventSel=C0H UMask=00H
Uncore
UNC_M2P_CLOCKTICKS Clockticks of the mesh to PCI (M2P) EventSel=01H UMask=00H
Counter=0,1,2,3
Uncore
UNC_M2P_CMS_CLOCKTICKS CMS Clockticks EventSel=C0H UMask=00H
Uncore
UNC_P_CLOCKTICKS Clockticks of the power control unit (PCU) EventSel=00H UMask=00H
Counter=0,1,2,3
Uncore
OFFCORE Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H Offcore
OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0002H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0002H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0002H Offcore
OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H Offcore
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0004H Offcore
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0004H Offcore
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H Offcore
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0004H Offcore
OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0010H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0010H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0010H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0010H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0010H Offcore
OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0020H Offcore
OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0020H Offcore
OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0020H Offcore
OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0020H Offcore
OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0020H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0040H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0040H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0040H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0040H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0040H Offcore
OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0400H Offcore
OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001003C0000H Offcore
OCR.UC_RD.L3_HIT.SNOOP_MISS OCR.UC_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002003C0000H Offcore
OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1004003C0000H Offcore
OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1008003C0000H Offcore
OCR.UC_RD.L3_HIT.SNOOP_HITM OCR.UC_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1010003C0000H Offcore
OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0044H Offcore
OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0044H Offcore
OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0044H Offcore
OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0044H Offcore
OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0044H Offcore
OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=400000010000H Offcore
OCR.PARTIAL_STREAMING_WR.L3_MISS OCR.PARTIAL_STREAMING_WR.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H Offcore
OCR.FULL_STREAMING_WR.ANY_RESPONSE OCR.FULL_STREAMING_WR.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800000010000H Offcore
OCR.FULL_STREAMING_WR.L3_MISS OCR.FULL_STREAMING_WR.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H Offcore
OCR.L1WB_M.ANY_RESPONSE OCR.L1WB_M.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000010000H Offcore
OCR.L1WB_M.L3_MISS OCR.L1WB_M.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H Offcore
OCR.L2WB_M.ANY_RESPONSE OCR.L2WB_M.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000000010000H Offcore
OCR.L2WB_M.L3_MISS OCR.L2WB_M.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H Offcore
OCR.ALL_CODE_RD.ANY_RESPONSE OCR.ALL_CODE_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10044H Offcore
OCR.ALL_CODE_RD.OUTSTANDING OCR.ALL_CODE_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000044H Offcore
OCR.ALL_CODE_RD.DRAM OCR.ALL_CODE_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H Offcore
OCR.ALL_CODE_RD.L3_MISS OCR.ALL_CODE_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H Offcore
OCR.DEMAND_DATA_RD.ANY_RESPONSE OCR.DEMAND_DATA_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H Offcore
OCR.DEMAND_DATA_RD.OUTSTANDING OCR.DEMAND_DATA_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H Offcore
OCR.DEMAND_DATA_RD.DRAM OCR.DEMAND_DATA_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
OCR.DEMAND_DATA_RD.L3_MISS OCR.DEMAND_DATA_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
OCR.DEMAND_RFO.ANY_RESPONSE OCR.DEMAND_RFO.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H Offcore
OCR.DEMAND_RFO.OUTSTANDING OCR.DEMAND_RFO.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000002H Offcore
OCR.DEMAND_RFO.DRAM OCR.DEMAND_RFO.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H Offcore
OCR.DEMAND_RFO.L3_MISS OCR.DEMAND_RFO.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H Offcore
OCR.DEMAND_CODE_RD.ANY_RESPONSE OCR.DEMAND_CODE_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H Offcore
OCR.DEMAND_CODE_RD.DRAM OCR.DEMAND_CODE_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H Offcore
OCR.DEMAND_CODE_RD.L3_MISS OCR.DEMAND_CODE_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H Offcore
OCR.COREWB_M.ANY_RESPONSE OCR.COREWB_M.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3000000010000H Offcore
OCR.COREWB_M.OUTSTANDING OCR.COREWB_M.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8003000000000000H Offcore
OCR.COREWB_M.L3_MISS OCR.COREWB_M.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H Offcore
OCR.HWPF_L2_DATA_RD.ANY_RESPONSE OCR.HWPF_L2_DATA_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H Offcore
OCR.HWPF_L2_DATA_RD.DRAM OCR.HWPF_L2_DATA_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H Offcore
OCR.HWPF_L2_DATA_RD.L3_MISS OCR.HWPF_L2_DATA_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H Offcore
OCR.HWPF_L2_RFO.ANY_RESPONSE OCR.HWPF_L2_RFO.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H Offcore
OCR.HWPF_L2_RFO.OUTSTANDING OCR.HWPF_L2_RFO.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000020H Offcore
OCR.HWPF_L2_RFO.DRAM OCR.HWPF_L2_RFO.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H Offcore
OCR.HWPF_L2_RFO.L3_MISS OCR.HWPF_L2_RFO.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H Offcore
OCR.HWPF_L2_CODE_RD.ANY_RESPONSE OCR.HWPF_L2_CODE_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10040H Offcore
OCR.HWPF_L2_CODE_RD.OUTSTANDING OCR.HWPF_L2_CODE_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000040H Offcore
OCR.HWPF_L2_CODE_RD.DRAM OCR.HWPF_L2_CODE_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H Offcore
OCR.HWPF_L2_CODE_RD.L3_MISS OCR.HWPF_L2_CODE_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H Offcore
OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H Offcore
OCR.STREAMING_WR.ANY_RESPONSE OCR.STREAMING_WR.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H Offcore
OCR.STREAMING_WR.L3_MISS OCR.STREAMING_WR.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H Offcore
OCR.OTHER.ANY_RESPONSE OCR.OTHER.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H Offcore
OCR.OTHER.L3_MISS OCR.OTHER.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H Offcore
OCR.UC_RD.ANY_RESPONSE OCR.UC_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100000010000H Offcore
OCR.UC_RD.OUTSTANDING OCR.UC_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000100000000000H Offcore
OCR.UC_RD.DRAM OCR.UC_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H Offcore
OCR.UC_RD.L3_MISS OCR.UC_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H Offcore
OCR.UC_WR.ANY_RESPONSE OCR.UC_WR.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000010000H Offcore
OCR.UC_WR.L3_MISS OCR.UC_WR.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.DRAM OCR.DEMAND_DATA_AND_L1PF_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
OCR.DEMAND_DATA_RD.LOCAL_DRAM OCR.DEMAND_DATA_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
OCR.DEMAND_RFO.LOCAL_DRAM OCR.DEMAND_RFO.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H Offcore
OCR.DEMAND_CODE_RD.LOCAL_DRAM OCR.DEMAND_CODE_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H Offcore
OCR.HWPF_L2_DATA_RD.LOCAL_DRAM OCR.HWPF_L2_DATA_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H Offcore
OCR.HWPF_L2_RFO.LOCAL_DRAM OCR.HWPF_L2_RFO.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H Offcore
OCR.HWPF_L2_CODE_RD.LOCAL_DRAM OCR.HWPF_L2_CODE_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H Offcore
OCR.UC_RD.LOCAL_DRAM OCR.UC_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H Offcore
OCR.ALL_CODE_RD.LOCAL_DRAM OCR.ALL_CODE_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
OCR.DEMAND_DATA_RD.L3_MISS_LOCAL OCR.DEMAND_DATA_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
OCR.DEMAND_RFO.L3_MISS_LOCAL OCR.DEMAND_RFO.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H Offcore
OCR.DEMAND_CODE_RD.L3_MISS_LOCAL OCR.DEMAND_CODE_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H Offcore
OCR.COREWB_M.L3_MISS_LOCAL OCR.COREWB_M.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H Offcore
OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H Offcore
OCR.HWPF_L2_RFO.L3_MISS_LOCAL OCR.HWPF_L2_RFO.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H Offcore
OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H Offcore
OCR.STREAMING_WR.L3_MISS_LOCAL OCR.STREAMING_WR.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H Offcore
OCR.OTHER.L3_MISS_LOCAL OCR.OTHER.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H Offcore
OCR.UC_RD.L3_MISS_LOCAL OCR.UC_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H Offcore
OCR.UC_WR.L3_MISS_LOCAL OCR.UC_WR.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H Offcore
OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H Offcore
OCR.FULL_STREAMING_WR.L3_MISS_LOCAL OCR.FULL_STREAMING_WR.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H Offcore
OCR.L1WB_M.L3_MISS_LOCAL OCR.L1WB_M.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H Offcore
OCR.L2WB_M.L3_MISS_LOCAL OCR.L2WB_M.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H Offcore
OCR.ALL_CODE_RD.L3_MISS_LOCAL OCR.ALL_CODE_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
OCR.PREFETCHES.ANY_RESPONSE OCR.PREFETCHES.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10470H Offcore
OCR.PREFETCHES.L3_MISS OCR.PREFETCHES.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000470H Offcore
OCR.READS_TO_CORE.ANY_RESPONSE OCR.READS_TO_CORE.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10477H Offcore
OCR.READS_TO_CORE.OUTSTANDING OCR.READS_TO_CORE.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000477H Offcore
OCR.READS_TO_CORE.DRAM OCR.READS_TO_CORE.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H Offcore
OCR.READS_TO_CORE.L3_MISS OCR.READS_TO_CORE.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H Offcore
OCR.READS_TO_CORE.LOCAL_DRAM OCR.READS_TO_CORE.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H Offcore
OCR.READS_TO_CORE.L3_MISS_LOCAL OCR.READS_TO_CORE.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H Offcore
OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0477H Offcore
OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0477H Offcore
OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0477H Offcore
OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0477H Offcore
OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0477H Offcore
OCR.DEMAND_DATA_RD.L3_HIT OCR.DEMAND_DATA_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H Offcore
OCR.DEMAND_RFO.L3_HIT OCR.DEMAND_RFO.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0002H Offcore
OCR.DEMAND_CODE_RD.L3_HIT OCR.DEMAND_CODE_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0004H Offcore
OCR.COREWB_M.L3_HIT OCR.COREWB_M.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3001F803C0000H Offcore
OCR.HWPF_L2_DATA_RD.L3_HIT OCR.HWPF_L2_DATA_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0010H Offcore
OCR.HWPF_L2_RFO.L3_HIT OCR.HWPF_L2_RFO.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0020H Offcore
OCR.HWPF_L2_CODE_RD.L3_HIT OCR.HWPF_L2_CODE_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0040H Offcore
OCR.STREAMING_WR.L3_HIT OCR.STREAMING_WR.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0800H Offcore
OCR.UC_RD.L3_HIT OCR.UC_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101F803C0000H Offcore
OCR.UC_WR.L3_HIT OCR.UC_WR.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=201F803C0000H Offcore
OCR.PARTIAL_STREAMING_WR.L3_HIT OCR.PARTIAL_STREAMING_WR.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=401F803C0000H Offcore
OCR.FULL_STREAMING_WR.L3_HIT OCR.FULL_STREAMING_WR.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=801F803C0000H Offcore
OCR.L1WB_M.L3_HIT OCR.L1WB_M.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001F803C0000H Offcore
OCR.L2WB_M.L3_HIT OCR.L2WB_M.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2001F803C0000H Offcore
OCR.ALL_CODE_RD.L3_HIT OCR.ALL_CODE_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0044H Offcore
OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H Offcore
OCR.READS_TO_CORE.L3_HIT OCR.READS_TO_CORE.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0477H Offcore