This site provides a reference for performance monitoring events supported by Intel Performance Monitoring Units (PMUs).
The PMU is hardware built inside a processor to measure its performance parameters such as instruction cycles, cache hits,
cache misses, branch misses,and many others.Performance monitoring events provide facilities to characterize the interaction
between programmed sequences of instructions and microarchitectural sub-systems.
Performance monitoring events are actively used by performance profiling tools, e.g., the Intel® VTune™ Profiler,
that provide event-based sampling microarchitecture analysis types to understand how effectively code uses hardware
resources and recommend relevant optimization techniques.
The events listed are the performance monitoring events that can be monitored with the Intel® 64 or IA-32 processors.
The ability to monitor performance events and the events that can be monitored in these processors are mostly model-specific,
except for architectural performance events which are listed separately.
These performance monitoring events are intended to be used as guides for performance tuning. The counter values
reported by the performance monitoring events are approximate and believed to be useful as relative guides for tuning
software. Known discrepancies are documented where applicable.
All performance event encodings not documented for the given processor are considered reserved, and their use will result in
undefined counter updates with associated overflow actions.