Intel® Core™ processors based on Meteor Lake performance hybrid architecture
This section provides reference for hardware events that can be monitored for the CPU(s):
  • Intel® Microarchitecture Code Named Redwood Cove (Performance Core)
  • Intel® Microarchitecture Code Named Crestmont (Efficient Core)
    • Event Name Description Additional Info EventType
    P-core PCoreOnly
    INST_RETIRED.ANY Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. CORE: PCore IA32_FIXED_CTR0
    PEBS:[PreciseEventingIP, PDISTCounter=32]
    Architectural, Fixed, AtRetirement    		 PCoreOnly
    CPU_CLK_UNHALTED.THREAD Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. CORE: PCore IA32_FIXED_CTR1
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.REF_TSC Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. CORE: PCore IA32_FIXED_CTR2
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 PCoreOnly
    TOPDOWN.SLOTS Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). CORE: PCore IA32_FIXED_CTR3
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 PCoreOnly
    BR_INST_RETIRED.ALL_BRANCHES Counts all branch instructions retired. CORE: PCore EventSel=C4H UMask=00H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. CORE: PCore EventSel=C5H UMask=00H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 PCoreOnly
    CPU_CLK_UNHALTED.REF_TSC_P Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. CORE: PCore EventSel=3CH UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.THREAD_P This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. CORE: PCore EventSel=3CH UMask=00H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    IDQ_BUBBLES.CORE This event counts a subset of the Topdown Slots event that when no operation was delivered to the back-end pipeline due to instruction fetch limitations when the back-end could have accepted more operations. Common examples include instruction cache misses or x86 instruction decode limitations. The count may be distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Frontend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method. CORE: PCore EventSel=9CH UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    INST_RETIRED.ANY_P Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. CORE: PCore EventSel=C0H UMask=00H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 PCoreOnly
    LONGEST_LAT_CACHE.MISS Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. CORE: PCore EventSel=2EH UMask=41H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    LONGEST_LAT_CACHE.REFERENCE Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. CORE: PCore EventSel=2EH UMask=4FH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    TOPDOWN.BACKEND_BOUND_SLOTS This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units’ limitations, or other conditions. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method. CORE: PCore EventSel=A4H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    TOPDOWN.SLOTS_P Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. CORE: PCore EventSel=A4H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 PCoreOnly
    UOPS_RETIRED.SLOTS This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance – for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method. CORE: PCore EventSel=C2H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 PCoreOnly
    ARITH.DIV_ACTIVE Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. CORE: PCore EventSel=B0H UMask=09H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ARITH.FPDIV_ACTIVE This event counts the cycles the floating point divider is busy. CORE: PCore EventSel=B0H UMask=01H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ARITH.IDIV_ACTIVE This event counts the cycles the integer divider is busy. CORE: PCore EventSel=B0H UMask=08H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ASSISTS.ANY Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists. CORE: PCore EventSel=C1H UMask=1BH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ASSISTS.FP Counts all microcode Floating Point assists. CORE: PCore EventSel=C1H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ASSISTS.PAGE_FAULT ASSISTS.PAGE_FAULT CORE: PCore EventSel=C1H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    ASSISTS.SSE_AVX_MIX ASSISTS.SSE_AVX_MIX CORE: PCore EventSel=C1H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    BACLEARS.ANY Number of times the front-end is resteered when it finds a branch instruction in a fetch line. This is called Unknown Branch which occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. CORE: PCore EventSel=60H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    BR_INST_RETIRED.COND Counts conditional branch instructions retired. CORE: PCore EventSel=C4H UMask=11H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.COND_NTAKEN Counts not taken branch instructions retired. CORE: PCore EventSel=C4H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.COND_TAKEN Counts taken conditional branch instructions retired. CORE: PCore EventSel=C4H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.FAR_BRANCH Counts far branch instructions retired. CORE: PCore EventSel=C4H UMask=40H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.INDIRECT Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. CORE: PCore EventSel=C4H UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.NEAR_CALL Counts both direct and indirect near call instructions retired. CORE: PCore EventSel=C4H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.NEAR_RETURN Counts return instructions retired. CORE: PCore EventSel=C4H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_INST_RETIRED.NEAR_TAKEN Counts taken branch instructions retired. CORE: PCore EventSel=C4H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES_COST All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=44H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND Counts mispredicted conditional branch instructions retired. CORE: PCore EventSel=C5H UMask=11H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND_COST Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=51H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND_NTAKEN Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. CORE: PCore EventSel=C5H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND_NTAKEN_COST Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=50H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND_TAKEN Counts taken conditional mispredicted branch instructions retired. CORE: PCore EventSel=C5H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.COND_TAKEN_COST Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=41H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.INDIRECT Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. CORE: PCore EventSel=C5H UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.INDIRECT_CALL Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect. CORE: PCore EventSel=C5H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.INDIRECT_CALL_COST Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=42H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.INDIRECT_COST Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=C0H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.NEAR_TAKEN Counts number of near branch instructions retired that were mispredicted and taken. CORE: PCore EventSel=C5H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.NEAR_TAKEN_COST Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=60H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.RET This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. CORE: PCore EventSel=C5H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    BR_MISP_RETIRED.RET_COST Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. CORE: PCore EventSel=C5H UMask=48H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    CPU_CLK_UNHALTED.C0_WAIT Counts core clocks when the thread is in the C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions) or running the PAUSE instruction. CORE: PCore EventSel=ECH UMask=70H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.C01 Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. CORE: PCore EventSel=ECH UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.C02 Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less power saving optimized state. This state can be entered via the TPAUSE or UMWAIT instructions. CORE: PCore EventSel=ECH UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.DISTRIBUTED This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. CORE: PCore EventSel=ECH UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted. CORE: PCore EventSel=3CH UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.PAUSE CPU_CLK_UNHALTED.PAUSE CORE: PCore EventSel=ECH UMask=40H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.PAUSE_INST CPU_CLK_UNHALTED.PAUSE_INST CORE: PCore EventSel=ECH UMask=40H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CPU_CLK_UNHALTED.REF_DISTRIBUTED This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. CORE: PCore EventSel=3CH UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=08H CMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=01H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.CYCLES_L3_MISS Cycles while L3 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=02H CMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an outstanding load. CORE: PCore EventSel=A3H UMask=10H CMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=0CH CMask=0CH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=05H CMask=05H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.STALLS_L3_MISS Execution stalls while L3 cache miss demand load is outstanding. CORE: PCore EventSel=A3H UMask=06H CMask=06H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls. CORE: PCore EventSel=A3H UMask=04H CMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    DECODE.LCP Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. CORE: PCore EventSel=87H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DECODE.MS_BUSY Cycles the Microcode Sequencer is busy. CORE: PCore EventSel=87H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DSB2MITE_SWITCHES.PENALTY_CYCLES Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE. CORE: PCore EventSel=61H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.STLB_HIT Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). CORE: PCore EventSel=12H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. CORE: PCore EventSel=12H UMask=10H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=12H UMask=0EH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_1G Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=12H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=12H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_4K Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=12H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_LOAD_MISSES.WALK_PENDING Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. CORE: PCore EventSel=12H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.STLB_HIT Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). CORE: PCore EventSel=13H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. CORE: PCore EventSel=13H UMask=10H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=13H UMask=0EH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_1G Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=13H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=13H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_4K Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=13H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    DTLB_STORE_MISSES.WALK_PENDING Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. CORE: PCore EventSel=13H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.1_PORTS_UTIL Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty. CORE: PCore EventSel=A6H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.2_3_PORTS_UTIL Cycles total of 2 or 3 uops are executed on all ports and Reservation Station (RS) was not empty. CORE: PCore EventSel=A6H UMask=0CH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.2_PORTS_UTIL Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. CORE: PCore EventSel=A6H UMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.3_PORTS_UTIL Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty. CORE: PCore EventSel=A6H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.4_PORTS_UTIL Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty. CORE: PCore EventSel=A6H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.BOUND_ON_LOADS Execution stalls while memory subsystem has an outstanding load. CORE: PCore EventSel=A6H UMask=21H CMask=05H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.BOUND_ON_STORES Counts cycles where the Store Buffer was full and no loads caused an execution stall. CORE: PCore EventSel=A6H UMask=40H CMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    EXE_ACTIVITY.EXE_BOUND_0_PORTS Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load. CORE: PCore EventSel=A6H UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    FP_ARITH_DISPATCHED.PORT_0 FP_ARITH_DISPATCHED.PORT_0 CORE: PCore EventSel=B3H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    FP_ARITH_DISPATCHED.PORT_1 FP_ARITH_DISPATCHED.PORT_1 CORE: PCore EventSel=B3H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    FP_ARITH_DISPATCHED.PORT_5 FP_ARITH_DISPATCHED.PORT_5 CORE: PCore EventSel=B3H UMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.4_FLOPS Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=18H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.SCALAR Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=03H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.SCALAR_DOUBLE Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.SCALAR_SINGLE Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FP_ARITH_INST_RETIRED.VECTOR Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. CORE: PCore EventSel=C7H UMask=FCH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.ANY_ANT Always Not Taken (ANT) conditional retired branches (no BTB entry and not mispredicted) CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=09H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.ANY_DSB_MISS Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.DSB_MISS Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=11H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.ITLB_MISS Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=14H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.L1I_MISS Counts retired Instructions who experienced Instruction L1 Cache true miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=12H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.L2_MISS Counts retired Instructions who experienced Instruction L2 Cache true miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=13H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_1 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600106H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_128 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=608006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_16 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=601006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_2 Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600206H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=100206H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_256 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=610006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_32 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=602006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_4 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600406H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_512 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=620006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_64 Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=604006H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.LATENCY_GE_8 Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=600806H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.MISP_ANT ANT retired branches that got just mispredicted CORE: PCore EventSel=C6H UMask=02H MSR_PEBS_FRONTEND(3F7H)=09H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.MS_FLOWS FRONTEND_RETIRED.MS_FLOWS CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.STLB_MISS Counts retired Instructions that experienced STLB (2nd level TLB) true miss. CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=15H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    FRONTEND_RETIRED.UNKNOWN_BRANCH FRONTEND_RETIRED.UNKNOWN_BRANCH CORE: PCore EventSel=C6H UMask=03H MSR_PEBS_FRONTEND(3F7H)=17H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    ICACHE_DATA.STALL_PERIODS ICACHE_DATA.STALL_PERIODS CORE: PCore EventSel=80H UMask=04H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ICACHE_DATA.STALLS Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The decode pipeline works at a 32 Byte granularity. CORE: PCore EventSel=80H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ICACHE_TAG.STALLS Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. CORE: PCore EventSel=83H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.DSB_CYCLES_ANY Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. CORE: PCore EventSel=79H UMask=08H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.DSB_CYCLES_OK Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ. CORE: PCore EventSel=79H UMask=08H CMask=06H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.DSB_UOPS Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. CORE: PCore EventSel=79H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MITE_CYCLES_ANY Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). CORE: PCore EventSel=79H UMask=04H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MITE_CYCLES_OK Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). CORE: PCore EventSel=79H UMask=04H CMask=06H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MITE_UOPS Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). CORE: PCore EventSel=79H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MS_CYCLES_ANY Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. CORE: PCore EventSel=79H UMask=20H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. CORE: PCore EventSel=79H UMask=20H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ.MS_UOPS Counts the number of uops initiated by MITE or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may 'bypass' the IDQ. CORE: PCore EventSel=79H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    IDQ_UOPS_NOT_DELIVERED.CORE Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. CORE: PCore EventSel=9CH UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. CORE: PCore EventSel=9CH UMask=01H CMask=06H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. CORE: PCore EventSel=9CH UMask=01H Invert=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INST_DECODED.DECODERS Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions. CORE: PCore EventSel=75H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    INST_RETIRED.MACRO_FUSED INST_RETIRED.MACRO_FUSED CORE: PCore EventSel=C0H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INST_RETIRED.NOP Counts all retired NOP or ENDBR32/64 or PREFETCHIT0/1 instructions CORE: PCore EventSel=C0H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INST_RETIRED.PREC_DIST A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0. CORE: PCore IA32_FIXED_CTR0
    PEBS:[PreciseEventingIP, PDISTCounter=32]
    Fixed, AtRetirement    		 PCoreOnly
    INST_RETIRED.REP_ITERATION Number of iterations of Repeat (REP) string retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, and doubleword version and string instructions can be repeated using a repetition prefix, REP, that allows their architectural execution to be repeated a number of times as specified by the RCX register. Note the number of iterations is implementation-dependent. CORE: PCore EventSel=C0H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_MISC.CLEAR_RESTEER_CYCLES Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. CORE: PCore EventSel=ADH UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INT_MISC.CLEARS_COUNT Counts the number of speculative clears due to any type of branch misprediction or machine clears CORE: PCore EventSel=ADH UMask=01H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INT_MISC.RECOVERY_CYCLES Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event. CORE: PCore EventSel=ADH UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INT_MISC.UNKNOWN_BRANCH_CYCLES Bubble cycles of BAClear (Unknown Branch). CORE: PCore EventSel=ADH UMask=40H MSR_PEBS_FRONTEND(3F7H)=07H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INT_MISC.UOP_DROPPING Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons CORE: PCore EventSel=ADH UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    INT_VEC_RETIRED.128BIT INT_VEC_RETIRED.128BIT CORE: PCore EventSel=E7H UMask=13H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.256BIT INT_VEC_RETIRED.256BIT CORE: PCore EventSel=E7H UMask=ACH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.ADD_128 Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions. CORE: PCore EventSel=E7H UMask=03H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.ADD_256 Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions. CORE: PCore EventSel=E7H UMask=0CH
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.MUL_256 INT_VEC_RETIRED.MUL_256 CORE: PCore EventSel=E7H UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.SHUFFLES INT_VEC_RETIRED.SHUFFLES CORE: PCore EventSel=E7H UMask=40H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.VNNI_128 INT_VEC_RETIRED.VNNI_128 CORE: PCore EventSel=E7H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    INT_VEC_RETIRED.VNNI_256 INT_VEC_RETIRED.VNNI_256 CORE: PCore EventSel=E7H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    ITLB_MISSES.STLB_HIT Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). CORE: PCore EventSel=11H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ITLB_MISSES.WALK_ACTIVE Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. CORE: PCore EventSel=11H UMask=10H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ITLB_MISSES.WALK_COMPLETED Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=11H UMask=0EH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ITLB_MISSES.WALK_COMPLETED_2M_4M Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=11H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ITLB_MISSES.WALK_COMPLETED_4K Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. CORE: PCore EventSel=11H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    ITLB_MISSES.WALK_PENDING Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. CORE: PCore EventSel=11H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D.HWPF_MISS L1D.HWPF_MISS CORE: PCore EventSel=51H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D.REPLACEMENT Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. CORE: PCore EventSel=51H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D_PEND_MISS.FB_FULL Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. CORE: PCore EventSel=48H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D_PEND_MISS.FB_FULL_PERIODS Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. CORE: PCore EventSel=48H UMask=02H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D_PEND_MISS.L2_STALLS Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. CORE: PCore EventSel=48H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D_PEND_MISS.PENDING Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. CORE: PCore EventSel=48H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L1D_PEND_MISS.PENDING_CYCLES Counts duration of L1D miss outstanding in cycles. CORE: PCore EventSel=48H UMask=01H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_LINES_IN.ALL Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. CORE: PCore EventSel=25H UMask=1FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_LINES_OUT.NON_SILENT Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3 CORE: PCore EventSel=26H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_LINES_OUT.SILENT Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event. CORE: PCore EventSel=26H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_LINES_OUT.USELESS_HWPF Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache CORE: PCore EventSel=26H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_CODE_RD Counts the total number of L2 code requests. CORE: PCore EventSel=24H UMask=E4H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_DEMAND_DATA_RD Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once. CORE: PCore EventSel=24H UMask=E1H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_DEMAND_MISS Counts demand requests that miss L2 cache. CORE: PCore EventSel=24H UMask=27H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_DEMAND_REFERENCES Counts demand requests to L2 cache. CORE: PCore EventSel=24H UMask=E7H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_HWPF L2_RQSTS.ALL_HWPF CORE: PCore EventSel=24H UMask=F0H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.ALL_RFO Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. CORE: PCore EventSel=24H UMask=E2H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.CODE_RD_HIT Counts L2 cache hits when fetching instructions, code reads. CORE: PCore EventSel=24H UMask=C4H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.CODE_RD_MISS Counts L2 cache misses when fetching instructions. CORE: PCore EventSel=24H UMask=24H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.DEMAND_DATA_RD_HIT Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. CORE: PCore EventSel=24H UMask=C1H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.DEMAND_DATA_RD_MISS Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once. CORE: PCore EventSel=24H UMask=21H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.HIT Counts all requests that hit L2 cache. CORE: PCore EventSel=24H UMask=DFH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.HWPF_MISS L2_RQSTS.HWPF_MISS CORE: PCore EventSel=24H UMask=30H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.MISS Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. CORE: PCore EventSel=24H UMask=3FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.REFERENCES Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. CORE: PCore EventSel=24H UMask=FFH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.RFO_HIT Counts the RFO (Read-for-Ownership) requests that hit L2 cache. CORE: PCore EventSel=24H UMask=C2H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.RFO_MISS Counts the RFO (Read-for-Ownership) requests that miss L2 cache. CORE: PCore EventSel=24H UMask=22H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.SWPF_HIT Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. CORE: PCore EventSel=24H UMask=C8H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_RQSTS.SWPF_MISS Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. CORE: PCore EventSel=24H UMask=28H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    L2_TRANS.L2_WB Counts L2 writebacks that access L2 cache. CORE: PCore EventSel=23H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LD_BLOCKS.ADDRESS_ALIAS Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address. CORE: PCore EventSel=03H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LD_BLOCKS.NO_SR Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. CORE: PCore EventSel=03H UMask=88H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LD_BLOCKS.STORE_FORWARD Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide. CORE: PCore EventSel=03H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LOAD_HIT_PREFETCH.SWPF Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. CORE: PCore EventSel=4CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LOCK_CYCLES.CACHE_LOCK_DURATION This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION). CORE: PCore EventSel=42H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    LSD.CYCLES_ACTIVE Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). CORE: PCore EventSel=A8H UMask=01H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    LSD.CYCLES_OK Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). CORE: PCore EventSel=A8H UMask=01H CMask=06H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    LSD.UOPS Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). CORE: PCore EventSel=A8H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    MACHINE_CLEARS.COUNT Counts the number of machine clears (nukes) of any type. CORE: PCore EventSel=C3H UMask=01H EdgeDetect=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture CORE: PCore EventSel=C3H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    MACHINE_CLEARS.SMC Counts self-modifying code (SMC) detected, which causes a machine clear. CORE: PCore EventSel=C3H UMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    MEM_INST_RETIRED.ALL_LOADS Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. CORE: PCore EventSel=D0H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.ALL_STORES Counts all retired store instructions. CORE: PCore EventSel=D0H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.ANY Counts all retired memory instructions - loads and stores. CORE: PCore EventSel=D0H UMask=83H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.LOCK_LOADS Counts retired load instructions with locked access. CORE: PCore EventSel=D0H UMask=21H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.SPLIT_LOADS Counts retired load instructions that split across a cacheline boundary. CORE: PCore EventSel=D0H UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.SPLIT_STORES Counts retired store instructions that split across a cacheline boundary. CORE: PCore EventSel=D0H UMask=42H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.STLB_HIT_LOADS Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). CORE: PCore EventSel=D0H UMask=09H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.STLB_HIT_STORES Number of retired store instructions that hit in the 2nd-level TLB (STLB). CORE: PCore EventSel=D0H UMask=0AH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.STLB_MISS_LOADS Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). CORE: PCore EventSel=D0H UMask=11H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_INST_RETIRED.STLB_MISS_STORES Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). CORE: PCore EventSel=D0H UMask=12H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_COMPLETED.L1_MISS_ANY Number of completed demand load requests that missed the L1 data cache including shadow misses (FB hits, merge to an ongoing L1D miss) CORE: PCore EventSel=43H UMask=FDH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD Counts retired load instructions whose data sources were HitM responses from shared L3. CORE: PCore EventSel=D2H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. CORE: PCore EventSel=D2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. CORE: PCore EventSel=D2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE Counts retired load instructions whose data sources were hits in L3 without snoops required. CORE: PCore EventSel=D2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM Retired load instructions which data sources missed L3 but serviced from local DRAM. CORE: PCore EventSel=D3H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_MISC_RETIRED.UC Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). CORE: PCore EventSel=D4H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.FB_HIT Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. CORE: PCore EventSel=D1H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L1_HIT Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. CORE: PCore EventSel=D1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L1_MISS Counts retired load instructions with at least one uop that missed in the L1 cache. CORE: PCore EventSel=D1H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L2_HIT Counts retired load instructions with L2 cache hits as data sources. CORE: PCore EventSel=D1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L2_MISS Counts retired load instructions missed L2 cache as data sources. CORE: PCore EventSel=D1H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L3_HIT Counts retired load instructions with at least one uop that hit in the L3 cache. CORE: PCore EventSel=D1H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_LOAD_RETIRED.L3_MISS Counts retired load instructions with at least one uop that missed in the L3 cache. CORE: PCore EventSel=D1H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_STORE_RETIRED.L2_HIT MEM_STORE_RETIRED.L2_HIT CORE: PCore EventSel=44H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024 Counts randomly selected loads when the latency from first dispatch to completion is greater than 1024 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048 Counts randomly selected loads when the latency from first dispatch to completion is greater than 2048 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. CORE: PCore EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H
    Counter=1,2,3,4,5,6,7 CounterHTOff=1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEM_TRANS_RETIRED.STORE_SAMPLE Counts Retired memory accesses with at least 1 store operation. This PEBS event is the precisely-distributed (PDist) trigger covering all stores uops for sampling by the PEBS Store Latency Facility. The facility is described in Intel SDM Volume 3 section 19.9.8 CORE: PCore EventSel=CDH UMask=02H
    Counter=0 CounterHTOff=0
    PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0]
    AtRetirement    		 PCoreOnly
    MEM_UOP_RETIRED.ANY Number of retired micro-operations (uops) for load or store memory accesses CORE: PCore EventSel=E5H UMask=03H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MEMORY_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding. CORE: PCore EventSel=47H UMask=02H CMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    MEMORY_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding. CORE: PCore EventSel=47H UMask=03H CMask=03H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    MEMORY_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock). CORE: PCore EventSel=47H UMask=05H CMask=05H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    MEMORY_ACTIVITY.STALLS_L3_MISS Execution stalls while L3 cache miss demand cacheable load request is outstanding (will not count for uncacheable demand requests e.g. bus lock). CORE: PCore EventSel=47H UMask=09H CMask=09H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    MISC_RETIRED.LBR_INSERTS Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT. CORE: PCore EventSel=CCH UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    MISC2_RETIRED.LFENCE number of LFENCE retired instructions CORE: PCore EventSel=E0H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.ALL_REQUESTS Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc.. CORE: PCore EventSel=21H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.DATA_RD Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. CORE: PCore EventSel=21H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.DEMAND_CODE_RD Counts both cacheable and Non-Cacheable code read requests. CORE: PCore EventSel=21H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.DEMAND_DATA_RD Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. CORE: PCore EventSel=21H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.DEMAND_RFO Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. CORE: PCore EventSel=21H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD Counts demand data read requests that miss the L3 cache. CORE: PCore EventSel=21H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. CORE: PCore EventSel=20H UMask=08H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. CORE: PCore EventSel=20H UMask=02H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Cycles where at least 1 outstanding demand data read request is pending. CORE: PCore EventSel=20H UMask=01H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. CORE: PCore EventSel=20H UMask=04H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ. CORE: PCore EventSel=20H UMask=10H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DATA_RD OFFCORE_REQUESTS_OUTSTANDING.DATA_RD CORE: PCore EventSel=20H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. CORE: PCore EventSel=20H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. CORE: PCore EventSel=20H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion. CORE: PCore EventSel=20H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD For every cycle, increments by the number of demand data read requests pending that are known to have missed the L3 cache. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known by the requesting core to have missed the L3 cache. CORE: PCore EventSel=20H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    RESOURCE_STALLS.SB Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end. CORE: PCore EventSel=A2H UMask=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    RESOURCE_STALLS.SCOREBOARD Counts cycles where the pipeline is stalled due to serializing operations. CORE: PCore EventSel=A2H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    RS.EMPTY Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) CORE: PCore EventSel=A5H UMask=07H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    RS.EMPTY_COUNT Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) CORE: PCore EventSel=A5H UMask=07H EdgeDetect=1 Invert=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    RS.EMPTY_RESOURCE Cycles when RS was empty and a resource allocation stall is asserted CORE: PCore EventSel=A5H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    SQ_MISC.BUS_LOCK Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory. CORE: PCore EventSel=2CH UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    SW_PREFETCH_ACCESS.ANY Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed. CORE: PCore EventSel=40H UMask=0FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    SW_PREFETCH_ACCESS.NTA Counts the number of PREFETCHNTA instructions executed. CORE: PCore EventSel=40H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    SW_PREFETCH_ACCESS.PREFETCHW Counts the number of PREFETCHW instructions executed. CORE: PCore EventSel=40H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    SW_PREFETCH_ACCESS.T0 Counts the number of PREFETCHT0 instructions executed. CORE: PCore EventSel=40H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    SW_PREFETCH_ACCESS.T1_T2 Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. CORE: PCore EventSel=40H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    TOPDOWN.BAD_SPEC_SLOTS Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations. CORE: PCore EventSel=A4H UMask=04H
    Counter=0 CounterHTOff=0
    PEBS:[NonPreciseEventingIP, Counter=0]
    Speculative    		 PCoreOnly
    TOPDOWN.BR_MISPREDICT_SLOTS Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction. CORE: PCore EventSel=A4H UMask=08H
    Counter=0 CounterHTOff=0
    PEBS:[NonPreciseEventingIP, Counter=0]
    Speculative    		 PCoreOnly
    TOPDOWN.MEMORY_BOUND_SLOTS TOPDOWN.MEMORY_BOUND_SLOTS CORE: PCore EventSel=A4H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DECODED.DEC0_UOPS This event counts the number of not dec-by-all uops decoded by decoder 0. CORE: PCore EventSel=76H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_0 Number of uops dispatch to execution port 0. CORE: PCore EventSel=B2H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_1 Number of uops dispatch to execution port 1. CORE: PCore EventSel=B2H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_2_3_10 Number of uops dispatch to execution ports 2, 3 and 10 CORE: PCore EventSel=B2H UMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_4_9 Number of uops dispatch to execution ports 4 and 9 CORE: PCore EventSel=B2H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_5_11 Number of uops dispatch to execution ports 5 and 11 CORE: PCore EventSel=B2H UMask=20H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_6 Number of uops dispatch to execution port 6. CORE: PCore EventSel=B2H UMask=40H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_DISPATCHED.PORT_7_8 Number of uops dispatch to execution ports 7 and 8. CORE: PCore EventSel=B2H UMask=80H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CORE Counts the number of uops executed from any thread. CORE: PCore EventSel=B1H UMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_1 Counts cycles when at least 1 micro-op is executed from any thread on physical core. CORE: PCore EventSel=B1H UMask=02H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_2 Counts cycles when at least 2 micro-ops are executed from any thread on physical core. CORE: PCore EventSel=B1H UMask=02H CMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_3 Counts cycles when at least 3 micro-ops are executed from any thread on physical core. CORE: PCore EventSel=B1H UMask=02H CMask=03H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_4 Counts cycles when at least 4 micro-ops are executed from any thread on physical core. CORE: PCore EventSel=B1H UMask=02H CMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CYCLES_GE_1 Cycles where at least 1 uop was executed per-thread. CORE: PCore EventSel=B1H UMask=01H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CYCLES_GE_2 Cycles where at least 2 uops were executed per-thread. CORE: PCore EventSel=B1H UMask=01H CMask=02H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CYCLES_GE_3 Cycles where at least 3 uops were executed per-thread. CORE: PCore EventSel=B1H UMask=01H CMask=03H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.CYCLES_GE_4 Cycles where at least 4 uops were executed per-thread. CORE: PCore EventSel=B1H UMask=01H CMask=04H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.STALLS Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. CORE: PCore EventSel=B1H UMask=01H Invert=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.THREAD Counts the number of uops to be executed per-thread each cycle. CORE: PCore EventSel=B1H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_EXECUTED.X87 Counts the number of x87 uops executed. CORE: PCore EventSel=B1H UMask=10H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_ISSUED.ANY Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS). CORE: PCore EventSel=AEH UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_ISSUED.CYCLES UOPS_ISSUED.CYCLES CORE: PCore EventSel=AEH UMask=01H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 PCoreOnly
    UOPS_RETIRED.CYCLES Counts cycles where at least one uop has retired. CORE: PCore EventSel=C2H UMask=02H CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    UOPS_RETIRED.HEAVY Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count. CORE: PCore EventSel=C2H UMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    UOPS_RETIRED.MS UOPS_RETIRED.MS CORE: PCore EventSel=C2H UMask=04H MSR_PEBS_FRONTEND(3F7H)=08H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    UOPS_RETIRED.STALLS This event counts cycles without actually retired uops. CORE: PCore EventSel=C2H UMask=02H Invert=1 CMask=01H
    Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 PCoreOnly
    XQ.FULL_CYCLES number of cycles when the thread is active and the uncore cannot take any further requests (for example prefetches, loads or stores initiated by the Core that miss the L2 cache). CORE: PCore EventSel=2DH UMask=01H CMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative    		 PCoreOnly
    E-core ECoreOnly
    INST_RETIRED.ANY Fixed Counter: Counts the number of instructions retired CORE: ECore IA32_FIXED_CTR0
    PEBS:[PreciseEventingIP, PDISTCounter=32]
    Architectural, Fixed, AtRetirement    		 ECoreOnly
    CPU_CLK_UNHALTED.CORE Fixed Counter: Counts the number of unhalted core clock cycles CORE: ECore IA32_FIXED_CTR1
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 ECoreOnly
    CPU_CLK_UNHALTED.THREAD Fixed Counter: Counts the number of unhalted core clock cycles CORE: ECore IA32_FIXED_CTR1
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 ECoreOnly
    CPU_CLK_UNHALTED.REF_TSC Fixed Counter: Counts the number of unhalted reference clock cycles CORE: ECore IA32_FIXED_CTR2
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed, Speculative    		 ECoreOnly
    BR_INST_RETIRED.ALL_BRANCHES Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. CORE: ECore EventSel=C4H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. CORE: ECore EventSel=C5H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 ECoreOnly
    CPU_CLK_UNHALTED.CORE_P Counts the number of unhalted core clock cycles CORE: ECore EventSel=3CH UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 ECoreOnly
    CPU_CLK_UNHALTED.REF_TSC_P Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. CORE: ECore EventSel=3CH UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 ECoreOnly
    INST_RETIRED.ANY_P Counts the number of instructions retired CORE: ECore EventSel=C0H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, AtRetirement    		 ECoreOnly
    LONGEST_LAT_CACHE.MISS Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. CORE: ECore EventSel=2EH UMask=41H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 ECoreOnly
    LONGEST_LAT_CACHE.REFERENCE Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. CORE: ECore EventSel=2EH UMask=4FH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Architectural, Speculative    		 ECoreOnly
    ARITH.DIV_ACTIVE Counts the number of cycles when any of the dividers are active. CORE: ECore EventSel=CDH UMask=03H CMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ARITH.FPDIV_ACTIVE Counts the number of cycles when any of the floating point dividers are active. CORE: ECore EventSel=CDH UMask=02H CMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    BACLEARS.ANY Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. CORE: ECore EventSel=E6H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    BR_INST_RETIRED.COND Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. CORE: ECore EventSel=C4H UMask=7EH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.COND_TAKEN Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. CORE: ECore EventSel=C4H UMask=FEH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.FAR_BRANCH Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. CORE: ECore EventSel=C4H UMask=BFH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.INDIRECT Counts the number of near indirect JMP and near indirect CALL branch instructions retired. CORE: ECore EventSel=C4H UMask=EBH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.INDIRECT_CALL Counts the number of near indirect CALL branch instructions retired. CORE: ECore EventSel=C4H UMask=FBH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.NEAR_CALL Counts the number of near CALL branch instructions retired. CORE: ECore EventSel=C4H UMask=F9H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.NEAR_RETURN Counts the number of near RET branch instructions retired. CORE: ECore EventSel=C4H UMask=F7H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.COND Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. CORE: ECore EventSel=C5H UMask=7EH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.COND_TAKEN Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. CORE: ECore EventSel=C5H UMask=FEH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.INDIRECT Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. CORE: ECore EventSel=C5H UMask=EBH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.INDIRECT_CALL Counts the number of mispredicted near indirect CALL branch instructions retired. CORE: ECore EventSel=C5H UMask=FBH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.NEAR_TAKEN Counts the number of mispredicted near taken branch instructions retired. CORE: ECore EventSel=C5H UMask=80H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_MISP_RETIRED.RETURN Counts the number of mispredicted near RET branch instructions retired. CORE: ECore EventSel=C5H UMask=F7H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    DTLB_LOAD_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB. CORE: ECore EventSel=08H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED Counts the number of page walks completed due to load DTLB misses. CORE: ECore EventSel=08H UMask=0EH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. CORE: ECore EventSel=08H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. CORE: ECore EventSel=08H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_LOAD_MISSES.WALK_PENDING Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. CORE: ECore EventSel=08H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_STORE_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB. CORE: ECore EventSel=49H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED Counts the number of page walks completed due to store DTLB misses to a 1G page. CORE: ECore EventSel=49H UMask=0EH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. CORE: ECore EventSel=49H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. CORE: ECore EventSel=49H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    DTLB_STORE_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. CORE: ECore EventSel=49H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    FP_FLOPS_RETIRED.ALL Counts the number of all types of floating point operations per uop with all default weighting CORE: ECore EventSel=C8H UMask=03H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_INST_RETIRED.128B_DP Counts the total number of floating point retired instructions. CORE: ECore EventSel=C7H UMask=08H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_INST_RETIRED.128B_SP Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. CORE: ECore EventSel=C7H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_INST_RETIRED.256B_DP Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. CORE: ECore EventSel=C7H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_INST_RETIRED.32B_SP Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. CORE: ECore EventSel=C7H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_INST_RETIRED.64B_DP Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. CORE: ECore EventSel=C7H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    FP_VINT_UOPS_EXECUTED.STD Counts the number of uops executed on floating point and vector integer store data port. CORE: ECore EventSel=B2H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    FRONTEND_RETIRED.ITLB_MISS Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss CORE: ECore EventSel=C6H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    ICACHE.ACCESSES Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump. CORE: ECore EventSel=80H UMask=03H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ICACHE.MISSES Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - CORE: ECore EventSel=80H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.MISS_CAUSED_WALK Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs. CORE: ECore EventSel=85H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB. CORE: ECore EventSel=85H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.WALK_COMPLETED Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. CORE: ECore EventSel=85H UMask=0EH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. CORE: ECore EventSel=85H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. CORE: ECore EventSel=85H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    ITLB_MISSES.WALK_PENDING Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks. CORE: ECore EventSel=85H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_BLOCKS.ADDRESS_ALIAS Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. CORE: ECore EventSel=03H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    LD_BLOCKS.DATA_UNKNOWN Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. CORE: ECore EventSel=03H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    LD_BLOCKS.STORE_FORWARD Counts the number of retired loads that are blocked because its address partially overlapped with an older store. CORE: ECore EventSel=03H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    LD_HEAD.ANY_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. CORE: ECore EventSel=05H UMask=FFH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.DTLB_MISS_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss. CORE: ECore EventSel=05H UMask=90H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.L1_BOUND_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. CORE: ECore EventSel=05H UMask=F4H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.L1_MISS_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss. CORE: ECore EventSel=05H UMask=81H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.OTHER_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc. CORE: ECore EventSel=05H UMask=C0H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.PGWALK_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk. CORE: ECore EventSel=05H UMask=A0H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    LD_HEAD.ST_ADDR_AT_RET Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match. CORE: ECore EventSel=05H UMask=84H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.ANY Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist. CORE: ECore EventSel=C3H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.DISAMBIGUATION Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. CORE: ECore EventSel=C3H UMask=08H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.FP_ASSIST Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. CORE: ECore EventSel=C3H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. CORE: ECore EventSel=C3H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.MRN_NUKE Counts the number of machines clears due to memory renaming. CORE: ECore EventSel=C3H UMask=80H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.PAGE_FAULT Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. CORE: ECore EventSel=C3H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.SLOW Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP. CORE: ECore EventSel=C3H UMask=6FH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MACHINE_CLEARS.SMC Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. CORE: ECore EventSel=C3H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_IFETCH.ALL Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss. CORE: ECore EventSel=35H UMask=7FH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_IFETCH.L2_HIT Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache. CORE: ECore EventSel=35H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_IFETCH.LLC_HIT Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC. CORE: ECore EventSel=35H UMask=06H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_IFETCH.LLC_MISS Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches. CORE: ECore EventSel=35H UMask=78H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_LOAD.ALL Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss. CORE: ECore EventSel=34H UMask=7FH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_LOAD.L2_HIT Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache. CORE: ECore EventSel=34H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_LOAD.LLC_HIT Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. CORE: ECore EventSel=34H UMask=06H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_BOUND_STALLS_LOAD.LLC_MISS Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. CORE: ECore EventSel=34H UMask=78H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM Counts the number of load ops retired that miss the L3 cache and hit in DRAM CORE: ECore EventSel=D4H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_HIT Counts the number of load ops retired that hit the L1 data cache. CORE: ECore EventSel=D1H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_MISS Counts the number of load ops retired that miss in the L1 data cache. CORE: ECore EventSel=D1H UMask=40H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_HIT Counts the number of load ops retired that hit in the L2 cache. CORE: ECore EventSel=D1H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_MISS Counts the number of load ops retired that miss in the L2 cache. CORE: ECore EventSel=D1H UMask=80H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.L3_HIT Counts the number of load ops retired that hit in the L3 cache. CORE: ECore EventSel=D1H UMask=1CH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_LOAD_UOPS_RETIRED.WCB_HIT Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate. CORE: ECore EventSel=D1H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_SCHEDULER_BLOCK.ALL Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. CORE: ECore EventSel=04H UMask=07H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_SCHEDULER_BLOCK.LD_BUF Counts the number of cycles that uops are blocked due to a load buffer full condition. CORE: ECore EventSel=04H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_SCHEDULER_BLOCK.RSV Counts the number of cycles that uops are blocked due to an RSV full condition. CORE: ECore EventSel=04H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_SCHEDULER_BLOCK.ST_BUF Counts the number of cycles that uops are blocked due to a store buffer full condition. CORE: ECore EventSel=04H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    MEM_UOPS_RETIRED.ALL_LOADS Counts the number of load ops retired. CORE: ECore EventSel=D0H UMask=81H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.ALL_STORES Counts the number of store ops retired. CORE: ECore EventSel=D0H UMask=82H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8 Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. CORE: ECore EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H
    Counter=0,1
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.LOCK_LOADS Counts the number of load uops retired that performed one or more locks CORE: ECore EventSel=D0H UMask=21H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.SPLIT Counts the number of memory uops retired that were splits. CORE: ECore EventSel=D0H UMask=43H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.SPLIT_LOADS Counts the number of retired split load uops. CORE: ECore EventSel=D0H UMask=41H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.SPLIT_STORES Counts the number of retired split store uops. CORE: ECore EventSel=D0H UMask=42H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MEM_UOPS_RETIRED.STORE_LATENCY Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES CORE: ECore EventSel=D0H UMask=06H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MISALIGN_MEM_REF.LOAD_PAGE_SPLIT Counts misaligned loads that are 4K page splits. CORE: ECore EventSel=13H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MISALIGN_MEM_REF.STORE_PAGE_SPLIT Counts misaligned stores that are 4K page splits. CORE: ECore EventSel=13H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    MISC_RETIRED.LBR_INSERTS Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. CORE: ECore EventSel=E4H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    SERIALIZATION.C01_MS_SCB Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. CORE: ECore EventSel=75H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BAD_SPECULATION.ALL_P Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. CORE: ECore EventSel=73H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BAD_SPECULATION.FASTNUKE Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes CORE: ECore EventSel=73H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. CORE: ECore EventSel=73H UMask=03H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BAD_SPECULATION.MISPREDICT Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict CORE: ECore EventSel=73H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BAD_SPECULATION.NUKE Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). CORE: ECore EventSel=73H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.ALL_P Counts the number of retirement slots not consumed due to backend stalls CORE: ECore EventSel=74H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions CORE: ECore EventSel=74H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block. CORE: ECore EventSel=74H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) CORE: ECore EventSel=74H UMask=08H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.REGISTER Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST). CORE: ECore EventSel=74H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.REORDER_BUFFER Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full CORE: ECore EventSel=74H UMask=40H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_BE_BOUND.SERIALIZATION Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb CORE: ECore EventSel=74H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.ALL_P Counts the number of retirement slots not consumed due to front end stalls CORE: ECore EventSel=71H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.BRANCH_DETECT Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear CORE: ECore EventSel=71H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.BRANCH_RESTEER Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear CORE: ECore EventSel=71H UMask=40H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.CISC Counts the number of issue slots every cycle that were not delivered by the frontend due to ms CORE: ECore EventSel=71H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.DECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall CORE: ECore EventSel=71H UMask=08H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. CORE: ECore EventSel=71H UMask=8DH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.FRONTEND_LATENCY Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. CORE: ECore EventSel=71H UMask=72H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.ICACHE Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss CORE: ECore EventSel=71H UMask=20H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.ITLB_MISS Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss CORE: ECore EventSel=71H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.OTHER Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall CORE: ECore EventSel=71H UMask=80H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_FE_BOUND.PREDECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong CORE: ECore EventSel=71H UMask=04H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    TOPDOWN_RETIRING.ALL_P Counts the number of consumed retirement slots. CORE: ECore EventSel=72H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    UOPS_ISSUED.ANY Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. CORE: ECore EventSel=0EH UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    Speculative    		 ECoreOnly
    UOPS_RETIRED.ALL Counts the total number of uops retired. CORE: ECore EventSel=C2H UMask=00H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    UOPS_RETIRED.FPDIV Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). CORE: ECore EventSel=C2H UMask=08H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    UOPS_RETIRED.IDIV Counts the number of integer divide uops retired. CORE: ECore EventSel=C2H UMask=10H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    UOPS_RETIRED.MS Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. CORE: ECore EventSel=C2H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    UOPS_RETIRED.X87 Counts the number of x87 uops retired, includes those in ms flows CORE: ECore EventSel=C2H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement    		 ECoreOnly
    BR_INST_RETIRED.IND_CALL This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL CORE: ECore EventSel=C4H UMask=FBH
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement, Deprecated    		 ECoreOnly
    FP_FLOPS_RETIRED.DP This event is deprecated. CORE: ECore EventSel=C8H UMask=01H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement, Deprecated    		 ECoreOnly
    FP_FLOPS_RETIRED.SP This event is deprecated. CORE: ECore EventSel=C8H UMask=02H
    Counter=0,1,2,3,4,5,6,7
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7]
    AtRetirement, Deprecated    		 ECoreOnly
    UNCORE Uncore
    UNC_CLOCK.SOCKET This 48-bit fixed counter counts the UCLK cycles. MSR_UNC_PERF_FIXED_CTR
    Fixed    		 Uncore
    UNC_ARB_DAT_OCCUPANCY.RD Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core. EventSel=85H UMask=02H
    Counter=0    		 Uncore
    UNC_HAC_ARB_REQ_TRK_REQUEST.DRD Number of all coherent Data Read entries. Doesn't include prefetches EventSel=81H UMask=02H
    Counter=0,1    		 Uncore
    UNC_HAC_ARB_TRANSACTIONS.ALL Number of all CMI transactions EventSel=8AH UMask=01H
    Counter=0,1    		 Uncore
    UNC_HAC_ARB_TRANSACTIONS.READS Number of all CMI reads EventSel=8AH UMask=02H
    Counter=0,1    		 Uncore
    UNC_HAC_ARB_TRANSACTIONS.WRITES Number of all CMI writes not including "Mflush" EventSel=8AH UMask=04H
    Counter=0,1    		 Uncore
    UNC_HAC_ARB_TRK_REQUESTS.ALL Total number of all outgoing entries allocated. Accounts for Coherent and non-coherent traffic. EventSel=81H UMask=01H
    Counter=0,1    		 Uncore
    UNC_HAC_CBO_TOR_ALLOCATION.ALL Number of all entries allocated. Includes also retries. EventSel=35H UMask=08H
    Counter=0,1    		 Uncore
    UNC_HAC_CBO_TOR_ALLOCATION.DRD Asserted on coherent DRD + DRdPref allocations into the queue. Cacheable only EventSel=35H UMask=01H
    Counter=0,1    		 Uncore
    UNC_M_ACT_COUNT_RD ACT command for a read request sent to DRAM EventSel=24H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_ACT_COUNT_TOTAL ACT command sent to DRAM EventSel=26H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_ACT_COUNT_WR ACT command for a write request sent to DRAM EventSel=25H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_CAS_COUNT_RD Read CAS command sent to DRAM EventSel=22H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_CAS_COUNT_WR Write CAS command sent to DRAM EventSel=23H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_PRE_COUNT_IDLE PRE command sent to DRAM due to page table idle timer expiration EventSel=28H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_PRE_COUNT_PAGE_MISS PRE command sent to DRAM for a read/write request EventSel=27H UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_RD_DATA Number of bytes read from DRAM, in 32B chunks. Counter increments by 1 after receiving 32B chunk data. EventSel=3AH UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_TOTAL_DATA Total number of read and write byte transfers to/from DRAM, in 32B chunks. Counter increments by 1 after sending or receiving 32B chunk data. EventSel=3CH UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_M_WR_DATA Number of bytes written to DRAM, in 32B chunks. Counter increments by 1 after sending 32B chunk data. EventSel=3BH UMask=00H
    Counter=0,1,2,3,4    		 Uncore
    UNC_MC0_RDCAS_COUNT_FREERUN Counts every CAS read command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. EventSel=00H UMask=00H
    Counter=0    		 Uncore
    UNC_MC0_TOTAL_REQCOUNT_FREERUN Counts every read and write request entering the Memory Controller 0 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW. EventSel=00H UMask=00H
    Counter=2    		 Uncore
    UNC_MC0_WRCAS_COUNT_FREERUN Counts every CAS write command sent from the Memory Controller 0 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. EventSel=00H UMask=00H
    Counter=1    		 Uncore
    UNC_MC1_RDCAS_COUNT_FREERUN Counts every CAS read command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. EventSel=00H UMask=00H
    Counter=3    		 Uncore
    UNC_MC1_TOTAL_REQCOUNT_FREERUN Counts every read and write request entering the Memory Controller 1 (sum of all channels). All requests are counted as one, whether they are 32B or 64B Read/Write or partial/full line writes. Some write requests to the same address may merge to a single write command to DRAM. Therefore, the total request count may be higher than total DRAM BW. EventSel=00H UMask=00H
    Counter=5    		 Uncore
    UNC_MC1_WRCAS_COUNT_FREERUN Counts every CAS write command sent from the Memory Controller 1 to DRAM (sum of all channels). Each CAS commands can be for 32B or 64B of data. EventSel=00H UMask=00H
    Counter=4    		 Uncore
    P-core Offcore PCoreOffcore
    OCR.DEMAND_DATA_RD.L3_MISS Counts demand data reads that were not supplied by the L3 cache. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00001H PCoreOffcore
    OCR.DEMAND_DATA_RD.ANY_RESPONSE Counts demand data reads that have any type of response. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H PCoreOffcore
    OCR.DEMAND_DATA_RD.DRAM Counts demand data reads that were supplied by DRAM. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H PCoreOffcore
    OCR.STREAMING_WR.ANY_RESPONSE Counts streaming stores that have any type of response. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H PCoreOffcore
    OCR.DEMAND_RFO.L3_MISS Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00002H PCoreOffcore
    OCR.DEMAND_RFO.ANY_RESPONSE Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H PCoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H PCoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand data reads that resulted in a snoop hit in another cores caches which forwarded the unmodified data to the requesting core. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H PCoreOffcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified. EventSel={2AH,2BH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H PCoreOffcore
    E-core Offcore ECoreOffcore
    OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000H ECoreOffcore
    OCR.FULL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify a full 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000H ECoreOffcore
    OCR.DEMAND_DATA_RD.ANY_RESPONSE Counts demand data reads that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H ECoreOffcore
    OCR.DEMAND_RFO.ANY_RESPONSE Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H ECoreOffcore
    OCR.STREAMING_WR.ANY_RESPONSE Counts streaming stores that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H ECoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H ECoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H ECoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H ECoreOffcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H ECoreOffcore
    OCR.DEMAND_DATA_RD.L3_HIT Counts demand data reads that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0001H ECoreOffcore
    OCR.DEMAND_RFO.L3_HIT Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0002H ECoreOffcore
    OCR.DEMAND_DATA_RD.L3_MISS Counts demand data reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00001H ECoreOffcore
    OCR.DEMAND_RFO.L3_MISS Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00002H ECoreOffcore
    OCR.DEMAND_DATA_RD.DRAM Counts demand data reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H ECoreOffcore
    OCR.DEMAND_RFO.DRAM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H ECoreOffcore