Intel® Xeon Phi™ Processor
This section provides reference for hardware events that can be monitored for the CPU(s):
  • Intel® Xeon Phi™ processor Code Named Knights Landing Events
  • Intel® Xeon Phi™ processor Code Named Knights Mill Events
  • CORE
    Event Name Description Additional Info EventType
    INST_RETIRED.ANY This event counts the number of instructions that retire. For instructions that consist of multiple micro-ops, this event counts exactly once, as the last micro-op of the instruction retires. The event continues counting while instructions retire, including during interrupt service routines caused by hardware interrupts, faults or traps. IA32_FIXED_CTR0
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.THREAD This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter IA32_FIXED_CTR1
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.REF_TSC Fixed Counter: Counts the number of unhalted reference clock cycles IA32_FIXED_CTR2
    Architectural, Fixed
    CoreOnly
    BR_INST_RETIRED.ALL_BRANCHES Counts the number of branch instructions retired EventSel=C4H UMask=00H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    Architectural
    CoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES Counts the number of mispredicted branch instructions retired EventSel=C5H UMask=00H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.REF Counts the number of unhalted reference clock cycles EventSel=3CH UMask=01H
    Counter=0,1
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.THREAD_P Counts the number of unhalted core clock cycles EventSel=3CH UMask=00H
    Counter=0,1
    Architectural
    CoreOnly
    INST_RETIRED.ANY_P Counts the total number of instructions retired EventSel=C0H UMask=00H
    Counter=0,1
    Architectural
    CoreOnly
    L2_REQUESTS.MISS Counts the number of L2 cache misses EventSel=2EH UMask=41H
    Counter=0,1
    Architectural
    CoreOnly
    L2_REQUESTS.REFERENCE Counts the total number of L2 cache references. EventSel=2EH UMask=4FH
    Counter=0,1
    Architectural
    CoreOnly
    LONGEST_LAT_CACHE.MISS Counts the number of L2 cache misses EventSel=2EH UMask=41H
    Counter=0,1
    Architectural
    CoreOnly
    LONGEST_LAT_CACHE.REFERENCE Counts the total number of L2 cache references. EventSel=2EH UMask=4FH
    Counter=0,1
    Architectural
    CoreOnly
    BACLEARS.ALL Counts the number of times the front end resteers for any branch as a result of another branch handling mechanism in the front end. EventSel=E6H UMask=01H
    Counter=0,1
    CoreOnly
    BACLEARS.COND Counts the number of times the front end resteers for conditional branches as a result of another branch handling mechanism in the front end. EventSel=E6H UMask=10H
    Counter=0,1
    CoreOnly
    BACLEARS.RETURN Counts the number of times the front end resteers for RET branches as a result of another branch handling mechanism in the front end. EventSel=E6H UMask=08H
    Counter=0,1
    CoreOnly
    BR_INST_RETIRED.CALL Counts the number of near CALL branch instructions retired. EventSel=C4H UMask=F9H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.FAR_BRANCH Counts the number of far branch instructions retired. EventSel=C4H UMask=BFH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.IND_CALL Counts the number of near indirect CALL branch instructions retired. EventSel=C4H UMask=FBH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.JCC Counts the number of branch instructions retired that were conditional jumps. EventSel=C4H UMask=7EH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NON_RETURN_IND Counts the number of branch instructions retired that were near indirect CALL or near indirect JMP. EventSel=C4H UMask=EBH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.REL_CALL Counts the number of near relative CALL branch instructions retired. EventSel=C4H UMask=FDH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.RETURN Counts the number of near RET branch instructions retired. EventSel=C4H UMask=F7H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.TAKEN_JCC Counts the number of branch instructions retired that were taken conditional jumps. EventSel=C4H UMask=FEH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.CALL Counts the number of mispredicted near CALL branch instructions retired. EventSel=C5H UMask=F9H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.FAR_BRANCH Counts the number of mispredicted far branch instructions retired. EventSel=C5H UMask=BFH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.IND_CALL Counts the number of mispredicted near indirect CALL branch instructions retired. EventSel=C5H UMask=FBH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.JCC Counts the number of mispredicted branch instructions retired that were conditional jumps. EventSel=C5H UMask=7EH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.NON_RETURN_IND Counts the number of mispredicted branch instructions retired that were near indirect CALL or near indirect JMP. EventSel=C5H UMask=EBH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.REL_CALL Counts the number of mispredicted near relative CALL branch instructions retired. EventSel=C5H UMask=FDH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.RETURN Counts the number of mispredicted near RET branch instructions retired. EventSel=C5H UMask=F7H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.TAKEN_JCC Counts the number of mispredicted branch instructions retired that were taken conditional jumps. EventSel=C5H UMask=FEH
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    CORE_REJECT_L2Q.ALL Counts the number of MEC requests that were not accepted into the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might include requests due to instructions in the speculative path. EventSel=31H UMask=00H
    Counter=0,1
    CoreOnly
    CYCLES_DIV_BUSY.ALL This event counts cycles when the divider is busy. More specifically cycles when the divide unit is unable to accept a new divide uop because it is busy processing a previously dispatched uop. The cycles will be counted irrespective of whether or not another divide uop is waiting to enter the divide unit (from the RS). This event counts integer divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not count vector divides. EventSel=CDH UMask=01H
    Counter=0,1
    CoreOnly
    FETCH_STALL.ICACHE_FILL_PENDING_CYCLES This event counts the number of core cycles the fetch stalls because of an icache miss. This is a cumulative count of cycles the NIP stalled for all icache misses. EventSel=86H UMask=04H
    Counter=0,1
    CoreOnly
    ICACHE.ACCESSES Counts all instruction fetches, including uncacheable fetches. EventSel=80H UMask=03H
    Counter=0,1
    CoreOnly
    ICACHE.HIT Counts all instruction fetches that hit the instruction cache. EventSel=80H UMask=01H
    Counter=0,1
    CoreOnly
    ICACHE.MISSES Counts all instruction fetches that miss the instruction cache or produce memory requests. An instruction fetch miss is counted only once and not once for every cycle it is outstanding. EventSel=80H UMask=02H
    Counter=0,1
    CoreOnly
    L2_PREFETCHER.ALLOC_XQ Counts the number of L2HWP allocated into XQ GP EventSel=3EH UMask=04H
    Counter=0,1
    CoreOnly
    L2_REQUESTS_REJECT.ALL Counts the number of MEC requests from the L2Q that reference a cache line (cacheable requests) excluding SW prefetches filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated rejects should be counted multiple times EventSel=30H UMask=00H
    Counter=0,1
    CoreOnly
    MACHINE_CLEARS.ALL Counts all machine clears EventSel=C3H UMask=08H
    Counter=0,1
    CoreOnly
    MACHINE_CLEARS.FP_ASSIST This event counts the number of times that the pipeline stalled due to FP operations needing assists. EventSel=C3H UMask=04H
    Counter=0,1
    CoreOnly
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of times the machine clears due to memory ordering hazards EventSel=C3H UMask=02H
    Counter=0,1
    CoreOnly
    MACHINE_CLEARS.SMC Counts the number of times that the machine clears due to program modifying data within 1K of a recently fetched code page EventSel=C3H UMask=01H
    Counter=0,1
    CoreOnly
    MEM_UOPS_RETIRED.ALL_LOADS This event counts the number of load micro-ops retired. EventSel=04H UMask=40H
    Counter=0,1
    CoreOnly
    MEM_UOPS_RETIRED.ALL_STORES This event counts the number of store micro-ops retired. EventSel=04H UMask=80H
    Counter=0,1
    CoreOnly
    MEM_UOPS_RETIRED.DTLB_MISS_LOADS Counts the number of load micro-ops retired that cause a DTLB miss EventSel=04H UMask=08H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.HITM Counts the loads retired that get the data from the other core in the same tile in M state EventSel=04H UMask=20H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.L1_MISS_LOADS This event counts the number of load micro-ops retired that miss in L1 Data cache. Note that prefetch misses will not be counted. EventSel=04H UMask=01H
    Counter=0,1
    CoreOnly
    MEM_UOPS_RETIRED.L2_HIT_LOADS Counts the number of load micro-ops retired that hit in the L2 EventSel=04H UMask=02H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.L2_MISS_LOADS Counts the number of load micro-ops retired that miss in the L2 EventSel=04H UMask=04H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.UTLB_MISS_LOADS Counts the number of load micro-ops retired that caused micro TLB miss EventSel=04H UMask=10H
    Counter=0,1
    CoreOnly
    MS_DECODED.MS_ENTRY Counts the number of times the MSROM starts a flow of uops. EventSel=E7H UMask=01H
    Counter=0,1
    CoreOnly
    NO_ALLOC_CYCLES.ALL Counts the total number of core cycles when no micro-ops are allocated for any reason. EventSel=CAH UMask=7FH
    Counter=0,1
    CoreOnly
    NO_ALLOC_CYCLES.MISPREDICTS This event counts the number of core cycles when no uops are allocated and the alloc pipe is stalled waiting for a mispredicted branch to retire. EventSel=CAH UMask=04H
    Counter=0,1
    CoreOnly
    NO_ALLOC_CYCLES.NOT_DELIVERED This event counts the number of core cycles when no uops are allocated, the instruction queue is empty and the alloc pipe is stalled waiting for instructions to be fetched. EventSel=CAH UMask=90H
    Counter=0,1
    CoreOnly
    NO_ALLOC_CYCLES.RAT_STALL Counts the number of core cycles when no micro-ops are allocated and a RATstall (caused by reservation station full) is asserted. EventSel=CAH UMask=20H
    Counter=0,1
    CoreOnly
    NO_ALLOC_CYCLES.ROB_FULL Counts the number of core cycles when no micro-ops are allocated and the ROB is full EventSel=CAH UMask=01H
    Counter=0,1
    CoreOnly
    PAGE_WALKS.CYCLES This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. EventSel=05H UMask=03H
    Counter=0,1
    CoreOnly
    PAGE_WALKS.D_SIDE_CYCLES Counts the total number of core cycles for all the D-side page walks. The cycles for page walks started in speculative path will also be included. EventSel=05H UMask=01H
    Counter=0,1
    CoreOnly
    PAGE_WALKS.D_SIDE_WALKS Counts the total D-side page walks that are completed or started. The page walks started in the speculative path will also be counted EventSel=05H UMask=01H EdgeDetect=1
    Counter=0,1
    CoreOnly
    PAGE_WALKS.I_SIDE_CYCLES This event counts every cycle when an I-side (walks due to an instruction fetch) page walk is in progress. EventSel=05H UMask=02H
    Counter=0,1
    CoreOnly
    PAGE_WALKS.I_SIDE_WALKS Counts the total I-side page walks that are completed. EventSel=05H UMask=02H EdgeDetect=1
    Counter=0,1
    CoreOnly
    PAGE_WALKS.WALKS Counts the total page walks that are completed (I-side and D-side) EventSel=05H UMask=03H EdgeDetect=1
    Counter=0,1
    CoreOnly
    RECYCLEQ.ANY_LD Counts any retired load that was pushed into the recycle queue for any reason. EventSel=03H UMask=40H
    Counter=0,1
    CoreOnly
    RECYCLEQ.ANY_ST Counts any retired store that was pushed into the recycle queue for any reason. EventSel=03H UMask=80H
    Counter=0,1
    CoreOnly
    RECYCLEQ.LD_BLOCK_ST_FORWARD Counts the number of occurrences a retired load gets blocked because its address partially overlaps with a store EventSel=03H UMask=01H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    RECYCLEQ.LD_BLOCK_STD_NOTREADY Counts the number of occurrences a retired load gets blocked because its address overlaps with a store whose data is not ready EventSel=03H UMask=02H
    Counter=0,1
    CoreOnly
    RECYCLEQ.LD_SPLITS Counts the number of occurrences a retired load that is a cache line split. Each split should be counted only once. EventSel=03H UMask=08H
    Counter=0,1
    PEBS:[PreciseEventingIP]
    CoreOnly
    RECYCLEQ.LOCK Counts all the retired locked loads. It does not include stores because we would double count if we count stores EventSel=03H UMask=10H
    Counter=0,1
    CoreOnly
    RECYCLEQ.ST_SPLITS This event counts the number of retired store that experienced a cache line boundary split(Precise Event). Note that each spilt should be counted only once. EventSel=03H UMask=04H
    Counter=0,1
    CoreOnly
    RECYCLEQ.STA_FULL Counts the store micro-ops retired that were pushed in the rehad queue because the store address buffer is full EventSel=03H UMask=20H
    Counter=0,1
    CoreOnly
    RS_FULL_STALL.ALL Counts the total number of core cycles allocation pipeline is stalled when any one of the reservation stations is full. EventSel=CBH UMask=1FH
    Counter=0,1
    CoreOnly
    RS_FULL_STALL.MEC Counts the number of core cycles when allocation pipeline is stalled and is waiting for a free MEC reservation station entry. EventSel=CBH UMask=01H
    Counter=0,1
    CoreOnly
    UOPS_RETIRED.ALL This event counts the number of micro-ops (uops) retired. The processor decodes complex macro instructions into a sequence of simpler uops. Most instructions are composed of one or two uops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. EventSel=C2H UMask=10H
    Counter=0,1
    CoreOnly
    UOPS_RETIRED.MS This event counts the number of micro-ops retired that were supplied from MSROM. EventSel=C2H UMask=01H
    Counter=0,1
    CoreOnly
    UOPS_RETIRED.PACKED_SIMD The length of the packed operation (128bits, 256bits or 512bits) is not taken into account when updating the counter; all count the same (+1). Mask (k) registers are ignored. For example: a micro-op operating with a mask that only enables one element or even zero elements will still trigger this counter (+1) This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all. EventSel=C2H UMask=40H
    Counter=0,1
    CoreOnly
    UOPS_RETIRED.SCALAR_SIMD This event is defined at the micro-op level and not instruction level. Most instructions are implemented with one micro-op but not all. EventSel=C2H UMask=20H
    Counter=0,1
    CoreOnly
    UNCORE
    UNC_H_U_CLOCKTICKS Uncore Clocks EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_OCCUPANCY.IRQ Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ EventSel=11H UMask=01H
    Counter=0
    Uncore
    UNC_H_INGRESS_OCCUPANCY.IRQ_REJ Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IRQ Rejected EventSel=11H UMask=02H
    Counter=0
    Uncore
    UNC_H_INGRESS_OCCUPANCY.IPQ Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - IPQ EventSel=11H UMask=04H
    Counter=0
    Uncore
    UNC_H_INGRESS_OCCUPANCY.PRQ Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ EventSel=11H UMask=10H
    Counter=0
    Uncore
    UNC_H_INGRESS_OCCUPANCY.PRQ_REJ Ingress Occupancy. Counts number of entries in the specified Ingress queue in each cycle. - PRQ Rejected EventSel=11H UMask=20H
    Counter=0
    Uncore
    UNC_H_INGRESS_INSERTS.IRQ Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ EventSel=13H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INSERTS.IRQ_REJ Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IRQ Rejected EventSel=13H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INSERTS.IPQ Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - IPQ EventSel=13H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INSERTS.PRQ Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ EventSel=13H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INSERTS.PRQ_REJ Ingress Allocations. Counts number of allocations per cycle into the specified Ingress queue. - PRQ Rejected EventSel=13H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INT_STARVED.IRQ Cycles with the IRQ in Internal Starvation. EventSel=14H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INT_STARVED.IPQ Cycles with the IPQ in Internal Starvation. EventSel=14H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INT_STARVED.ISMQ Cycles with the ISMQ in Internal Starvation. EventSel=14H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_INT_STARVED.PRQ Ingress internal starvation cycles. Counts cycles in internal starvation. This occurs when one or more of the entries in the ingress queue are being starved out by other entries in the queue. EventSel=14H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0 Ingress Request Queue Rejects EventSel=18H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0 Ingress Request Queue Rejects EventSel=18H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0 Ingress Request Queue Rejects EventSel=18H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0 Ingress Request Queue Rejects EventSel=18H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0 Ingress Request Queue Rejects EventSel=18H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0 Ingress Request Queue Rejects EventSel=18H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI Ingress Request Queue Rejects EventSel=18H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI Ingress Request Queue Rejects EventSel=18H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0 Ingress Request Queue Rejects EventSel=19H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM Ingress Request Queue Rejects EventSel=19H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY Ingress Request Queue Rejects EventSel=19H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP Ingress Request Queue Rejects EventSel=19H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH Ingress Request Queue Rejects EventSel=19H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0 Ingress Request Queue Rejects EventSel=20H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0 Ingress Request Queue Rejects EventSel=20H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0 Ingress Request Queue Rejects EventSel=20H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0 Ingress Request Queue Rejects EventSel=20H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0 Ingress Request Queue Rejects EventSel=20H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0 Ingress Request Queue Rejects EventSel=20H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI Ingress Request Queue Rejects EventSel=20H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI Ingress Request Queue Rejects EventSel=20H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0 Ingress Request Queue Rejects EventSel=21H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM Ingress Request Queue Rejects EventSel=21H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY Ingress Request Queue Rejects EventSel=21H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP Ingress Request Queue Rejects EventSel=21H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH Ingress Request Queue Rejects EventSel=21H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0 Ingress Probe Queue Rejects EventSel=22H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI Ingress Probe Queue Rejects EventSel=22H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI Ingress Probe Queue Rejects EventSel=22H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0 Ingress Probe Queue Rejects EventSel=23H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM Ingress Probe Queue Rejects EventSel=23H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY Ingress Probe Queue Rejects EventSel=23H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP Ingress Probe Queue Rejects EventSel=23H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH Ingress Probe Queue Rejects EventSel=23H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0 ISMQ Rejects EventSel=24H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0 ISMQ Rejects EventSel=24H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0 ISMQ Rejects EventSel=24H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0 ISMQ Rejects EventSel=24H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0 ISMQ Rejects EventSel=24H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0 ISMQ Rejects EventSel=24H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI ISMQ Rejects EventSel=24H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI ISMQ Rejects EventSel=24H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2AH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0 REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2BH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2BH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2BH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH REQUESTQ"" includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) EventSel=2BH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0 ISMQ Retries EventSel=2CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0 ISMQ Retries EventSel=2CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0 ISMQ Retries EventSel=2CH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0 ISMQ Retries EventSel=2CH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0 ISMQ Retries EventSel=2CH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0 ISMQ Retries EventSel=2CH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI ISMQ Retries EventSel=2CH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI ISMQ Retries EventSel=2CH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0 Other Queue Retries EventSel=2EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0 Other Queue Retries EventSel=2EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0 Other Queue Retries EventSel=2EH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0 Other Queue Retries EventSel=2EH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0 Other Queue Retries EventSel=2EH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0 Other Queue Retries EventSel=2EH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI Other Queue Retries EventSel=2EH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI Other Queue Retries EventSel=2EH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0 Other Queue Retries EventSel=2FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM Other Queue Retries EventSel=2FH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY Other Queue Retries EventSel=2FH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP Other Queue Retries EventSel=2FH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH Other Queue Retries EventSel=2FH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_SF_LOOKUP.DATA_READ Cache Lookups. Counts the number of times the LLC was accessed. Read transactions EventSel=34H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_SF_LOOKUP.WRITE Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC. EventSel=34H UMask=05H
    Counter=0,1,2,3
    Uncore
    UNC_H_SF_LOOKUP.REMOTE_SNOOP Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ. EventSel=34H UMask=09H
    Counter=0,1,2,3
    Uncore
    UNC_H_SF_LOOKUP.ANY Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ. EventSel=34H UMask=11H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.M_STATE Cache Lookups. Counts the number of times the LLC was accessed. Read transactions EventSel=37H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.E_STATE Cache Lookups. Counts the number of times the LLC was accessed. Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC. EventSel=37H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.S_STATE Cache Lookups. Counts the number of times the LLC was accessed. Filters for only snoop requests coming from the remote socket(s) through the IPQ. EventSel=37H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.F_STATE Cache Lookups. Counts the number of times the LLC was accessed. Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ. EventSel=37H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.LOCAL Lines Victimized that Match NID EventSel=37H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_CACHE_LINES_VICTIMIZED.REMOTE Lines Victimized that Does Not Match NID EventSel=37H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.IRQ Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IRQ EventSel=35H UMask=31H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.EVICT Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -SF/LLC Evictions EventSel=35H UMask=32H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.PRQ Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -PRQ EventSel=35H UMask=34H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.IPQ Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IPQ EventSel=35H UMask=38H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.HIT Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -Hit (Not a Miss) EventSel=35H UMask=1FH
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_INSERTS.MISS Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -Miss EventSel=35H UMask=2FH
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_OCCUPANCY.IRQ For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ EventSel=36H UMask=31H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.EVICT For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -SF/LLC Evictions EventSel=36H UMask=32H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.PRQ For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ EventSel=36H UMask=34H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.IPQ For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ EventSel=36H UMask=38H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.HIT For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Hit (Not a Miss) EventSel=36H UMask=1FH
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.MISS For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -Miss EventSel=36H UMask=2FH
    Counter=0
    Uncore
    UNC_H_MISC.RSPI_WAS_FSE Miscellaneous events in the Cbo. Silent Snoop Eviction EventSel=39H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_MISC.WC_ALIASING Miscellaneous events in the Cbo. Write Combining Aliasing EventSel=39H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_MISC.RFO_HIT_S Miscellaneous events in the Cbo. RFO HitS EventSel=39H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_MISC.CV0_PREF_VIC Miscellaneous events in the Cbo. CV0 Prefetch Victim EventSel=39H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_MISC.CV0_PREF_MISS Miscellaneous events in the Cbo. CV0 Prefetch Miss EventSel=39H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.IRQ_HIT Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IRQ EventSel=35H UMask=11H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.IRQ_MISS Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IRQ EventSel=35H UMask=21H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.PRQ_HIT Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -PRQ EventSel=35H UMask=14H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.PRQ_MISS Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -PRQ EventSel=35H UMask=24H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.IPQ_HIT Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IPQ EventSel=35H UMask=18H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.IPQ_MISS Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IPQ EventSel=35H UMask=28H
    Counter=0,1,2,3
    Uncore
    UNC_C_TOR_INSERTS.LOC_ALL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent -IRQ or PRQ EventSel=35H UMask=37H
    Counter=0,1,2,3
    Uncore
    UNC_H_TOR_OCCUPANCY.IRQ_HIT For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ hit EventSel=36H UMask=11H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.IRQ_MISS For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IRQ or PRQ miss EventSel=36H UMask=21H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.PRQ_HIT For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ hit EventSel=36H UMask=14H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.PRQ_MISS For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -PRQ miss EventSel=36H UMask=24H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.IPQ_HIT For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ hit EventSel=36H UMask=18H
    Counter=0
    Uncore
    UNC_H_TOR_OCCUPANCY.IPQ_MISS For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent -IPQ miss EventSel=36H UMask=28H
    Counter=0
    Uncore
    UNC_H_CLOCK Uncore Clocks EventSel=C0H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR0 CMS Agent0 AD Credits Acquired For Transgress 0 EventSel=80H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR1 CMS Agent0 AD Credits Acquired For Transgress 1 EventSel=80H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR2 CMS Agent0 AD Credits Acquired For Transgress 2 EventSel=80H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR3 CMS Agent0 AD Credits Acquired For Transgress 3 EventSel=80H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR4 CMS Agent0 AD Credits Acquired For Transgress 4 EventSel=80H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR5 CMS Agent0 AD Credits Acquired For Transgress 5 EventSel=80H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR6 CMS Agent0 AD Credits Acquired For Transgress 6 EventSel=80H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED.TGR7 CMS Agent0 AD Credits Acquired For Transgress 7 EventSel=80H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8 CMS Agent0 AD Credits Acquired For Transgress 8 EventSel=81H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent0 AD Credits Acquired For Transgress 0-7 EventSel=81H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0 CMS Agent0 AD Credits Occupancy For Transgress 0 EventSel=82H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1 CMS Agent0 AD Credits Occupancy For Transgress 1 EventSel=82H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2 CMS Agent0 AD Credits Occupancy For Transgress 2 EventSel=82H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3 CMS Agent0 AD Credits Occupancy For Transgress 3 EventSel=82H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4 CMS Agent0 AD Credits Occupancy For Transgress 4 EventSel=82H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5 CMS Agent0 AD Credits Occupancy For Transgress 5 EventSel=82H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6 CMS Agent0 AD Credits Occupancy For Transgress 6 EventSel=82H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7 CMS Agent0 AD Credits Occupancy For Transgress 7 EventSel=82H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8 CMS Agent0 AD Credits Occupancy For Transgress 8 EventSel=83H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent0 AD Credits Occupancy For Transgress 0-7 EventSel=83H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR0 CMS Agent1 AD Credits Acquired For Transgress 0 EventSel=84H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR1 CMS Agent1 AD Credits Acquired For Transgress 1 EventSel=84H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR2 CMS Agent1 AD Credits Acquired For Transgress 2 EventSel=84H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR3 CMS Agent1 AD Credits Acquired For Transgress 3 EventSel=84H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR4 CMS Agent1 AD Credits Acquired For Transgress 4 EventSel=84H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR5 CMS Agent1 AD Credits Acquired For Transgress 5 EventSel=84H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR6 CMS Agent1 AD Credits Acquired For Transgress 6 EventSel=84H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED.TGR7 CMS Agent1 AD Credits Acquired For Transgress 7 EventSel=84H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8 CMS Agent1 AD Credits Acquired For Transgress 8 EventSel=85H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent1 AD Credits Acquired For Transgress 0-7 EventSel=85H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0 CMS Agent1 AD Credits Occupancy For Transgress 0 EventSel=86H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1 CMS Agent1 AD Credits Occupancy For Transgress 1 EventSel=86H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2 CMS Agent1 AD Credits Occupancy For Transgress 2 EventSel=86H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3 CMS Agent1 AD Credits Occupancy For Transgress 3 EventSel=86H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4 CMS Agent1 AD Credits Occupancy For Transgress 4 EventSel=86H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5 CMS Agent1 AD Credits Occupancy For Transgress 5 EventSel=86H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6 CMS Agent1 AD Credits Occupancy For Transgress 6 EventSel=86H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7 CMS Agent1 AD Credits Occupancy For Transgress 7 EventSel=86H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8 CMS Agent1 AD Credits Occupancy For Transgress 8 EventSel=87H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent1 AD Credits Occupancy For Transgress 0-7 EventSel=87H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR0 CMS Agent0 BL Credits Acquired For Transgress 0 EventSel=88H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR1 CMS Agent0 BL Credits Acquired For Transgress 1 EventSel=88H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR2 CMS Agent0 BL Credits Acquired For Transgress 2 EventSel=88H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR3 CMS Agent0 BL Credits Acquired For Transgress 3 EventSel=88H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR4 CMS Agent0 BL Credits Acquired For Transgress 4 EventSel=88H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR5 CMS Agent0 BL Credits Acquired For Transgress 5 EventSel=88H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR6 CMS Agent0 BL Credits Acquired For Transgress 6 EventSel=88H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED.TGR7 CMS Agent0 BL Credits Acquired For Transgress 7 EventSel=88H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8 CMS Agent0 BL Credits Acquired For Transgress 8 EventSel=89H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent0 BL Credits Acquired For Transgress 0-7 EventSel=89H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0 CMS Agent0 BL Credits Occupancy For Transgress 0 EventSel=8AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1 CMS Agent0 BL Credits Occupancy For Transgress 1 EventSel=8AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2 CMS Agent0 BL Credits Occupancy For Transgress 2 EventSel=8AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3 CMS Agent0 BL Credits Occupancy For Transgress 3 EventSel=8AH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4 CMS Agent0 BL Credits Occupancy For Transgress 4 EventSel=8AH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5 CMS Agent0 BL Credits Occupancy For Transgress 5 EventSel=8AH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6 CMS Agent0 BL Credits Occupancy For Transgress 6 EventSel=8AH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7 CMS Agent0 BL Credits Occupancy For Transgress 7 EventSel=8AH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8 CMS Agent0 BL Credits Occupancy For Transgress 8 EventSel=8BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent0 BL Credits Occupancy For Transgress 0-7 EventSel=8BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR0 CMS Agent1 BL Credits Acquired For Transgress 0 EventSel=8CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR1 CMS Agent1 BL Credits Acquired For Transgress 1 EventSel=8CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR2 CMS Agent1 BL Credits Acquired For Transgress 2 EventSel=8CH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR3 CMS Agent1 BL Credits Acquired For Transgress 3 EventSel=8CH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR4 CMS Agent1 BL Credits Acquired For Transgress 4 EventSel=8CH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR5 CMS Agent1 BL Credits Acquired For Transgress 5 EventSel=8CH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR6 CMS Agent1 BL Credits Acquired For Transgress 6 EventSel=8CH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED.TGR7 CMS Agent1 BL Credits Acquired For Transgress 7 EventSel=8CH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8 CMS Agent1 BL Credits Acquired For Transgress 8 EventSel=8DH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent1 BL Credits Acquired For Transgress 0-7 EventSel=8DH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0 CMS Agent1 BL Credits Occupancy For Transgress 0 EventSel=8EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1 CMS Agent1 BL Credits Occupancy For Transgress 1 EventSel=8EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2 CMS Agent1 BL Credits Occupancy For Transgress 2 EventSel=8EH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3 CMS Agent1 BL Credits Occupancy For Transgress 3 EventSel=8EH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4 CMS Agent1 BL Credits Occupancy For Transgress 4 EventSel=8EH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5 CMS Agent1 BL Credits Occupancy For Transgress 5 EventSel=8EH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6 CMS Agent1 BL Credits Occupancy For Transgress 6 EventSel=8EH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7 CMS Agent1 BL Credits Occupancy For Transgress 7 EventSel=8EH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8 CMS Agent1 BL Credits Occupancy For Transgress 8 EventSel=8FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7 CMS Agent1 BL Credits Occupancy For Transgress 0-7 EventSel=8FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0 Stall on No AD Transgress Credits For Transgress 0 EventSel=D0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1 Stall on No AD Transgress Credits For Transgress 1 EventSel=D0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2 Stall on No AD Transgress Credits For Transgress 2 EventSel=D0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3 Stall on No AD Transgress Credits For Transgress 3 EventSel=D0H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4 Stall on No AD Transgress Credits For Transgress 4 EventSel=D0H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5 Stall on No AD Transgress Credits For Transgress 5 EventSel=D0H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6 Stall on No AD Transgress Credits For Transgress 6 EventSel=D0H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7 Stall on No AD Transgress Credits For Transgress 7 EventSel=D0H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8 Stall on No AD Transgress Credits For Transgress 8 EventSel=D1H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7 Stall on No AD Transgress Credits For Transgress 0-7 EventSel=D1H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0 Stall on No AD Transgress Credits For Transgress 0 EventSel=D2H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1 Stall on No AD Transgress Credits For Transgress 1 EventSel=D2H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2 Stall on No AD Transgress Credits For Transgress 2 EventSel=D2H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3 Stall on No AD Transgress Credits For Transgress 3 EventSel=D2H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4 Stall on No AD Transgress Credits For Transgress 4 EventSel=D2H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5 Stall on No AD Transgress Credits For Transgress 5 EventSel=D2H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6 Stall on No AD Transgress Credits For Transgress 6 EventSel=D2H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7 Stall on No AD Transgress Credits For Transgress 7 EventSel=D2H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8 Stall on No AD Transgress Credits For Transgress 8 EventSel=D3H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR0_THRU_TGR7 Stall on No AD Transgress Credits For Transgress 0-7 EventSel=D3H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0 Stall on No AD Transgress Credits For Transgress 0 EventSel=D4H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1 Stall on No AD Transgress Credits For Transgress 1 EventSel=D4H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2 Stall on No AD Transgress Credits For Transgress 2 EventSel=D4H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3 Stall on No AD Transgress Credits For Transgress 3 EventSel=D4H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4 Stall on No AD Transgress Credits For Transgress 4 EventSel=D4H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5 Stall on No AD Transgress Credits For Transgress 5 EventSel=D4H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6 Stall on No AD Transgress Credits For Transgress 6 EventSel=D4H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7 Stall on No AD Transgress Credits For Transgress 7 EventSel=D4H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8 Stall on No AD Transgress Credits For Transgress 8 EventSel=D5H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7 Stall on No AD Transgress Credits For Transgress 0-7 EventSel=D5H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0 Stall on No AD Transgress Credits For Transgress 0 EventSel=D6H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1 Stall on No AD Transgress Credits For Transgress 1 EventSel=D6H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2 Stall on No AD Transgress Credits For Transgress 2 EventSel=D6H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3 Stall on No AD Transgress Credits For Transgress 3 EventSel=D6H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4 Stall on No AD Transgress Credits For Transgress 4 EventSel=D6H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5 Stall on No AD Transgress Credits For Transgress 5 EventSel=D6H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6 Stall on No AD Transgress Credits For Transgress 6 EventSel=D6H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7 Stall on No AD Transgress Credits For Transgress 7 EventSel=D6H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8 Stall on No AD Transgress Credits For Transgress 8 EventSel=D7H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR0_THRU_TGR7 Stall on No AD Transgress Credits For Transgress 0-7 EventSel=D7H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0 CMS Vert Egress Occupancy AD - Agent 0 EventSel=90H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0 CMS Vert Egress Occupancy AK - Agent 0 EventSel=90H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0 CMS Vert Egress Occupancy BL - Agent 0 EventSel=90H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0 CMS Vert Egress Occupancy IV - Agent 0 EventSel=90H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1 CMS Vert Egress Occupancy AD - Agent 1 EventSel=90H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1 CMS Vert Egress Occupancy AK - Agent 1 EventSel=90H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1 CMS Vert Egress Occupancy BL - Agent 1 EventSel=90H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.AD_AG0 CMS Vert Egress Allocations AD - Agent 0 EventSel=91H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.AK_AG0 CMS Vert Egress Allocations AK - Agent 0 EventSel=91H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.BL_AG0 CMS Vert Egress Allocations BL - Agent 0 EventSel=91H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.IV_AG0 CMS Vert Egress Allocations IV - Agent 0 EventSel=91H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.AD_AG1 CMS Vert Egress Allocations AD - Agent 1 EventSel=91H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.AK_AG1 CMS Vert Egress Allocations AK - Agent 1 EventSel=91H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_INSERTS.BL_AG1 CMS Vert Egress Allocations BL - Agent 1 EventSel=91H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0 Cycles CMS Vertical Egress Queue Is Full AD - Agent 0 EventSel=92H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0 Cycles CMS Vertical Egress Queue Is Full AK - Agent 0 EventSel=92H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0 Cycles CMS Vertical Egress Queue Is Full BL - Agent 0 EventSel=92H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0 Cycles CMS Vertical Egress Queue Is Full IV - Agent 0 EventSel=92H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1 Cycles CMS Vertical Egress Queue Is Full AD - Agent 1 EventSel=92H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1 Cycles CMS Vertical Egress Queue Is Full AK - Agent 1 EventSel=92H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1 Cycles CMS Vertical Egress Queue Is Full BL - Agent 1 EventSel=92H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0 Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 0 EventSel=93H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0 Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 0 EventSel=93H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0 Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 0 EventSel=93H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0 Cycles CMS Vertical Egress Queue Is Not Empty IV - Agent 0 EventSel=93H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1 Cycles CMS Vertical Egress Queue Is Not Empty AD - Agent 1 EventSel=93H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1 Cycles CMS Vertical Egress Queue Is Not Empty AK - Agent 1 EventSel=93H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1 Cycles CMS Vertical Egress Queue Is Not Empty BL - Agent 1 EventSel=93H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.AD_AG0 CMS Vertical Egress NACKs EventSel=98H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.AK_AG0 CMS Vertical Egress NACKs Onto AK Ring EventSel=98H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.BL_AG0 CMS Vertical Egress NACKs Onto BL Ring EventSel=98H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.IV_AG0 CMS Vertical Egress NACKs EventSel=98H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.AD_AG1 CMS Vertical Egress NACKs EventSel=98H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.AK_AG1 CMS Vertical Egress NACKs EventSel=98H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_NACK.BL_AG1 CMS Vertical Egress NACKs EventSel=98H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.AD_AG0 CMS Vertical Egress Injection Starvation EventSel=9AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.AK_AG0 CMS Vertical Egress Injection Starvation Onto AK Ring EventSel=9AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.BL_AG0 CMS Vertical Egress Injection Starvation Onto BL Ring EventSel=9AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.IV_AG0 CMS Vertical Egress Injection Starvation EventSel=9AH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.AD_AG1 CMS Vertical Egress Injection Starvation EventSel=9AH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.AK_AG1 CMS Vertical Egress Injection Starvation EventSel=9AH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_STARVED.BL_AG1 CMS Vertical Egress Injection Starvation EventSel=9AH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.AD_AG0 CMS Vertical ADS Used EventSel=9CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.AK_AG0 CMS Vertical ADS Used EventSel=9CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.BL_AG0 CMS Vertical ADS Used EventSel=9CH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.AD_AG1 CMS Vertical ADS Used EventSel=9CH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.AK_AG1 CMS Vertical ADS Used EventSel=9CH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_ADS_USED.BL_AG1 CMS Vertical ADS Used EventSel=9CH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.AD_AG0 CMS Vertical Egress Bypass. AD ring agent 0 EventSel=9EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.AK_AG0 CMS Vertical Egress Bypass. AK ring agent 0 EventSel=9EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.BL_AG0 CMS Vertical Egress Bypass. BL ring agent 0 EventSel=9EH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.IV CMS Vertical Egress Bypass. IV ring agent 0 EventSel=9EH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.AD_AG1 CMS Vertical Egress Bypass. AD ring agent 1 EventSel=9EH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.AK_AG1 CMS Vertical Egress Bypass. AK ring agent 1 EventSel=9EH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_VERT_BYPASS.BL_AG1 CMS Vertical Egress Bypass. BL ring agent 1 EventSel=9EH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_OCCUPANCY.AD CMS Horizontal Egress Occupancy AD EventSel=94H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_OCCUPANCY.AK CMS Horizontal Egress Occupancy AK EventSel=94H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_OCCUPANCY.BL CMS Horizontal Egress Occupancy BL EventSel=94H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_OCCUPANCY.IV CMS Horizontal Egress Occupancy IV EventSel=94H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_INSERTS.AD CMS Horizontal Egress Inserts AD EventSel=95H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_INSERTS.AK CMS Horizontal Egress Inserts AK EventSel=95H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_INSERTS.BL CMS Horizontal Egress Inserts BL EventSel=95H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_INSERTS.IV CMS Horizontal Egress Inserts IV EventSel=95H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_FULL.AD Cycles CMS Horizontal Egress Queue is Full AD EventSel=96H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_FULL.AK Cycles CMS Horizontal Egress Queue is Full AK EventSel=96H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_FULL.BL Cycles CMS Horizontal Egress Queue is Full BL EventSel=96H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_FULL.IV Cycles CMS Horizontal Egress Queue is Full IV EventSel=96H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_NE.AD Cycles CMS Horizontal Egress Queue is Not Empty AD EventSel=97H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_NE.AK Cycles CMS Horizontal Egress Queue is Not Empty AK EventSel=97H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_NE.BL Cycles CMS Horizontal Egress Queue is Not Empty BL EventSel=97H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_CYCLES_NE.IV Cycles CMS Horizontal Egress Queue is Not Empty IV EventSel=97H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_NACK.AD CMS Horizontal Egress NACKs EventSel=99H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_NACK.AK CMS Horizontal Egress NACKs EventSel=99H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_NACK.BL CMS Horizontal Egress NACKs EventSel=99H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_NACK.IV CMS Horizontal Egress NACKs EventSel=99H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_STARVED.AD CMS Horizontal Egress Injection Starvation EventSel=9BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_STARVED.AK CMS Horizontal Egress Injection Starvation EventSel=9BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_STARVED.BL CMS Horizontal Egress Injection Starvation EventSel=9BH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_STARVED.IV CMS Horizontal Egress Injection Starvation EventSel=9BH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_ADS_USED.AD CMS Horizontal ADS Used EventSel=9DH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_ADS_USED.AK CMS Horizontal ADS Used EventSel=9DH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_ADS_USED.BL CMS Horizontal ADS Used EventSel=9DH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_BYPASS.AD CMS Horizontal Egress Bypass. AD ring EventSel=9FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_BYPASS.AK CMS Horizontal Egress Bypass. AK ring EventSel=9FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_BYPASS.BL CMS Horizontal Egress Bypass. BL ring EventSel=9FH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_HORZ_BYPASS.IV CMS Horizontal Egress Bypass. IV ring EventSel=9FH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_VERT.AD Number of incoming messages from the Vertical ring that were bounced, by ring type. EventSel=A0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_VERT.AK Number of incoming messages from the Vertical ring that were bounced, by ring type - Acknowledgements to core EventSel=A0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_VERT.BL Number of incoming messages from the Vertical ring that were bounced, by ring type - Data Responses to core. EventSel=A0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_VERT.IV Number of incoming messages from the Vertical ring that were bounced, by ring type - Snoops of processor's cache. EventSel=A0H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_HORZ.AD Number of incoming messages from the Horizontal ring that were bounced, by ring type. EventSel=A1H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_HORZ.AK Number of incoming messages from the Horizontal ring that were bounced, by ring type - Acknowledgements to core EventSel=A1H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_HORZ.BL Number of incoming messages from the Horizontal ring that were bounced, by ring type - Data Responses to core. EventSel=A1H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BOUNCES_HORZ.IV Number of incoming messages from the Horizontal ring that were bounced, by ring type - Snoops of processor's cache. EventSel=A1H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_VERT.AD Vertical ring sink starvation count - AD ring EventSel=A2H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_VERT.AK Vertical ring sink starvation count - AK ring EventSel=A2H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_VERT.BL Vertical ring sink starvation count - BL ring EventSel=A2H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_VERT.IV Vertical ring sink starvation count - IV ring EventSel=A2H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_HORZ.AD Horizontal ring sink starvation count - AD ring EventSel=A3H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_HORZ.AK Horizontal ring sink starvation count - AK ring EventSel=A3H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_HORZ.BL Horizontal ring sink starvation count - BL ring EventSel=A3H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SINK_STARVED_HORZ.IV Horizontal ring sink starvation count - IV ring EventSel=A3H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_SRC_THRTL Counts cycles in throttle mode. EventSel=A4H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_FAST_ASSERTED.VERT Counts cycles source throttling is adderted - vertical EventSel=A5H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_FAST_ASSERTED.HORZ Counts cycles source throttling is adderted - horizontal EventSel=A5H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AD_IN_USE.UP_EVEN Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Even EventSel=A6H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AD_IN_USE.UP_ODD Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Up and Odd EventSel=A6H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AD_IN_USE.DN_EVEN Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Even EventSel=A6H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AD_IN_USE.DN_ODD Counts the number of cycles that the Vertical AD ring is being used at this ring stop - Down and Odd EventSel=A6H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Even EventSel=A7H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Left and Odd EventSel=A7H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Even EventSel=A7H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD Counts the number of cycles that the Horizontal AD ring is being used at this ring stop - Right and Odd EventSel=A7H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AK_IN_USE.UP_EVEN Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Even EventSel=A8H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AK_IN_USE.UP_ODD Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Up and Odd EventSel=A8H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AK_IN_USE.DN_EVEN Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Even EventSel=A8H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_AK_IN_USE.DN_ODD Counts the number of cycles that the Vertical AK ring is being used at this ring stop - Down and Odd EventSel=A8H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Even EventSel=A9H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Left and Odd EventSel=A9H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Even EventSel=A9H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD Counts the number of cycles that the Horizontal AK ring is being used at this ring stop - Right and Odd EventSel=A9H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_BL_IN_USE.UP_EVEN Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Even EventSel=AAH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_BL_IN_USE.UP_ODD Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Up and Odd EventSel=AAH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_BL_IN_USE.DN_EVEN Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Even EventSel=AAH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_BL_IN_USE.DN_ODD Counts the number of cycles that the Vertical BL ring is being used at this ring stop - Down and Odd EventSel=AAH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Even EventSel=ABH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Left and Odd EventSel=ABH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Even EventSel=ABH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD Counts the number of cycles that the Horizontal BL ring is being used at this ring stop - Right and Odd EventSel=ABH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_IV_IN_USE.UP Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Up EventSel=ACH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_VERT_RING_IV_IN_USE.DN Counts the number of cycles that the Vertical IV ring is being used at this ring stop - Down EventSel=ACH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_IV_IN_USE.LEFT Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Left EventSel=ADH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_HORZ_RING_IV_IN_USE.RIGHT Counts the number of cycles that the Horizontal IV ring is being used at this ring stop - Right EventSel=ADH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements EventSel=AEH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements EventSel=AEH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD Transgress Ingress Occupancy. Occupancy event for the Ingress buffers in the CMS The Ingress is used to queue up requests received from the mesh EventSel=B0H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.AD_BNC Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.AK_BNC Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.BL_BNC Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.IV_BNC Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.AD_CRD Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_INSERTS.BL_CRD Transgress Ingress Allocations. Number of allocations into the CMS Ingress The Ingress is used to queue up requests received from the mesh EventSel=B1H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.AD_BNC Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.AK_BNC Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.BL_BNC Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.IV_BNC Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.AD_CRD Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BYPASS.BL_CRD Transgress Ingress Bypass. Number of packets bypassing the CMS Ingress . EventSel=B2H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_CRD_STARVED.IFV Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, the Ingress is unable to forward to the Egress due to a lack of credit. EventSel=B3H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority EventSel=B4H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority EventSel=B4H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority EventSel=B4H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD Transgress Injection Starvation. Counts cycles under injection starvation mode. This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time. In this case, because a message from the other queue has higher priority EventSel=B4H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_E_E_CLOCKTICKS ECLK count EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_E_RPQ_INSERTS Counts the number of read requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all read requests as well as streaming stores that hit or miss in the MCDRAM cache. EventSel=01H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_E_WPQ_INSERTS Counts the number of write requests received by the MCDRAM controller. This event is valid in all three memory modes: flat, cache and hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, read requests that miss in MCDRAM cache. EventSel=02H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_E_U_CLOCKTICKS UCLK count EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_E_EDC_ACCESS.HIT_CLEAN Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode. EventSel=02H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_E_EDC_ACCESS.HIT_DIRTY Counts the number of read requests and streaming stores that hit in MCDRAM cache and the data in MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode. EventSel=02H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_E_EDC_ACCESS.MISS_CLEAN Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is clean with respect to DDR. This event is only valid in cache and hybrid memory mode. EventSel=02H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_E_EDC_ACCESS.MISS_DIRTY Counts the number of read requests and streaming stores that miss in MCDRAM cache and the data evicted from the MCDRAM is dirty with respect to DDR. This event is only valid in cache and hybrid memory mode. EventSel=02H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_E_EDC_ACCESS.MISS_INVALID Number of EDC Hits or Misses. Miss I EventSel=02H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_D_CLOCKTICKS DCLK count EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD CAS Reads EventSel=03H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.WR CAS Writes EventSel=03H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.ALL CAS All EventSel=03H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_M_U_CLOCKTICKS UCLK count EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_IDI EventSel=10H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCB EventSel=10H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.CBO_NCS EventSel=10H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_INGRESS_CYCLES_NE.ALL Ingress Queue Cycles Not Empty. Counts the number of cycles when the M2PCIe Ingress is not empty.ALL EventSel=10H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.AD_0 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_0 EventSel=23H UMask=01H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.AK_0 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_0 EventSel=23H UMask=02H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.BL_0 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_0 EventSel=23H UMask=04H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.AD_1 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AD_1 EventSel=23H UMask=08H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.AK_1 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. AK_1 EventSel=23H UMask=10H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_CYCLES_NE.BL_1 Egress (to CMS) Cycles Not Empty. Counts the number of cycles when the M2PCIe Egress is not empty. BL_1 EventSel=23H UMask=20H
    Counter=0,1
    Uncore
    UNC_M2P_EGRESS_INSERTS.AD_0 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_0 EventSel=24H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.AK_0 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_0 EventSel=24H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.BL_0 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_0 EventSel=24H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.AK_CRD_0 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0 EventSel=24H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.AD_1 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AD_1 EventSel=24H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.AK_1 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_1 EventSel=24H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.BL_1 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. BL_1 EventSel=24H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_INSERTS.AK_CRD_1 Egress (to CMS) Ingress. Counts the number of number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1 EventSel=24H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.AD_0 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_0 EventSel=25H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.AK_0 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_0 EventSel=25H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.BL_0 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_0 EventSel=25H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.AD_1 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AD_1 EventSel=25H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.AK_1 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. AK_1 EventSel=25H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M2P_EGRESS_CYCLES_FULL.BL_1 Egress (to CMS) Cycles Full. Counts the number of cycles when the M2PCIe Egress is full. BL_1 EventSel=25H UMask=20H
    Counter=0,1,2,3
    Uncore
    OFFCORE
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=OUTSTANDING Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_FAR_TILE_M Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_FAR_TILE_E_F Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_NEAR_TILE_M Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_NEAR_TILE_E_F Counts any Prefetch requestsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=MCDRAM_FAR Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=MCDRAM_NEAR Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=DDR_FAR Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=DDR_NEAR Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800060H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=ANY_RESPONSE Counts any Prefetch requestshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10060H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=OUTSTANDING Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=40000032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_FAR_TILE_M Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_FAR_TILE_E_F Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8004032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_NEAR_TILE_M Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000832E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_NEAR_TILE_E_F Counts any Read requestaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000832E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=MCDRAM_FAR Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1004032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=MCDRAM_NEAR Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=DDR_FAR Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1010032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=DDR_NEAR Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=808032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=ANY_RESPONSE Counts any Read requesthave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=132E7H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=OUTSTANDING Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_FAR_TILE_M Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_FAR_TILE_E_F Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_NEAR_TILE_M Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_NEAR_TILE_E_F Counts Demand code reads and prefetch code read requestsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=MCDRAM_FAR Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=MCDRAM_NEAR Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=DDR_FAR Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=DDR_NEAR Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800044H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=ANY_RESPONSE Counts Demand code reads and prefetch code read requestshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10044H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=OUTSTANDING Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_FAR_TILE_M Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_FAR_TILE_E_F Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_NEAR_TILE_M Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_NEAR_TILE_E_F Counts Demand cacheable data write requestsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=MCDRAM_FAR Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=MCDRAM_NEAR Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=DDR_FAR Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=DDR_NEAR Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800022H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=ANY_RESPONSE Counts Demand cacheable data write requestshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10022H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=OUTSTANDING Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000003081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_FAR_TILE_M Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000403081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_FAR_TILE_E_F Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800403081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_NEAR_TILE_M Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000083081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_NEAR_TILE_E_F Counts Demand cacheable data and L1 prefetch data read requestsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800083081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=MCDRAM_FAR Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100403081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=MCDRAM_NEAR Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80203081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=DDR_FAR Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101003081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=DDR_NEAR Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80803081H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=ANY_RESPONSE Counts Demand cacheable data and L1 prefetch data read requestshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=13081H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=OUTSTANDING Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000008000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_FAR_TILE_M Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000408000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_FAR_TILE_E_F Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800408000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_NEAR_TILE_M Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000088000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_NEAR_TILE_E_F Counts any requestaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800088000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=MCDRAM_FAR Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100408000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=MCDRAM_NEAR Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80208000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=DDR_FAR Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101008000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=DDR_NEAR Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80808000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=ANY_RESPONSE Counts any requesthave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H Offcore
    OFFCORE_RESPONSE:request=STREAMING_STORES: response=ANY_RESPONSE Counts all streaming stores (WC and should be programmed on PMC1)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=14800H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_STREAMING_STORES: response=ANY_RESPONSE Counts Partial streaming stores (WC and should be programmed on PMC1)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=14000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=OUTSTANDING Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000002000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_FAR_TILE_M Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000402000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_FAR_TILE_E_F Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800402000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_NEAR_TILE_M Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000082000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_NEAR_TILE_E_F Counts L1 data HW prefetchesaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800082000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=MCDRAM_FAR Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100402000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=MCDRAM_NEAR Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80202000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=DDR_FAR Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101002000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=DDR_NEAR Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80802000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=ANY_RESPONSE Counts L1 data HW prefetcheshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=12000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=OUTSTANDING Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000001000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_FAR_TILE_M Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000401000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_FAR_TILE_E_F Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800401000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_NEAR_TILE_M Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000081000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_NEAR_TILE_E_F Counts Software Prefetchesaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800081000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=MCDRAM_FAR Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100401000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=MCDRAM_NEAR Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80201000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=DDR_FAR Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101001000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=DDR_NEAR Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80801000H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=ANY_RESPONSE Counts Software Prefetcheshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=11000H Offcore
    OFFCORE_RESPONSE:request=FULL_STREAMING_STORES: response=ANY_RESPONSE Counts Full streaming stores (WC and should be programmed on PMC1)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=10800H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=OUTSTANDING Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_FAR_TILE_M Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_FAR_TILE_E_F Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_NEAR_TILE_M Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_NEAR_TILE_E_F Counts Bus locks and split lock requestsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=MCDRAM_FAR Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=MCDRAM_NEAR Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=DDR_FAR Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=DDR_NEAR Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800400H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=ANY_RESPONSE Counts Bus locks and split lock requestshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10400H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=OUTSTANDING Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_FAR_TILE_M Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_FAR_TILE_E_F Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_NEAR_TILE_M Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_NEAR_TILE_E_F Counts UC code reads (valid only for Outstanding response type)accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=MCDRAM_FAR Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=MCDRAM_NEAR Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=DDR_FAR Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=DDR_NEAR Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800200H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=ANY_RESPONSE Counts UC code reads (valid only for Outstanding response type)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10200H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_FAR_TILE_M Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=1000400100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_FAR_TILE_E_F Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=800400100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_NEAR_TILE_M Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=1000080100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_NEAR_TILE_E_F Counts Partial writes (UC or WT or WP and should be programmed on PMC1)accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=800080100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=MCDRAM_FAR Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=100400100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=MCDRAM_NEAR Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=80200100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=DDR_FAR Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=101000100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=DDR_NEAR Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=80800100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=ANY_RESPONSE Counts Partial writes (UC or WT or WP and should be programmed on PMC1)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=10100H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=OUTSTANDING Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=NON_DRAM Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_FAR_TILE_M Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_FAR_TILE_E_F Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_NEAR_TILE_M Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_NEAR_TILE_E_F Counts Partial reads (UC or WC and is valid only for Outstanding response type).accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=MCDRAM_FAR Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=MCDRAM_NEAR Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=DDR_FAR Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=DDR_NEAR Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=ANY_RESPONSE Counts Partial reads (UC or WC and is valid only for Outstanding response type).have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10080H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=OUTSTANDING Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_FAR_TILE_M Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_FAR_TILE_E_F Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_NEAR_TILE_M Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_NEAR_TILE_E_F Counts L2 code HW prefetchesaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=MCDRAM_FAR Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=MCDRAM_NEAR Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=DDR_FAR Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=DDR_NEAR Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=ANY_RESPONSE Counts L2 code HW prefetcheshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10040H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=NON_DRAM Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_FAR_TILE_M Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_FAR_TILE_E_F Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_NEAR_TILE_M Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_NEAR_TILE_E_F Counts L2 data RFO prefetches (includes PREFETCHW instruction)accounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=MCDRAM_FAR Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=MCDRAM_NEAR Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=DDR_FAR Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=DDR_NEAR Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=20020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=ANY_RESPONSE Counts L2 data RFO prefetches (includes PREFETCHW instruction)have any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=OUTSTANDING Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_FAR_TILE_M Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_FAR_TILE_E_F Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_NEAR_TILE_M Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_NEAR_TILE_E_F Counts demand code reads and prefetch code readsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=MCDRAM_FAR Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=MCDRAM_NEAR Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=DDR_FAR Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=DDR_NEAR Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=ANY_RESPONSE Counts demand code reads and prefetch code readshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=OUTSTANDING Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_FAR_TILE_M Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_FAR_TILE_E_F Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_NEAR_TILE_M Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_NEAR_TILE_E_F Counts Demand cacheable data writesaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=MCDRAM_FAR Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=MCDRAM_NEAR Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=DDR_FAR Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=DDR_NEAR Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=ANY_RESPONSE Counts Demand cacheable data writeshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=OUTSTANDING Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=4000000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_FAR_TILE_M Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000400001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_FAR_TILE_E_F Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800400001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_NEAR_TILE_M Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000080001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_NEAR_TILE_E_F Counts demand cacheable data and L1 prefetch data readsaccounts for responses from a snoop request hit with data forwarded from its Near-other tile's L2 in E/F state. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800080001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=MCDRAM_FAR Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100400001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=MCDRAM_NEAR Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80200001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=DDR_FAR Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=DDR_NEAR Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80800001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=ANY_RESPONSE Counts demand cacheable data and L1 prefetch data readshave any response type. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=MCDRAM Counts demand cacheable data and L1 prefetch data readsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=MCDRAM Counts Demand cacheable data writesaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=MCDRAM Counts demand code reads and prefetch code readsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=MCDRAM Counts L2 data RFO prefetches (includes PREFETCHW instruction)accounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600020H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=MCDRAM Counts Partial reads (UC or WC and is valid only for Outstanding response type).accounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=MCDRAM Counts Partial writes (UC or WT or WP and should be programmed on PMC1)accounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=180600100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=MCDRAM Counts UC code reads (valid only for Outstanding response type)accounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=MCDRAM Counts Bus locks and split lock requestsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=MCDRAM Counts Software Prefetchesaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180601000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=MCDRAM Counts any requestaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180608000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=MCDRAM Counts Demand cacheable data and L1 prefetch data read requestsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180603081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=MCDRAM Counts Demand cacheable data write requestsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=MCDRAM Counts Demand code reads and prefetch code read requestsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=MCDRAM Counts any Read requestaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1806032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=MCDRAM Counts any Prefetch requestsaccounts for responses from MCDRAM (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=180600060H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=DDR Counts demand cacheable data and L1 prefetch data readsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=DDR Counts Demand cacheable data writesaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=DDR Counts demand code reads and prefetch code readsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=DDR Counts L2 data RFO prefetches (includes PREFETCHW instruction)accounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=DDR Counts L2 code HW prefetchesaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800040H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=DDR Counts Partial reads (UC or WC and is valid only for Outstanding response type).accounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800080H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=DDR Counts UC code reads (valid only for Outstanding response type)accounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=DDR Counts Bus locks and split lock requestsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=DDR Counts Software Prefetchesaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181801000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=DDR Counts L1 data HW prefetchesaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181802000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=DDR Counts any requestaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181808000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=DDR Counts Demand cacheable data and L1 prefetch data read requestsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181803081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=DDR Counts Demand cacheable data write requestsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=DDR Counts Demand code reads and prefetch code read requestsaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=181800044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=DDR Counts any Read requestaccounts for responses from DDR (local and far) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1818032E7H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_THIS_TILE_M Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_THIS_TILE_M Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_THIS_TILE_M Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_THIS_TILE_M Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_THIS_TILE_M Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_THIS_TILE_M Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=2000100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_THIS_TILE_M Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_THIS_TILE_M Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_THIS_TILE_M Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2001000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_THIS_TILE_M Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_THIS_TILE_M Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2008000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_THIS_TILE_M Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_THIS_TILE_M Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_THIS_TILE_M Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_THIS_TILE_M Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=20032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_THIS_TILE_M Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000060H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_THIS_TILE_E Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_THIS_TILE_E Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_THIS_TILE_E Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_THIS_TILE_E Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_THIS_TILE_E Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000040H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_THIS_TILE_E Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_THIS_TILE_E Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=4000100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_THIS_TILE_E Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_THIS_TILE_E Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_THIS_TILE_E Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4001000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_THIS_TILE_E Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4002000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_THIS_TILE_E Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4008000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_THIS_TILE_E Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_THIS_TILE_E Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_THIS_TILE_E Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_THIS_TILE_E Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=40032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_THIS_TILE_E Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4000060H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_THIS_TILE_S Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_THIS_TILE_S Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_THIS_TILE_S Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_THIS_TILE_S Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000020H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_THIS_TILE_S Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_THIS_TILE_S Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=8000100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_THIS_TILE_S Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_THIS_TILE_S Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_THIS_TILE_S Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8001000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_THIS_TILE_S Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8002000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_THIS_TILE_S Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8008000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_THIS_TILE_S Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_THIS_TILE_S Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_THIS_TILE_S Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8000044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_THIS_TILE_S Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=80032E7H Offcore
    OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L2_HIT_THIS_TILE_F Counts demand cacheable data and L1 prefetch data reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000001H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_THIS_TILE_F Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_THIS_TILE_F Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_THIS_TILE_F Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_THIS_TILE_F Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000040H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_THIS_TILE_F Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_THIS_TILE_F Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=10000100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_THIS_TILE_F Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_THIS_TILE_F Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_THIS_TILE_F Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_THIS_TILE_F Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_THIS_TILE_F Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10008000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_THIS_TILE_F Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_THIS_TILE_F Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_THIS_TILE_F Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_THIS_TILE_F Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_THIS_TILE_F Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10000060H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_NEAR_TILE Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_NEAR_TILE Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_RFO: response=L2_HIT_NEAR_TILE Counts L2 data RFO prefetches (includes PREFETCHW instruction) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180020H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_NEAR_TILE Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180040H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_NEAR_TILE Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_NEAR_TILE Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=1800180100H Offcore
    OFFCORE_RESPONSE:request=UC_CODE_READS: response=L2_HIT_NEAR_TILE Counts UC code reads (valid only for Outstanding response type) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180200H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_NEAR_TILE Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_NEAR_TILE Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800181000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_NEAR_TILE Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800182000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_NEAR_TILE Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800188000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_NEAR_TILE Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800183081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_NEAR_TILE Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_NEAR_TILE Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_NEAR_TILE Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18001832E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_NEAR_TILE Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800180060H Offcore
    OFFCORE_RESPONSE:request=DEMAND_RFO: response=L2_HIT_FAR_TILE Counts Demand cacheable data writes EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400002H Offcore
    OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L2_HIT_FAR_TILE Counts demand code reads and prefetch code reads EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400004H Offcore
    OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L2_HIT_FAR_TILE Counts L2 code HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400040H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_READS: response=L2_HIT_FAR_TILE Counts Partial reads (UC or WC and is valid only for Outstanding response type). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400080H Offcore
    OFFCORE_RESPONSE:request=PARTIAL_WRITES: response=L2_HIT_FAR_TILE Counts Partial writes (UC or WT or WP and should be programmed on PMC1) EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A7H)=1800400100H Offcore
    OFFCORE_RESPONSE:request=BUS_LOCKS: response=L2_HIT_FAR_TILE Counts Bus locks and split lock requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400400H Offcore
    OFFCORE_RESPONSE:request=PF_SOFTWARE: response=L2_HIT_FAR_TILE Counts Software Prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800401000H Offcore
    OFFCORE_RESPONSE:request=PF_L1_DATA_RD: response=L2_HIT_FAR_TILE Counts L1 data HW prefetches EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800402000H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_HIT_FAR_TILE Counts any request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800408000H Offcore
    OFFCORE_RESPONSE:request=ANY_DATA_RD: response=L2_HIT_FAR_TILE Counts Demand cacheable data and L1 prefetch data read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800403081H Offcore
    OFFCORE_RESPONSE:request=ANY_RFO: response=L2_HIT_FAR_TILE Counts Demand cacheable data write requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400022H Offcore
    OFFCORE_RESPONSE:request=ANY_CODE_RD: response=L2_HIT_FAR_TILE Counts Demand code reads and prefetch code read requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400044H Offcore
    OFFCORE_RESPONSE:request=ANY_READ: response=L2_HIT_FAR_TILE Counts any Read request EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18004032E7H Offcore
    OFFCORE_RESPONSE:request=ANY_PF_L2: response=L2_HIT_FAR_TILE Counts any Prefetch requests EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1800400060H Offcore
    OFFCORE_RESPONSE:request=ANY_REQUEST: response=L2_MISS Counts any requestAccounts for responses which miss its own tile’s L2. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=331F88000H Offcore