Intel(R) Xeon(R) processor E5 family and Intel(R) Xeon(R) processor E7 family Based on the Ivy Bridge-EP Microarchitecture
This section provides reference for hardware events that can be monitored for the CPU(s):
  • Intel® Xeon® E5/E7 v2 processor
  • Event Name Description Additional Info EventType
    CORE CoreOnly
    INST_RETIRED.ANY Instructions retired from execution. IA32_FIXED_CTR0
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.THREAD Core cycles when the thread is not in halt state. IA32_FIXED_CTR1
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.THREAD_ANY Core cycles when at least one thread on the physical core is not in halt state. IA32_FIXED_CTR1
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.REF_TSC Reference cycles when the core is not in halt state. IA32_FIXED_CTR2
    Architectural, Fixed
    CoreOnly
    BR_INST_RETIRED.ALL_BRANCHES Branch instructions at retirement. EventSel=C4H UMask=00H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES Mispredicted branch instructions at retirement. EventSel=C5H UMask=00H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    CPU_CLK_THREAD_UNHALTED.REF_XCLK Increments at the frequency of XCLK (100 MHz) when not halted. EventSel=3CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) EventSel=3CH UMask=01H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.REF_XCLK Reference cycles when the thread is unhalted. (counts at 100 MHz rate) EventSel=3CH UMask=01H
    Counter=0,1,2,3
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.REF_XCLK_ANY Reference cycles when the at least one thread on the physical core is unhalted. (counts at 100 MHz rate) EventSel=3CH UMask=01H AnyThread=1
    Counter=0,1,2,3
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.THREAD_P Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. EventSel=3CH UMask=00H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.THREAD_P_ANY Core cycles when at least one thread on the physical core is not in halt state. EventSel=3CH UMask=00H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    INST_RETIRED.ANY_P Number of instructions at retirement. EventSel=C0H UMask=00H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    LONGEST_LAT_CACHE.MISS This event counts each cache miss condition for references to the last level cache. EventSel=2EH UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    LONGEST_LAT_CACHE.REFERENCE This event counts requests originating from the core that reference a cache line in the last level cache. EventSel=2EH UMask=4FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    Architectural
    CoreOnly
    ARITH.FPU_DIV Divide operations executed. EventSel=14H UMask=04H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ARITH.FPU_DIV_ACTIVE Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. EventSel=14H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BACLEARS.ANY Number of front end re-steers due to BPU misprediction. EventSel=E6H UMask=1FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_BRANCHES Counts all near executed branches (not necessarily retired). EventSel=88H UMask=FFH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_CONDITIONAL Speculative and retired macro-conditional branches. EventSel=88H UMask=C1H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_DIRECT_JMP Speculative and retired macro-unconditional branches excluding calls and indirects. EventSel=88H UMask=C2H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_DIRECT_NEAR_CALL Speculative and retired direct near calls. EventSel=88H UMask=D0H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Speculative and retired indirect branches excluding calls and returns. EventSel=88H UMask=C4H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN Speculative and retired indirect return branches. EventSel=88H UMask=C8H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.NONTAKEN_CONDITIONAL Not taken macro-conditional branches. EventSel=88H UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_CONDITIONAL Taken speculative and retired macro-conditional branches. EventSel=88H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_DIRECT_JUMP Taken speculative and retired macro-conditional branch instructions excluding calls and indirects. EventSel=88H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL Taken speculative and retired direct near calls. EventSel=88H UMask=90H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired indirect branches excluding calls and returns. EventSel=88H UMask=84H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired indirect calls. EventSel=88H UMask=A0H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN Taken speculative and retired indirect branches with return mnemonic. EventSel=88H UMask=88H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_INST_RETIRED.ALL_BRANCHES_PS All (macro) branch instructions retired. EventSel=C4H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.CONDITIONAL Counts the number of conditional branch instructions retired. EventSel=C4H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.CONDITIONAL_PS Conditional branch instructions retired. EventSel=C4H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.FAR_BRANCH Number of far branches retired. EventSel=C4H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_CALL Direct and indirect near call instructions retired. EventSel=C4H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_CALL_PS Direct and indirect near call instructions retired. EventSel=C4H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_CALL_R3 Direct and indirect macro near call instructions retired (captured in ring 3). EventSel=C4H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_CALL_R3_PS Direct and indirect macro near call instructions retired (captured in ring 3). EventSel=C4H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_RETURN Counts the number of near return instructions retired. EventSel=C4H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_RETURN_PS Return instructions retired. EventSel=C4H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_TAKEN Number of near taken branches retired. EventSel=C4H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NEAR_TAKEN_PS Taken branch instructions retired. EventSel=C4H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_INST_RETIRED.NOT_TAKEN Counts the number of not taken branch instructions retired. EventSel=C4H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_EXEC.ALL_BRANCHES Counts all near executed branches (not necessarily retired). EventSel=89H UMask=FFH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.ALL_CONDITIONAL Speculative and retired mispredicted macro conditional branches. EventSel=89H UMask=C1H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET Mispredicted indirect branches excluding calls and returns. EventSel=89H UMask=C4H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.NONTAKEN_CONDITIONAL Not taken speculative and retired mispredicted macro conditional branches. EventSel=89H UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.TAKEN_CONDITIONAL Taken speculative and retired mispredicted macro conditional branches. EventSel=89H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET Taken speculative and retired mispredicted indirect branches excluding calls and returns. EventSel=89H UMask=84H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL Taken speculative and retired mispredicted indirect calls. EventSel=89H UMask=A0H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_EXEC.TAKEN_RETURN_NEAR Taken speculative and retired mispredicted indirect branches with return mnemonic. EventSel=89H UMask=88H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES_PS Mispredicted macro branch instructions retired. EventSel=C5H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.CONDITIONAL Mispredicted conditional branch instructions retired. EventSel=C5H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.CONDITIONAL_PS Mispredicted conditional branch instructions retired. EventSel=C5H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.NEAR_TAKEN Mispredicted taken branch instructions retired. EventSel=C5H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    BR_MISP_RETIRED.NEAR_TAKEN_PS number of near branch instructions retired that were mispredicted and taken. EventSel=C5H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    CPL_CYCLES.RING0 Unhalted core cycles when the thread is in ring 0. EventSel=5CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    CPL_CYCLES.RING0_TRANS Number of intervals between processor halts while thread is in ring 0. EventSel=5CH UMask=01H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    CPL_CYCLES.RING123 Unhalted core cycles when the thread is not in ring 0. EventSel=5CH UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other is halted. EventSel=3CH UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE Count XClk pulses when this thread is unhalted and the other thread is halted. EventSel=3CH UMask=02H
    Counter=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_L1D_MISS Cycles while L1 cache miss demand load is outstanding. EventSel=A3H UMask=08H CMask=8
    Counter=2 CounterHTOff=2
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_L1D_PENDING Cycles with pending L1 cache miss loads. Set AnyThread to count per core. EventSel=A3H UMask=08H CMask=8
    Counter=2 CounterHTOff=2
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_L2_MISS Cycles while L2 cache miss load* is outstanding. EventSel=A3H UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_L2_PENDING Cycles with pending L2 miss loads. Set AnyThread to count per core. EventSel=A3H UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_LDM_PENDING Cycles with pending memory loads. Set AnyThread to count per core. EventSel=A3H UMask=02H CMask=2
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_MEM_ANY Cycles while memory subsystem has an outstanding load. EventSel=A3H UMask=02H CMask=2
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.CYCLES_NO_EXECUTE Total execution stalls. EventSel=A3H UMask=04H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.STALLS_L1D_MISS Execution stalls while L1 cache miss demand load is outstanding. EventSel=A3H UMask=0CH CMask=12
    Counter=2 CounterHTOff=2
    CoreOnly
    CYCLE_ACTIVITY.STALLS_L1D_PENDING Execution stalls due to L1 data cache miss loads. Set Cmask=0CH. EventSel=A3H UMask=0CH CMask=12
    Counter=2 CounterHTOff=2
    CoreOnly
    CYCLE_ACTIVITY.STALLS_L2_MISS Execution stalls while L2 cache miss load* is outstanding. EventSel=A3H UMask=05H CMask=5
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.STALLS_L2_PENDING Number of loads missed L2. EventSel=A3H UMask=05H CMask=5
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.STALLS_LDM_PENDING Execution stalls due to memory subsystem. EventSel=A3H UMask=06H CMask=6
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.STALLS_MEM_ANY Execution stalls while memory subsystem has an outstanding load. EventSel=A3H UMask=06H CMask=6
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    CYCLE_ACTIVITY.STALLS_TOTAL Total execution stalls. EventSel=A3H UMask=04H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    DSB_FILL.EXCEED_DSB_LINES DSB Fill encountered > 3 DSB lines. EventSel=ACH UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DSB2MITE_SWITCHES.COUNT Number of DSB to MITE switches. EventSel=ABH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DSB2MITE_SWITCHES.PENALTY_CYCLES Cycles DSB to MITE switches caused delay. EventSel=ABH UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size. EventSel=08H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION Demand load cycles page miss handler (PMH) is busy with this walk. EventSel=08H UMask=84H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED Page walk for a large page completed for Demand load. EventSel=08H UMask=88H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK Misses in all TLB levels that cause a page walk of any page size from demand loads. EventSel=08H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.STLB_HIT Counts load operations that missed 1st level DTLB but hit the 2nd level. EventSel=5FH UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED Misses in all TLB levels that caused page walk completed of any size by demand loads. EventSel=08H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_LOAD_MISSES.WALK_DURATION Cycle PMH is busy with a walk due to demand loads. EventSel=08H UMask=84H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_STORE_MISSES.MISS_CAUSES_A_WALK Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G). EventSel=49H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_STORE_MISSES.STLB_HIT Store operations that miss the first TLB level but hit the second and do not cause page walks. EventSel=49H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). EventSel=49H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    DTLB_STORE_MISSES.WALK_DURATION Cycles PMH is busy with this walk. EventSel=49H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    EPT.WALK_CYCLES Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    FP_ASSIST.ANY Cycles with any input/output SSE* or FP assists. EventSel=CAH UMask=1EH CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    FP_ASSIST.SIMD_INPUT Number of SIMD FP assists due to input values. EventSel=CAH UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    FP_ASSIST.SIMD_OUTPUT Number of SIMD FP assists due to output values. EventSel=CAH UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    FP_ASSIST.X87_INPUT Number of X87 FP assists due to input values. EventSel=CAH UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    FP_ASSIST.X87_OUTPUT Number of X87 FP assists due to output values. EventSel=CAH UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle. EventSel=10H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    FP_COMP_OPS_EXE.SSE_PACKED_SINGLE Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle. EventSel=10H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE Counts number of SSE* or AVX-128 double precision FP scalar uops executed. EventSel=10H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle. EventSel=10H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    FP_COMP_OPS_EXE.X87 Counts number of X87 uops executed. EventSel=10H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ICACHE.HIT Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches. EventSel=80H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ICACHE.IFETCH_STALL Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss. EventSel=80H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ICACHE.MISSES Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. EventSel=80H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.ALL_DSB_CYCLES_4_UOPS Counts cycles DSB is delivered four uops. Set Cmask = 4. EventSel=79H UMask=18H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.ALL_DSB_CYCLES_ANY_UOPS Counts cycles DSB is delivered at least one uops. Set Cmask = 1. EventSel=79H UMask=18H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.ALL_MITE_CYCLES_4_UOPS Counts cycles MITE is delivered four uops. Set Cmask = 4. EventSel=79H UMask=24H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.ALL_MITE_CYCLES_ANY_UOPS Counts cycles MITE is delivered at least one uops. Set Cmask = 1. EventSel=79H UMask=24H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.DSB_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path. EventSel=79H UMask=08H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.DSB_UOPS Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. EventSel=79H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.EMPTY Counts cycles the IDQ is empty. EventSel=79H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ.MITE_ALL_UOPS Number of uops delivered to IDQ from any path. EventSel=79H UMask=3CH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MITE_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path. EventSel=79H UMask=04H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MITE_UOPS Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. EventSel=79H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_CYCLES Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy. EventSel=79H UMask=30H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_DSB_CYCLES Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy. EventSel=79H UMask=10H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_DSB_OCCUR Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy. EventSel=79H UMask=10H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_DSB_UOPS Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. EventSel=79H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_MITE_UOPS Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. EventSel=79H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_SWITCHES Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. EventSel=79H UMask=30H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ.MS_UOPS Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. EventSel=79H UMask=30H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CORE Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall. EventSel=9CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled. EventSel=9CH UMask=01H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE. EventSel=9CH UMask=01H Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled. EventSel=9CH UMask=01H CMask=3
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE Cycles with less than 2 uops delivered by the front end. EventSel=9CH UMask=01H CMask=2
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE Cycles with less than 3 uops delivered by the front end. EventSel=9CH UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    ILD_STALL.IQ_FULL Stall cycles due to IQ is full. EventSel=87H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ILD_STALL.LCP Stalls caused by changing prefix length of the instruction. EventSel=87H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    INST_RETIRED.PREC_DIST Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. EventSel=C0H UMask=01H
    Counter=1 CounterHTOff=1
    PEBS:[Precise]
    CoreOnly
    INT_MISC.RECOVERY_CYCLES Number of cycles waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) EventSel=0DH UMask=03H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    INT_MISC.RECOVERY_CYCLES_ANY Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke). EventSel=0DH UMask=03H AnyThread=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    INT_MISC.RECOVERY_STALLS_COUNT Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.) EventSel=0DH UMask=03H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB.ITLB_FLUSH Counts the number of ITLB flushes, includes 4k/2M/4M pages. EventSel=AEH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED Completed page walks in ITLB due to STLB load misses for large pages. EventSel=85H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB_MISSES.MISS_CAUSES_A_WALK Misses in all ITLB levels that cause page walks. EventSel=85H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB_MISSES.STLB_HIT Number of cache load STLB hits. No page walk. EventSel=85H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB_MISSES.WALK_COMPLETED Misses in all ITLB levels that cause completed page walks. EventSel=85H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ITLB_MISSES.WALK_DURATION Cycle PMH is busy with a walk. EventSel=85H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L1D.REPLACEMENT Counts the number of lines brought into the L1 data cache. EventSel=51H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L1D_PEND_MISS.FB_FULL Cycles a demand request was blocked due to Fill Buffers inavailability. EventSel=48H UMask=02H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L1D_PEND_MISS.PENDING Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences. EventSel=48H UMask=01H
    Counter=2 CounterHTOff=2
    CoreOnly
    L1D_PEND_MISS.PENDING_CYCLES Cycles with L1D load Misses outstanding. EventSel=48H UMask=01H CMask=1
    Counter=2 CounterHTOff=2
    CoreOnly
    L1D_PEND_MISS.PENDING_CYCLES_ANY Cycles with L1D load Misses outstanding from any thread on physical core. EventSel=48H UMask=01H AnyThread=1 CMask=1
    Counter=2 CounterHTOff=2
    CoreOnly
    L2_L1D_WB_RQSTS.ALL Not rejected writebacks from L1D to L2 cache lines in any state. EventSel=28H UMask=0FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_L1D_WB_RQSTS.HIT_E Not rejected writebacks from L1D to L2 cache lines in E state. EventSel=28H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_L1D_WB_RQSTS.HIT_M Not rejected writebacks from L1D to L2 cache lines in M state. EventSel=28H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_L1D_WB_RQSTS.MISS Not rejected writebacks that missed LLC. EventSel=28H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_IN.ALL L2 cache lines filling L2. EventSel=F1H UMask=07H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_IN.E L2 cache lines in E state filling L2. EventSel=F1H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_IN.I L2 cache lines in I state filling L2. EventSel=F1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_IN.S L2 cache lines in S state filling L2. EventSel=F1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_OUT.DEMAND_CLEAN Clean L2 cache lines evicted by demand. EventSel=F2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_OUT.DEMAND_DIRTY Dirty L2 cache lines evicted by demand. EventSel=F2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_OUT.DIRTY_ALL Dirty L2 cache lines filling the L2. EventSel=F2H UMask=0AH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_OUT.PF_CLEAN Clean L2 cache lines evicted by the MLC prefetcher. EventSel=F2H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_LINES_OUT.PF_DIRTY Dirty L2 cache lines evicted by the MLC prefetcher. EventSel=F2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.ALL_CODE_RD Counts all L2 code requests. EventSel=24H UMask=30H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.ALL_DEMAND_DATA_RD Counts any demand and L1 HW prefetch data load requests to L2. EventSel=24H UMask=03H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.ALL_PF Counts all L2 HW prefetcher requests. EventSel=24H UMask=C0H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.ALL_RFO Counts all L2 store RFO requests. EventSel=24H UMask=0CH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.CODE_RD_HIT Number of instruction fetches that hit the L2 cache. EventSel=24H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.CODE_RD_MISS Number of instruction fetches that missed the L2 cache. EventSel=24H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.DEMAND_DATA_RD_HIT Demand Data Read requests that hit L2 cache. EventSel=24H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.PF_HIT Counts all L2 HW prefetcher requests that hit L2. EventSel=24H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.PF_MISS Counts all L2 HW prefetcher requests that missed L2. EventSel=24H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.RFO_HIT RFO requests that hit L2 cache. EventSel=24H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_RQSTS.RFO_MISS Counts the number of store RFO requests that miss the L2 cache. EventSel=24H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_STORE_LOCK_RQSTS.ALL RFOs that access cache lines in any state. EventSel=27H UMask=0FH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_STORE_LOCK_RQSTS.HIT_M RFOs that hit cache lines in M state. EventSel=27H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_STORE_LOCK_RQSTS.MISS RFOs that miss cache lines. EventSel=27H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.ALL_PF Any MLC or LLC HW prefetch accessing L2, including rejects. EventSel=F0H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.ALL_REQUESTS Transactions accessing L2 pipe. EventSel=F0H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.CODE_RD L2 cache accesses when fetching instructions. EventSel=F0H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.DEMAND_DATA_RD Demand Data Read requests that access L2 cache. EventSel=F0H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.L1D_WB L1D writebacks that access L2 cache. EventSel=F0H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.L2_FILL L2 fill requests that access L2 cache. EventSel=F0H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.L2_WB L2 writebacks that access L2 cache. EventSel=F0H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    L2_TRANS.RFO RFO requests that access L2 cache. EventSel=F0H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LD_BLOCKS.NO_SR The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. EventSel=03H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LD_BLOCKS.STORE_FORWARD Loads blocked by overlapping with store buffer that cannot be forwarded. EventSel=03H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LD_BLOCKS_PARTIAL.ADDRESS_ALIAS False dependencies in MOB due to partial compare on address. EventSel=07H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LOAD_HIT_PRE.HW_PF Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. EventSel=4CH UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LOAD_HIT_PRE.SW_PF Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. EventSel=4CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LOCK_CYCLES.CACHE_LOCK_DURATION Cycles in which the L1D is locked. EventSel=63H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. EventSel=63H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LSD.CYCLES_4_UOPS Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. EventSel=A8H UMask=01H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LSD.CYCLES_ACTIVE Cycles Uops delivered by the LSD, but didn't come from the decoder. EventSel=A8H UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    LSD.UOPS Number of Uops delivered by the LSD. EventSel=A8H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MACHINE_CLEARS.COUNT Number of machine clears (nukes) of any type. EventSel=C3H UMask=01H EdgeDetect=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MACHINE_CLEARS.MASKMOV Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. EventSel=C3H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of machine clears due to memory order conflicts. EventSel=C3H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MACHINE_CLEARS.SMC Number of self-modifying-code machine clears detected. EventSel=C3H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT Retired load uops whose data source was an on-package LLC hit and cross-core snoop hits. EventSel=D2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT_PS Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. EventSel=D2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM Retired load uops whose data source was an on-package core cache with HitM responses. EventSel=D2H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM_PS Retired load uops which data sources were HitM responses from shared LLC. EventSel=D2H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS Retired load uops whose data source was an on-package core cache LLC hit and cross-core snoop missed. EventSel=D2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS_PS Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. EventSel=D2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE Retired load uops whose data source was LLC hit with no snoop required. EventSel=D2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE_PS Retired load uops which data sources were hits in LLC without snoops required. EventSel=D2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM Retired load uops whose data source was local DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded). EventSel=D3H UMask=03H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM Retired load uops whose data source was remote DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded). EventSel=D3H UMask=0CH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD Data forwarded from remote cache. EventSel=D3H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM Remote cache HITM. EventSel=D3H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.HIT_LFB Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. EventSel=D1H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. EventSel=D1H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_HIT Retired load uops with L1 cache hits as data sources. EventSel=D1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_HIT_PS Retired load uops with L1 cache hits as data sources. EventSel=D1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_MISS Retired load uops whose data source followed an L1 miss. EventSel=D1H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_MISS_PS Retired load uops which data sources following L1 data-cache miss. EventSel=D1H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_HIT Retired load uops with L2 cache hits as data sources. EventSel=D1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_HIT_PS Retired load uops with L2 cache hits as data sources. EventSel=D1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_MISS Retired load uops that missed L2, excluding unknown sources. EventSel=D1H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_MISS_PS Retired load uops with L2 cache misses as data sources. EventSel=D1H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.LLC_HIT Retired load uops whose data source was LLC hit with no snoop required. EventSel=D1H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.LLC_HIT_PS Retired load uops which data sources were data hits in LLC without snoops required. EventSel=D1H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.LLC_MISS Retired load uops whose data source is LLC miss. EventSel=D1H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.LLC_MISS_PS Miss in last-level (L3) cache. Excludes Unknown data-source. EventSel=D1H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 Randomly selected loads with latency value being above 128. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 Randomly selected loads with latency value being above 16. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 Randomly selected loads with latency value being above 256. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 Randomly selected loads with latency value being above 32. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 Randomly selected loads with latency value being above 4. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 Randomly selected loads with latency value being above 512. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 Randomly selected loads with latency value being above 64. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 Randomly selected loads with latency value being above 8. EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, DataLinearAddress, Latency]
    CoreOnly
    MEM_TRANS_RETIRED.PRECISE_STORE Sample stores and collect precise store operation via PEBS record. PMC3 only. EventSel=CDH UMask=02H
    Counter=3 CounterHTOff=3
    PEBS:[Precise, Latency]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_LOADS All retired load uops. EventSel=D0H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_LOADS_PS All retired load uops. (Precise Event) EventSel=D0H UMask=81H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_STORES All retired store uops. EventSel=D0H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_STORES_PS All retired store uops. (Precise Event) EventSel=D0H UMask=82H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.LOCK_LOADS Retired load uops with locked access. EventSel=D0H UMask=21H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.LOCK_LOADS_PS Retired load uops with locked access. (Precise Event) EventSel=D0H UMask=21H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.SPLIT_LOADS Retired load uops that split across a cacheline boundary. EventSel=D0H UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.SPLIT_LOADS_PS Retired load uops that split across a cacheline boundary. (Precise Event) EventSel=D0H UMask=41H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.SPLIT_STORES Retired store uops that split across a cacheline boundary. EventSel=D0H UMask=42H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.SPLIT_STORES_PS Retired store uops that split across a cacheline boundary. (Precise Event) EventSel=D0H UMask=42H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.STLB_MISS_LOADS Retired load uops that miss the STLB. EventSel=D0H UMask=11H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS Retired load uops that miss the STLB. (Precise Event) EventSel=D0H UMask=11H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.STLB_MISS_STORES Retired store uops that miss the STLB. EventSel=D0H UMask=12H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MEM_UOPS_RETIRED.STLB_MISS_STORES_PS Retired store uops that miss the STLB. (Precise Event) EventSel=D0H UMask=12H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    MISALIGN_MEM_REF.LOADS Speculative cache-line split load uops dispatched to L1D. EventSel=05H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MISALIGN_MEM_REF.STORES Speculative cache-line split Store-address uops dispatched to L1D. EventSel=05H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MOVE_ELIMINATION.INT_ELIMINATED Number of integer Move Elimination candidate uops that were eliminated. EventSel=58H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MOVE_ELIMINATION.INT_NOT_ELIMINATED Number of integer Move Elimination candidate uops that were not eliminated. EventSel=58H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MOVE_ELIMINATION.SIMD_ELIMINATED Number of SIMD Move Elimination candidate uops that were eliminated. EventSel=58H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    MOVE_ELIMINATION.SIMD_NOT_ELIMINATED Number of SIMD Move Elimination candidate uops that were not eliminated. EventSel=58H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS.ALL_DATA_RD Data read requests sent to uncore (demand and prefetch). EventSel=B0H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS.ALL_REQUESTS Any memory transaction that reached the SQ. This includes requests initiated by the core, include all LLC prefetches, page walks, etc. EventSel=B0H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS.DEMAND_CODE_RD Demand code read requests sent to uncore. EventSel=B0H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS.DEMAND_DATA_RD Demand data read requests sent to uncore. EventSel=B0H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS.DEMAND_RFO Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. EventSel=B0H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_BUFFER.SQ_FULL Cases when offcore requests buffer cannot take more entries for core. EventSel=B2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. EventSel=60H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore. EventSel=60H UMask=08H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle. EventSel=60H UMask=02H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore. EventSel=60H UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle. EventSel=60H UMask=04H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. EventSel=60H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. EventSel=60H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue. EventSel=60H UMask=01H CMask=6
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. EventSel=60H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    OTHER_ASSISTS.ANY_WB_ASSIST Number of times any microcode assist is invoked by HW upon uop writeback. EventSel=C1H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    OTHER_ASSISTS.AVX_STORE Number of assists associated with 256-bit AVX store operations. EventSel=C1H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    OTHER_ASSISTS.AVX_TO_SSE Number of transitions from AVX-256 to legacy SSE when penalty applicable. EventSel=C1H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    OTHER_ASSISTS.SSE_TO_AVX Number of transitions from SSE to AVX-256 when penalty applicable. EventSel=C1H UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    RESOURCE_STALLS.ANY Cycles Allocation is stalled due to Resource Related reason. EventSel=A2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    RESOURCE_STALLS.ROB Cycles stalled due to re-order buffer full. EventSel=A2H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    RESOURCE_STALLS.RS Cycles stalled due to no eligible RS entry available. EventSel=A2H UMask=04H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    RESOURCE_STALLS.SB Cycles stalled due to no store buffers available (not including draining form sync). EventSel=A2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    ROB_MISC_EVENTS.LBR_INSERTS Count cases of saving new LBR records by hardware. EventSel=CCH UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    RS_EVENTS.EMPTY_CYCLES Cycles the RS is empty for the thread. EventSel=5EH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    RS_EVENTS.EMPTY_END Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues. EventSel=5EH UMask=01H EdgeDetect=1 Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    SIMD_FP_256.PACKED_DOUBLE Counts 256-bit packed double-precision floating-point instructions. EventSel=11H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    SIMD_FP_256.PACKED_SINGLE Counts 256-bit packed single-precision floating-point instructions. EventSel=11H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    SQ_MISC.SPLIT_LOCK Split locks in SQ EventSel=F4H UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    TLB_FLUSH.DTLB_THREAD DTLB flush attempts of the thread-specific entries. EventSel=BDH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    TLB_FLUSH.STLB_ANY Count number of STLB flush attempts. EventSel=BDH UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_0 Cycles which a Uop is dispatched on port 0. EventSel=A1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_0_CORE Cycles per core when uops are dispatched to port 0. EventSel=A1H UMask=01H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_1 Cycles which a Uop is dispatched on port 1. EventSel=A1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_1_CORE Cycles per core when uops are dispatched to port 1. EventSel=A1H UMask=02H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_2 Cycles which a Uop is dispatched on port 2. EventSel=A1H UMask=0CH
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_2_CORE Uops dispatched to port 2, loads and stores per core (speculative and retired). EventSel=A1H UMask=0CH AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_3 Cycles which a Uop is dispatched on port 3. EventSel=A1H UMask=30H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_3_CORE Cycles per core when load or STA uops are dispatched to port 3. EventSel=A1H UMask=30H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_4 Cycles which a Uop is dispatched on port 4. EventSel=A1H UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_4_CORE Cycles per core when uops are dispatched to port 4. EventSel=A1H UMask=40H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_5 Cycles which a Uop is dispatched on port 5. EventSel=A1H UMask=80H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_DISPATCHED_PORT.PORT_5_CORE Cycles per core when uops are dispatched to port 5. EventSel=A1H UMask=80H AnyThread=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE Counts total number of uops to be executed per-core each cycle. EventSel=B1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_1 Cycles at least 1 micro-op is executed from any thread on physical core. EventSel=B1H UMask=02H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_2 Cycles at least 2 micro-op is executed from any thread on physical core. EventSel=B1H UMask=02H CMask=2
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_3 Cycles at least 3 micro-op is executed from any thread on physical core. EventSel=B1H UMask=02H CMask=3
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE_CYCLES_GE_4 Cycles at least 4 micro-op is executed from any thread on physical core. EventSel=B1H UMask=02H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CORE_CYCLES_NONE Cycles with no micro-ops executed from any thread on physical core. EventSel=B1H UMask=02H Invert=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC Cycles where at least 1 uop was executed per-thread. EventSel=B1H UMask=01H CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC Cycles where at least 2 uops were executed per-thread. EventSel=B1H UMask=01H CMask=2
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC Cycles where at least 3 uops were executed per-thread. EventSel=B1H UMask=01H CMask=3
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC Cycles where at least 4 uops were executed per-thread. EventSel=B1H UMask=01H CMask=4
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_EXECUTED.STALL_CYCLES Counts number of cycles no uops were dispatched to be executed on this thread. EventSel=B1H UMask=01H Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    UOPS_EXECUTED.THREAD Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. EventSel=B1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_ISSUED.ANY Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. EventSel=0EH UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_ISSUED.CORE_STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for all threads. EventSel=0EH UMask=01H AnyThread=1 Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    UOPS_ISSUED.FLAGS_MERGE Number of flags-merge uops allocated. Such uops adds delay. EventSel=0EH UMask=10H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_ISSUED.SINGLE_MUL Number of multiply packed/scalar single precision uops allocated. EventSel=0EH UMask=40H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_ISSUED.SLOW_LEA Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. EventSel=0EH UMask=20H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    CoreOnly
    UOPS_ISSUED.STALL_CYCLES Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread. EventSel=0EH UMask=01H Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    CoreOnly
    UOPS_RETIRED.ALL Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. EventSel=C2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.ALL_PS Retired uops. EventSel=C2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.CORE_STALL_CYCLES Cycles without actually retired uops. EventSel=C2H UMask=01H AnyThread=1 Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.RETIRE_SLOTS Counts the number of retirement slots used each cycle. EventSel=C2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.RETIRE_SLOTS_PS Retirement slots used. EventSel=C2H UMask=02H
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.STALL_CYCLES Cycles without actually retired uops. EventSel=C2H UMask=01H Invert=1 CMask=1
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    UOPS_RETIRED.TOTAL_CYCLES Cycles with less than 10 actually retired uops. EventSel=C2H UMask=01H Invert=1 CMask=10
    Counter=0,1,2,3 CounterHTOff=0,1,2,3
    PEBS:[PreciseEventingIP]
    CoreOnly
    UNCORE Uncore
    UNC_C_CLOCKTICKS Uncore Clocks EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_C_COUNTER0_OCCUPANCY Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0. The filtering available is found in the control register - threshold, invert and edge detect. E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry. EventSel=1FH UMask=00H
    Counter=1,2,3
    Uncore
    UNC_C_LLC_LOOKUP.ANY Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for any transaction originating from the IPQ or IRQ. This does not include lookups originating from the ISMQ. EventSel=34H UMask=11H
    Counter=0,1
    Uncore
    UNC_C_LLC_LOOKUP.DATA_READ Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Read transactions EventSel=34H UMask=03H
    Counter=0,1
    Uncore
    UNC_C_LLC_LOOKUP.NID Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system. EventSel=34H UMask=41H
    Counter=0,1
    Uncore
    UNC_C_LLC_LOOKUP.REMOTE_SNOOP Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Filters for only snoop requests coming from the remote socket(s) through the IPQ. EventSel=34H UMask=09H
    Counter=0,1
    Uncore
    UNC_C_LLC_LOOKUP.WRITE Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set filter mask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CBoGlCtrl[22:17] bits correspond to [M'FMESI] state.; Writeback transactions from L2 to the LLC This includes all write transactions -- both Cachable and UC. EventSel=34H UMask=05H
    Counter=0,1
    Uncore
    UNC_C_LLC_VICTIMS.E_STATE Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. EventSel=37H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_LLC_VICTIMS.M_STATE Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. EventSel=37H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_LLC_VICTIMS.MISS Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. EventSel=37H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_LLC_VICTIMS.NID Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in.; Qualify one of the other subevents by the Target NID. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system. EventSel=37H UMask=40H
    Counter=0,1
    Uncore
    UNC_C_LLC_VICTIMS.S_STATE Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. EventSel=37H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_MISC.RFO_HIT_S Miscellaneous events in the Cbo.; Number of times that an RFO hit in S state. This is useful for determining if it might be good for a workload to use RspIWB instead of RspSWB. EventSel=39H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_MISC.RSPI_WAS_FSE Miscellaneous events in the Cbo.; Counts the number of times when a Snoop hit in FSE states and triggered a silent eviction. This is useful because this information is lost in the PRE encodings. EventSel=39H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_MISC.STARTED Miscellaneous events in the Cbo. EventSel=39H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_MISC.WC_ALIASING Miscellaneous events in the Cbo.; Counts the number of times that a USWC write (WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followed by the USWC write. This occurs when there is WC aliasing. EventSel=39H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_QLRU.AGE0 How often age was set to 0 EventSel=3CH UMask=01H
    Counter=0,1
    Uncore
    UNC_C_QLRU.AGE1 How often age was set to 1 EventSel=3CH UMask=02H
    Counter=0,1
    Uncore
    UNC_C_QLRU.AGE2 How often age was set to 2 EventSel=3CH UMask=04H
    Counter=0,1
    Uncore
    UNC_C_QLRU.AGE3 How often age was set to 3 EventSel=3CH UMask=08H
    Counter=0,1
    Uncore
    UNC_C_QLRU.LRU_DECREMENT How often all LRU bits were decremented by 1 EventSel=3CH UMask=10H
    Counter=0,1
    Uncore
    UNC_C_QLRU.VICTIM_NON_ZERO How often we picked a victim that had a non-zero age EventSel=3CH UMask=20H
    Counter=0,1
    Uncore
    UNC_C_RING_AD_USED.CCW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1BH UMask=0CH
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.CW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1BH UMask=03H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.DOWN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1BH UMask=CCH
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.DOWN_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0. EventSel=1BH UMask=04H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.DOWN_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0. EventSel=1BH UMask=08H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.DOWN_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1. EventSel=1BH UMask=40H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.DOWN_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1. EventSel=1BH UMask=80H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.UP Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1BH UMask=33H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.UP_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0. EventSel=1BH UMask=01H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.UP_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0. EventSel=1BH UMask=02H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.UP_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1. EventSel=1BH UMask=10H
    Counter=2,3
    Uncore
    UNC_C_RING_AD_USED.UP_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1. EventSel=1BH UMask=20H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.CCW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1CH UMask=0CH
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.CW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1CH UMask=03H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.DOWN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1CH UMask=CCH
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.DOWN_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0. EventSel=1CH UMask=04H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.DOWN_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0. EventSel=1CH UMask=08H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.DOWN_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1. EventSel=1CH UMask=40H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.DOWN_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1. EventSel=1CH UMask=80H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.UP Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1CH UMask=33H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.UP_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0. EventSel=1CH UMask=01H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.UP_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0. EventSel=1CH UMask=02H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.UP_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1. EventSel=1CH UMask=10H
    Counter=2,3
    Uncore
    UNC_C_RING_AK_USED.UP_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1. EventSel=1CH UMask=20H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.CCW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1DH UMask=0CH
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.CW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1DH UMask=03H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.DOWN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1DH UMask=CCH
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.DOWN_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 0. EventSel=1DH UMask=04H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.DOWN_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 0. EventSel=1DH UMask=08H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.DOWN_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Even ring polarity on Virtual Ring 1. EventSel=1DH UMask=40H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.DOWN_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Down and Odd ring polarity on Virtual Ring 1. EventSel=1DH UMask=80H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.UP Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring. EventSel=1DH UMask=33H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.UP_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 0. EventSel=1DH UMask=01H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.UP_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 0. EventSel=1DH UMask=02H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.UP_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Even ring polarity on Virtual Ring 1. EventSel=1DH UMask=10H
    Counter=2,3
    Uncore
    UNC_C_RING_BL_USED.UP_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in JKT -- a clockwise ring and a counter-clockwise ring. On the left side of the ring, the "UP" direction is on the clockwise ring and "DN" is on the counter-clockwise ring. On the right side of the ring, this is reversed. The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.; Filters for the Up and Odd ring polarity on Virtual Ring 1. EventSel=1DH UMask=20H
    Counter=2,3
    Uncore
    UNC_C_RING_BOUNCES.AD_IRQ Number of LLC responses that bounced on the Ring. EventSel=05H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.AK Number of LLC responses that bounced on the Ring.; Acknowledgements to core EventSel=05H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.AK_CORE Number of LLC responses that bounced on the Ring.: Acknowledgements to core EventSel=05H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.BL Number of LLC responses that bounced on the Ring.; Data Responses to core EventSel=05H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.BL_CORE Number of LLC responses that bounced on the Ring.: Data Responses to core EventSel=05H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.IV Number of LLC responses that bounced on the Ring.; Snoops of processor's cache. EventSel=05H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RING_BOUNCES.IV_CORE Number of LLC responses that bounced on the Ring.: Snoops of processor's cache. EventSel=05H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RING_IV_USED.ANY Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters any polarity EventSel=1EH UMask=0FH
    Counter=2,3
    Uncore
    UNC_C_RING_IV_USED.DOWN Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Down polarity EventSel=1EH UMask=CCH
    Counter=2,3
    Uncore
    UNC_C_RING_IV_USED.UP Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for Up polarity EventSel=1EH UMask=33H
    Counter=2,3
    Uncore
    UNC_C_RING_SINK_STARVED.AD_IPQ UNC_C_RING_SINK_STARVED.AD_IPQ EventSel=06H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RING_SINK_STARVED.AD_IRQ UNC_C_RING_SINK_STARVED.AD_IRQ EventSel=06H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RING_SINK_STARVED.IV UNC_C_RING_SINK_STARVED.IV EventSel=06H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RING_SRC_THRTL UNC_C_RING_SRC_THRTL EventSel=07H UMask=00H
    Counter=0,1
    Uncore
    UNC_C_RxR_EXT_STARVED.IPQ Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IPQ is externally startved and therefore we are blocking the IRQ. EventSel=12H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_EXT_STARVED.IRQ Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; IRQ is externally starved and therefore we are blocking the IPQ. EventSel=12H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_EXT_STARVED.ISMQ_BIDS Counts cycles in external starvation. This occurs when one of the ingress queues is being starved by the other queues.; Number of times that the ISMQ Bid. EventSel=12H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RxR_EXT_STARVED.PRQ IRQ is blocking the ingress queue and causing the starvation. EventSel=12H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RxR_INSERTS.IPQ Counts number of allocations per cycle into the specified Ingress queue. EventSel=13H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RxR_INSERTS.IRQ Counts number of allocations per cycle into the specified Ingress queue. EventSel=13H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_INSERTS.IRQ_REJ Counts number of allocations per cycle into the specified Ingress queue. EventSel=13H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_INSERTS.IRQ_REJECTED Counts number of allocations per cycle into the specified Ingress queue. EventSel=13H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_INSERTS.VFIFO Counts number of allocations per cycle into the specified Ingress queue.; Counts the number of allocations into the IRQ Ordering FIFO. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Occupancy Accumulator event, can be used to calculate average lifetime in the FIFO. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ. EventSel=13H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RxR_INT_STARVED.IPQ Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IPQ in Internal Starvation. EventSel=14H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RxR_INT_STARVED.IRQ Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the IRQ in Internal Starvation. EventSel=14H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_INT_STARVED.ISMQ Counts cycles in internal starvation. This occurs when one (or more) of the entries in the ingress queue are being starved out by other entries in that queue.; Cycles with the ISMQ in Internal Starvation. EventSel=14H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from an address conflicts. Address conflicts out of the IPQ should be rare. They will generally only occur if two different sockets are sending requests to the same address at the same time. This is a true "conflict" case, unlike the IPQ Address Conflict which is commonly caused by prefetching characteristics. EventSel=31H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RxR_IPQ_RETRY.ANY Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject. TOR rejects from the IPQ can be caused by the Egress being full or Address Conflicts. EventSel=31H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_IPQ_RETRY.FULL Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries.; Counts the number of times that a request form the IPQ was retried because of a TOR reject from the Egress being full. IPQ requests make use of the AD Egress for regular responses, the BL egress to forward data, and the AK egress to return credits. EventSel=31H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_IPQ_RETRY.QPI_CREDITS Number of times a snoop (probe) request had to retry. Filters exist to cover some of the common cases retries. EventSel=31H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT Counts the number of times that a request from the IRQ was retried because of an address match in the TOR. In order to maintain coherency, requests to the same address are not allowed to pass each other up in the Cbo. Therefore, if there is an outstanding request to a given address, one cannot issue another request to that address until it is complete. This comes up most commonly with prefetches. Outstanding prefetches occasionally will not complete their memory fetch and a demand request to the same address will then sit in the IRQ and get retried until the prefetch fills the data into the LLC. Therefore, it will not be uncommon to see this case in high bandwidth streaming workloads when the LLC Prefetcher in the core is enabled. EventSel=32H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.ANY Counts the number of IRQ retries that occur. Requests from the IRQ are retried if they are rejected from the TOR pipeline for a variety of reasons. Some of the most common reasons include if the Egress is full, there are no RTIDs, or there is a Physical Address match to another outstanding request. EventSel=32H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.FULL Counts the number of times that a request from the IRQ was retried because it failed to acquire an entry in the Egress. The egress is the buffer that queues up for allocating onto the ring. IRQ requests can make use of all four rings and all four Egresses. If any of the queues that a given request needs to make use of are full, the request will be retried. EventSel=32H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.IIO_CREDITS Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO. EventSel=32H UMask=20H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.QPI_CREDITS Number of requests rejects because of lack of QPI Ingress credits. These credits are required in order to send transactions to the QPI agent. Please see the QPI_IGR_CREDITS events for more information. EventSel=32H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RxR_IRQ_RETRY.RTID Counts the number of times that requests from the IRQ were retried because there were no RTIDs available. RTIDs are required after a request misses the LLC and needs to send snoops and/or requests to memory. If there are no RTIDs available, requests will queue up in the IRQ and retry until one becomes available. Note that there are multiple RTID pools for the different sockets. There may be cases where the local RTIDs are all used, but requests destined for remote memory can still acquire an RTID because there are remote RTIDs available. This event does not provide any filtering for this case. EventSel=32H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.ANY Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the total number of times that a request from the ISMQ retried because of a TOR reject. ISMQ requests generally will not need to retry (or at least ISMQ retries are less common than IRQ retries). ISMQ requests will retry if they are not able to acquire a needed Egress credit to get onto the ring, or for cache evictions that need to acquire an RTID. Most ISMQ requests already have an RTID, so eviction retries will be less common here. EventSel=33H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.FULL Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by a lack of Egress credits. The egress is the buffer that queues up for allocating onto the ring. If any of the Egress queues that a given request needs to make use of are full, the request will be retried. EventSel=33H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Number of times a request attempted to acquire the NCS/NCB credit for sending messages on BL to the IIO. There is a single credit in each CBo that is shared between the NCS and NCB message classes for sending transactions on the BL ring (such as read data) to the IIO. EventSel=33H UMask=20H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores. EventSel=33H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.RTID Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Counts the number of times that a request from the ISMQ retried because of a TOR reject caused by no RTIDs. M-state cache evictions are serviced through the ISMQ, and must acquire an RTID in order to write back to memory. If no RTIDs are available, they will be retried. EventSel=33H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_RxR_ISMQ_RETRY.WB_CREDITS Number of times a transaction flowing through the ISMQ had to retry. Transaction pass through the ISMQ as responses for requests that already exist in the Cbo. Some examples include: when data is returned or when snoop responses come back from the cores.; Retries of writes to local memory due to lack of HT WB credits EventSel=33H UMask=80H
    Counter=0,1
    Uncore
    UNC_C_RxR_OCCUPANCY.IPQ Counts number of entries in the specified Ingress queue in each cycle. EventSel=11H UMask=04H
    Counter=0
    Uncore
    UNC_C_RxR_OCCUPANCY.IRQ Counts number of entries in the specified Ingress queue in each cycle. EventSel=11H UMask=01H
    Counter=0
    Uncore
    UNC_C_RxR_OCCUPANCY.IRQ_REJ Counts number of entries in the specified Ingress queue in each cycle. EventSel=11H UMask=02H
    Counter=0
    Uncore
    UNC_C_RxR_OCCUPANCY.IRQ_REJECTED Counts number of entries in the specified Ingress queue in each cycle. EventSel=11H UMask=02H
    Counter=0
    Uncore
    UNC_C_RxR_OCCUPANCY.VFIFO Counts number of entries in the specified Ingress queue in each cycle.; Accumulates the number of used entries in the IRQ Ordering FIFO in each cycle. In JKT, it is necessary to keep IO requests in order. Therefore, they are allocated into an ordering FIFO that sits next to the IRQ, and must be satisfied from the FIFO in order (with respect to each other). This event, in conjunction with the Allocations event, can be used to calculate average lifetime in the FIFO. This event can be used in conjunction with the Not Empty event to calculate average queue occupancy. Transactions are allocated into the FIFO as soon as they enter the Cachebo (and the IRQ) and are deallocated from the FIFO as soon as they are deallocated from the IRQ. EventSel=11H UMask=10H
    Counter=0
    Uncore
    UNC_C_TOR_INSERTS.ALL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots. EventSel=35H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.EVICTION Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Eviction transactions inserted into the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory). EventSel=35H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.LOCAL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by locally HOMed memory. EventSel=35H UMask=28H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.LOCAL_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory. EventSel=35H UMask=21H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.MISS_LOCAL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by locally HOMed memory. EventSel=35H UMask=2AH
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by locally HOMed memory. EventSel=35H UMask=23H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.MISS_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match an opcode. EventSel=35H UMask=03H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.MISS_REMOTE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that are satisifed by remote caches or remote memory. EventSel=35H UMask=8AH
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory. EventSel=35H UMask=83H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_ALL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched (matches an RTID destination) transactions inserted into the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid. In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system. EventSel=35H UMask=48H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_EVICTION Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched eviction transactions inserted into the TOR. EventSel=35H UMask=44H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_MISS_ALL Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All NID matched miss requests that were inserted into the TOR. EventSel=35H UMask=4AH
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_MISS_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Miss transactions inserted into the TOR that match a NID and an opcode. EventSel=35H UMask=43H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match a NID and an opcode. EventSel=35H UMask=41H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.NID_WB Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; NID matched write transactions inserted into the TOR. EventSel=35H UMask=50H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Transactions inserted into the TOR that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc) EventSel=35H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.REMOTE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions inserted into the TOR that are satisifed by remote caches or remote memory. EventSel=35H UMask=88H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.REMOTE_OPCODE Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; All transactions, satisifed by an opcode, inserted into the TOR that are satisifed by remote caches or remote memory. EventSel=35H UMask=81H
    Counter=0,1
    Uncore
    UNC_C_TOR_INSERTS.WB Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182).; Write transactions inserted into the TOR. This does not include "RFO", but actual operations that contain data being sent from the core. EventSel=35H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_TOR_OCCUPANCY.ALL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All valid TOR entries. This includes requests that reside in the TOR for a short time, such as LLC Hits that do not need to snoop cores or requests that get rejected and have to be retried through one of the ingress queues. The TOR is more commonly a bottleneck in skews with smaller core counts, where the ratio of RTIDs to TOR entries is larger. Note that there are reserved TOR entries for various request types, so it is possible that a given request type be blocked with an occupancy that is less than 20. Also note that generally requests will not be able to arbitrate into the TOR pipeline if there are no available TOR slots. EventSel=36H UMask=08H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.EVICTION For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding eviction transactions in the TOR. Evictions can be quick, such as when the line is in the F, S, or E states and no core valid bits are set. They can also be longer if either CV bits are set (so the cores need to be snooped) and/or if there is a HitM (in which case it is necessary to write the request out to memory). EventSel=36H UMask=04H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.LOCAL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) EventSel=36H UMask=28H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory. EventSel=36H UMask=21H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_ALL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding miss requests in the TOR. 'Miss' means the allocation requires an RTID. This generally means that the request was sent to memory or MMIO. EventSel=36H UMask=0AH
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_LOCAL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) EventSel=36H UMask=2AH
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by locally HOMed memory. EventSel=36H UMask=23H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries for miss transactions that match an opcode. This generally means that the request was sent to memory or MMIO. EventSel=36H UMask=03H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_REMOTE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) EventSel=36H UMask=8AH
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory. EventSel=36H UMask=83H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_ALL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of NID matched outstanding requests in the TOR. The NID is programmed in Cn_MSR_PMON_BOX_FILTER.nid.In conjunction with STATE = I, it is possible to monitor misses to specific NIDs in the system. EventSel=36H UMask=48H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_EVICTION For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding NID matched eviction transactions in the TOR . EventSel=36H UMask=44H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_MISS_ALL For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID. EventSel=36H UMask=4AH
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding Miss requests in the TOR that match a NID and an opcode. EventSel=36H UMask=43H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match a NID and an opcode. EventSel=36H UMask=41H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.NID_WB For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); NID matched write transactions int the TOR. EventSel=36H UMask=50H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); TOR entries that match an opcode (matched by Cn_MSR_PMON_BOX_FILTER.opc). EventSel=36H UMask=01H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.REMOTE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182) EventSel=36H UMask=88H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Number of outstanding transactions, satisifed by an opcode, in the TOR that are satisifed by remote caches or remote memory. EventSel=36H UMask=81H
    Counter=0
    Uncore
    UNC_C_TOR_OCCUPANCY.WB For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. There are a number of subevent 'filters' but only a subset of the subevent combinations are valid. Subevents that require an opcode or NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. If, for example, one wanted to count DRD Local Misses, one should select "MISS_OPC_MATCH" and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); Write transactions in the TOR. This does not include "RFO", but actual operations that contain data being sent from the core. EventSel=36H UMask=10H
    Counter=0
    Uncore
    UNC_C_TxR_ADS_USED.AD Onto AD Ring EventSel=04H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_TxR_ADS_USED.AK Onto AK Ring EventSel=04H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_TxR_ADS_USED.BL Onto BL Ring EventSel=04H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.AD_CACHE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AD ring. Some example include outbound requests, snoop requests, and snoop responses. EventSel=02H UMask=01H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.AD_CORE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AD ring. This is commonly used for outbound requests. EventSel=02H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.AK_CACHE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the AK ring. This is commonly used for credit returns and GO responses. EventSel=02H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.AK_CORE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the AK ring. This is commonly used for snoop responses coming from the core and destined for a Cachebo. EventSel=02H UMask=20H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.BL_CACHE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the BL ring. This is commonly used to send data from the cache to various destinations. EventSel=02H UMask=04H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.BL_CORE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Corebo destined for the BL ring. This is commonly used for transfering writeback data to the cache. EventSel=02H UMask=40H
    Counter=0,1
    Uncore
    UNC_C_TxR_INSERTS.IV_CACHE Number of allocations into the Cbo Egress. The Egress is used to queue up requests destined for the ring.; Ring transactions from the Cachebo destined for the IV ring. This is commonly used for snoops to the cores. EventSel=02H UMask=08H
    Counter=0,1
    Uncore
    UNC_C_TxR_STARVED.AD_CORE Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the core AD egress spent in starvation EventSel=03H UMask=10H
    Counter=0,1
    Uncore
    UNC_C_TxR_STARVED.AK_BOTH Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that both AK egresses spent in starvation EventSel=03H UMask=02H
    Counter=0,1
    Uncore
    UNC_C_TxR_STARVED.IV Counts injection starvation. This starvation is triggered when the Egress cannot send a transaction onto the ring for a long period of time.; cycles that the cachebo IV egress spent in starvation EventSel=03H UMask=08H
    Counter=0,1
    Uncore
    UNC_H_ADDR_OPC_MATCH.AD QPI Address/Opcode Match; AD Opcodes EventSel=20H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_ADDR_OPC_MATCH.ADDR QPI Address/Opcode Match; Address EventSel=20H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_ADDR_OPC_MATCH.AK QPI Address/Opcode Match; AK Opcodes EventSel=20H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_ADDR_OPC_MATCH.BL QPI Address/Opcode Match; BL Opcodes EventSel=20H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_ADDR_OPC_MATCH.FILT QPI Address/Opcode Match; Address & Opcode Match EventSel=20H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_ADDR_OPC_MATCH.OPC QPI Address/Opcode Match; Opcode EventSel=20H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_BYPASS Number of transactions that bypass the BT (fifo) to HT EventSel=52H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_CYCLES_NE Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT. EventSel=42H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_CYCLES_NE.LOCAL Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT. EventSel=42H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_CYCLES_NE.REMOTE Cycles the Backup Tracker (BT) is not empty. The BT is the actual HOM tracker in IVT. EventSel=42H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.LOCAL Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.READS_LOCAL Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.READS_REMOTE Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.REMOTE Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.WRITES_LOCAL Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_OCCUPANCY.WRITES_REMOTE Accumulates the occupancy of the HA BT pool in every cycle. This can be used with the "not empty" stat to calculate average queue occupancy or the "allocations" stat in order to calculate average queue latency. HA BTs are allocated as soon as a request enters the HA and is released after the snoop response and data return (or post in the case of a write) and the response is returned on the ring. EventSel=43H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard EventSel=51H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming snoop hazard EventSel=51H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard EventSel=51H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD Counts the number of cycles when the HA does not issue transaction from BT to HT.; Cycles unable to issue from BT due to incoming BL data hazard EventSel=51H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_BYPASS_IMC.NOT_TAKEN Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that could not take the bypass. EventSel=14H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_BYPASS_IMC.TAKEN Counts the number of times when the HA was able to bypass was attempted. This is a latency optimization for situations when there is light loadings on the memory subsystem. This can be filted by when the bypass was taken and when it was not.; Filter for transactions that succeeded in taking the bypass. EventSel=14H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_CLOCKTICKS Counts the number of uclks in the HA. This will be slightly different than the count in the Ubox because of enable/freeze delays. The HA is on the other side of the die from the fixed Ubox uclk counter, so the drift could be somewhat larger than in units that are closer like the QPI Agent. EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_CONFLICT_CYCLES.ACKCNFLTS Count the number of Ackcnflts EventSel=0BH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_CONFLICT_CYCLES.CMP_FWDS Count the number of Cmp_Fwd. This will give the number of late conflicts. EventSel=0BH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_CONFLICT_CYCLES.CONFLICT Counts the number of cycles that we are handling conflicts. EventSel=0BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_CONFLICT_CYCLES.LAST Count every last conflictor in conflict chain. Can be used to compute the average conflict chain length as (#Ackcnflts/#LastConflictor)+1. This can be used to give a feel for the conflict chain lenghts while analyzing lock kernels. EventSel=0BH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECT2CORE_COUNT Number of Direct2Core messages sent EventSel=11H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECT2CORE_CYCLES_DISABLED Number of cycles in which Direct2Core was disabled EventSel=12H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECT2CORE_TXN_OVERRIDE Number of Reads where Direct2Core overridden EventSel=13H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LAT_OPT Directory Latency Optimization Data Return Path Taken. When directory mode is enabled and the directory retuned for a read is Dir=I, then data can be returned using a faster path if certain conditions are met (credits, free pipeline, etc). EventSel=41H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.ANY Directory Lookups: Any state EventSel=0CH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.NO_SNP Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that did not have to send any snoops because the directory bit was clear. EventSel=0CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.SNOOP_A Directory Lookups: Snoop A EventSel=0CH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.SNOOP_S Directory Lookups: Snoop S EventSel=0CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.SNP Counts the number of transactions that looked up the directory. Can be filtered by requests that had to snoop and those that did not have to.; Filters for transactions that had to send one or more snoops because the directory bit was set. EventSel=0CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.STATE_A Directory Lookups: A State EventSel=0CH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.STATE_I Directory Lookups: I State EventSel=0CH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_LOOKUP.STATE_S Directory Lookups: S State EventSel=0CH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.A2I Directory Updates: A2I EventSel=0DH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.A2S Directory Updates: A2S EventSel=0DH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.ANY Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears. EventSel=0DH UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.CLEAR Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory clears. This occurs when snoops were sent and all returned with RspI. EventSel=0DH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.I2A Directory Updates: I2A EventSel=0DH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.I2S Directory Updates: I2S EventSel=0DH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.S2A Directory Updates: S2A EventSel=0DH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.S2I Directory Updates: S2I EventSel=0DH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_DIRECTORY_UPDATE.SET Counts the number of directory updates that were required. These result in writes to the memory controller. This can be filtered by directory sets and directory clears.; Filter for directory sets. This occurs when a remote read transaction requests memory, bringing it to a remote cache. EventSel=0DH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_AD_QPI2_ACCUMULATOR AD QPI Link 2 Credit Accumulator EventSel=59H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_BL_QPI2_ACCUMULATOR BL QPI Link 2 Credit Accumulator EventSel=5AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_CREDITS_AD_QPI2 Accumulates the number of credits available to the QPI Link 2 AD Ingress buffer. EventSel=59H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_CREDITS_BL_QPI2 Accumulates the number of credits available to the QPI Link 2 BL Ingress buffer. EventSel=5AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links. EventSel=22H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links. EventSel=22H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links. EventSel=22H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1 Counts the number of cycles when the HA does not have credits to send messages to the QPI Agent. This can be filtered by the different credit pools and the different links. EventSel=22H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_READS.NORMAL Count of the number of reads issued to any of the memory controller channels. This can be filtered by the priority of the reads. EventSel=17H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_RETRY Retry Events EventSel=1EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_WRITES.ALL Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH. EventSel=1AH UMask=0FH
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_WRITES.FULL Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH. EventSel=1AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_WRITES.FULL_ISOCH Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH. EventSel=1AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_WRITES.PARTIAL Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH. EventSel=1AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_IMC_WRITES.PARTIAL_ISOCH Counts the total number of full line writes issued from the HA into the memory controller. This counts for all four channels. It can be filtered by full/partial and ISOCH/non-ISOCH. EventSel=1AH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_CONFLICTS.ANY IODC Conflicts; Any Conflict EventSel=57H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_CONFLICTS.LAST IODC Conflicts; Last Conflict EventSel=57H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID IODC Conflicts: Remote InvItoE - Same RTID EventSel=57H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR IODC Conflicts: Remote (Other) - Same Addr EventSel=57H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_INSERTS IODC Allocations EventSel=56H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_IODC_OLEN_WBMTOI Num IODC 0 Length Writebacks M to I - All of which are dropped. EventSel=58H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB.INVITOE_LOCAL Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB. EventSel=53H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB.READS_LOCAL Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB. EventSel=53H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB.REMOTE Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB. EventSel=53H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB_EDR.ALL Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return EventSel=54H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB_EDR.READS_LOCAL_I Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return EventSel=54H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB_EDR.READS_LOCAL_S Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return EventSel=54H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB_EDR.READS_REMOTE_I Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return EventSel=54H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_OSB_EDR.READS_REMOTE_S Counts the number of transactions that broadcast snoop due to OSB, but found clean data in memory and was able to do early data return EventSel=54H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.INVITOE_LOCAL Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from the local socket. EventSel=01H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.INVITOE_REMOTE Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only InvItoEs coming from remote sockets. EventSel=01H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.READS Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming ead requests. This is a good proxy for LLC Read Misses (including RFOs). EventSel=01H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.READS_LOCAL Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the local socket. This is a good proxy for LLC Read Misses (including RFOs) from the local socket. EventSel=01H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.READS_REMOTE Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only read requests coming from the remote socket. This is a good proxy for LLC Read Misses (including RFOs) from the remote socket. EventSel=01H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.WRITES Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; Incoming write requests. EventSel=01H UMask=0CH
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.WRITES_LOCAL Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from the local socket. EventSel=01H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_REQUESTS.WRITES_REMOTE Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc).; This filter includes only writes coming from remote sockets. EventSel=01H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CCW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=3EH UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CCW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=3EH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CCW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=3EH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CCW_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=3EH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CCW_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=3EH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=3EH UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=3EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=3EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CW_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=3EH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AD_USED.CW_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=3EH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CCW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=3FH UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CCW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=3FH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CCW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=3FH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CCW_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=3FH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CCW_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=3FH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=3FH UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=3FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=3FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CW_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=3FH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_AK_USED.CW_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=3FH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CCW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=40H UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CCW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=40H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CCW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=40H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CCW_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=40H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CCW_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=40H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=40H UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=40H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=40H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CW_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=40H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_RING_BL_USED.CW_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=40H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0 Counts the number of cycles when there are no "regular" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only. EventSel=15H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1 Counts the number of cycles when there are no "regular" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only. EventSel=15H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2 Counts the number of cycles when there are no "regular" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only. EventSel=15H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3 Counts the number of cycles when there are no "regular" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only. EventSel=15H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0 Counts the number of cycles when there are no "special" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only. EventSel=16H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1 Counts the number of cycles when there are no "special" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only. EventSel=16H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2 Counts the number of cycles when there are no "special" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only. EventSel=16H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3 Counts the number of cycles when there are no "special" credits available for posting reads from the HA into the iMC. In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's RPQ (read pending queue). This queue is broken into regular credits/buffers that are used by general reads, and "special" requests such as ISOCH reads. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only. EventSel=16H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSP_FWD_WB Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory. EventSel=21H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSP_WB Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership. EventSel=21H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSPCNFLCT Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI. EventSel=21H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSPI Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data). EventSel=21H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSPIFWD Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE. EventSel=21H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSPS Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS. EventSel=21H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNOOP_RESP.RSPSFWD Counts the total number of RspI snoop responses received. Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system. In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received. For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state. EventSel=21H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.OTHER Number of snoop responses received for a Local request; Filters for all other snoop responses. EventSel=60H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT Number of snoop responses received for a Local request; Filters for snoops responses of RspConflict. This is returned when a snoop finds an existing outstanding transaction in a remote caching agent when it CAMs that caching agent. This triggers conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI. EventSel=60H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPI Number of snoop responses received for a Local request; Filters for snoops responses of RspI. RspI is returned when the remote cache does not have the data, or when the remote cache silently evicts data (such as when an RFO hits non-modified data). EventSel=60H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD Number of snoop responses received for a Local request; Filters for snoop responses of RspIFwd. This is returned when a remote caching agent forwards data and the requesting agent is able to acquire the data in E or M states. This is commonly returned with RFO transactions. It can be either a HitM or a HitFE. EventSel=60H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPS Number of snoop responses received for a Local request; Filters for snoop responses of RspS. RspS is returned when a remote cache has data but is not forwarding it. It is a way to let the requesting socket know that it cannot allocate the data in E state. No data is sent with S RspS. EventSel=60H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD Number of snoop responses received for a Local request; Filters for a snoop response of RspSFwd. This is returned when a remote caching agent forwards data but holds on to its currentl copy. This is common for data and code reads that hit in a remote socket in E or F state. EventSel=60H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB Number of snoop responses received for a Local request; Filters for a snoop response of Rsp*Fwd*WB. This snoop response is only used in 4s systems. It is used when a snoop HITM's in a remote caching agent and it directly forwards data to a requestor, and simultaneously returns data to the home to be written back to memory. EventSel=60H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB Number of snoop responses received for a Local request; Filters for a snoop response of RspIWB or RspSWB. This is returned when a non-RFO request hits in M state. Data and Code Reads can return either RspIWB or RspSWB depending on how the system has been configured. InvItoE transactions will also return RspIWB because they must acquire ownership. EventSel=60H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION0 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 0 EventSel=1BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION1 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 1 EventSel=1BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION2 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 2 EventSel=1BH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION3 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 3 EventSel=1BH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION4 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 4 EventSel=1BH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION5 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 5 EventSel=1BH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION6 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 6 EventSel=1BH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G0.REGION7 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 0 to 7. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 7 EventSel=1BH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G1.REGION10 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 10 EventSel=1CH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G1.REGION11 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 11 EventSel=1CH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G1.REGION8 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 8 EventSel=1CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TAD_REQUESTS_G1.REGION9 Counts the number of HA requests to a given TAD region. There are up to 11 TAD (target address decode) regions in each home agent. All requests destined for the memory controller must first be decoded to determine which TAD region they are in. This event is filtered based on the TAD region ID, and covers regions 8 to 10. This event is useful for understanding how applications are using the memory that is spread across the different memory regions. It is particularly useful for "Monroe" systems that use the TAD to enable individual channels to enter self-refresh to save power.; Filters request made to TAD Region 9 EventSel=1CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TRACKER_CYCLES_NE Tracker Cycles Not Empty EventSel=03H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD.HOM Counts the number of outbound transactions on the AD ring. This can be filtered by the NDR and SNP message classes. See the filter descriptions for more details.; Filter for outbound NDR transactions sent on the AD ring. NDR stands for "non-data response" and is generally used for completions that do not include data. AD NDR is used for transactions to remote sockets. EventSel=0FH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_FULL.ALL AD Egress Full; Cycles full from both schedulers EventSel=2AH UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_FULL.SCHED0 AD Egress Full; Filter for cycles full from scheduler bank 0 EventSel=2AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_FULL.SCHED1 AD Egress Full; Filter for cycles full from scheduler bank 1 EventSel=2AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_NE.ALL AD Egress Not Empty; Cycles full from both schedulers EventSel=29H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_NE.SCHED0 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 0 EventSel=29H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_CYCLES_NE.SCHED1 AD Egress Not Empty; Filter for cycles not empty from scheduler bank 1 EventSel=29H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_INSERTS.ALL AD Egress Allocations; Allocations from both schedulers EventSel=27H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_INSERTS.SCHED0 AD Egress Allocations; Filter for allocations from scheduler bank 0 EventSel=27H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_INSERTS.SCHED1 AD Egress Allocations; Filter for allocations from scheduler bank 1 EventSel=27H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_OCCUPANCY.SCHED0 AD Egress Occupancy; Filter for occupancy from scheduler bank 0 EventSel=28H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AD_OCCUPANCY.SCHED1 AD Egress Occupancy; Filter for occupancy from scheduler bank 1 EventSel=28H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK.CRD_CBO Outbound Ring Transactions on AK: CRD Transactions to Cbo EventSel=0EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_FULL.ALL AK Egress Full; Cycles full from both schedulers EventSel=32H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_FULL.SCHED0 AK Egress Full; Filter for cycles full from scheduler bank 0 EventSel=32H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_FULL.SCHED1 AK Egress Full; Filter for cycles full from scheduler bank 1 EventSel=32H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_NE.ALL AK Egress Not Empty; Cycles full from both schedulers EventSel=31H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_NE.SCHED0 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 0 EventSel=31H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_CYCLES_NE.SCHED1 AK Egress Not Empty; Filter for cycles not empty from scheduler bank 1 EventSel=31H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_INSERTS.ALL AK Egress Allocations; Allocations from both schedulers EventSel=2FH UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_INSERTS.SCHED0 AK Egress Allocations; Filter for allocations from scheduler bank 0 EventSel=2FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_INSERTS.SCHED1 AK Egress Allocations; Filter for allocations from scheduler bank 1 EventSel=2FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_OCCUPANCY.SCHED0 AK Egress Occupancy; Filter for occupancy from scheduler bank 0 EventSel=30H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_AK_OCCUPANCY.SCHED1 AK Egress Occupancy; Filter for occupancy from scheduler bank 1 EventSel=30H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL.DRS_CACHE Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to the cache. EventSel=10H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL.DRS_CORE Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent directly to the requesting core. EventSel=10H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL.DRS_QPI Counts the number of DRS messages sent out on the BL ring. This can be filtered by the destination.; Filter for data being sent to a remote socket over QPI. EventSel=10H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_FULL.ALL BL Egress Full; Cycles full from both schedulers EventSel=36H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_FULL.SCHED0 BL Egress Full; Filter for cycles full from scheduler bank 0 EventSel=36H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_FULL.SCHED1 BL Egress Full; Filter for cycles full from scheduler bank 1 EventSel=36H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_NE.ALL BL Egress Not Empty; Cycles full from both schedulers EventSel=35H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_NE.SCHED0 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 0 EventSel=35H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_CYCLES_NE.SCHED1 BL Egress Not Empty; Filter for cycles not empty from scheduler bank 1 EventSel=35H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_INSERTS.ALL BL Egress Allocations; Allocations from both schedulers EventSel=33H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_INSERTS.SCHED0 BL Egress Allocations; Filter for allocations from scheduler bank 0 EventSel=33H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_INSERTS.SCHED1 BL Egress Allocations; Filter for allocations from scheduler bank 1 EventSel=33H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_OCCUPANCY.ALL BL Egress Occupancy: All EventSel=34H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_OCCUPANCY.SCHED0 BL Egress Occupancy; Filter for occupancy from scheduler bank 0 EventSel=34H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_TxR_BL_OCCUPANCY.SCHED1 BL Egress Occupancy; Filter for occupancy from scheduler bank 1 EventSel=34H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0 Counts the number of cycles when there are no "regular" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only. EventSel=18H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1 Counts the number of cycles when there are no "regular" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only. EventSel=18H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2 Counts the number of cycles when there are no "regular" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only. EventSel=18H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3 Counts the number of cycles when there are no "regular" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the regular credits Common high banwidth workloads should be able to make use of all of the regular buffers, but it will be difficult (and uncommon) to make use of both the regular and special buffers at the same time. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only. EventSel=18H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0 Counts the number of cycles when there are no "special" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 0 only. EventSel=19H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1 Counts the number of cycles when there are no "special" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 1 only. EventSel=19H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2 Counts the number of cycles when there are no "special" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 2 only. EventSel=19H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3 Counts the number of cycles when there are no "special" credits available for posting writes from the HA into the iMC. In order to send writes into the memory controller, the HA must first acquire a credit for the iMC's WPQ (write pending queue). This queue is broken into regular credits/buffers that are used by general writes, and "special" requests such as ISOCH writes. This count only tracks the "special" credits. This statistic is generally not interesting for general IA workloads, but may be of interest for understanding the characteristics of systems using ISOCH. One can filter based on the memory controller channel. One or more channels can be tracked at a given time.; Filter for memory controller channel 3 only. EventSel=19H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_ACT_COUNT.BYP Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. EventSel=01H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_ACT_COUNT.RD Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. EventSel=01H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_ACT_COUNT.WR Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. EventSel=01H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_BYP_CMDS.ACT ACT command issued by 2 cycle bypass EventSel=A1H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_BYP_CMDS.CAS CAS command issued by 2 cycle bypass EventSel=A1H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_BYP_CMDS.PRE PRE command issued by 2 cycle bypass EventSel=A1H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.ALL DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM CAS commands issued on this channel. EventSel=04H UMask=0FH
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Read CAS commands issued on this channel (including underfills). EventSel=04H UMask=03H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD_REG DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Read CAS commands issued on this channel. This includes both regular RD CAS commands as well as those with implicit Precharge. AutoPre is only used in systems that are using closed page policy. We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills). EventSel=04H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD_RMM DRAM RD_CAS and WR_CAS Commands EventSel=04H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD_UNDERFILL DRAM RD_CAS and WR_CAS Commands; Counts the number of underfill reads that are issued by the memory controller. This will generally be about the same as the number of partial writes, but may be slightly less because of partials hitting in the WPQ. While it is possible for underfills to be issed in both WMM and RMM, this event counts both. EventSel=04H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.RD_WMM DRAM RD_CAS and WR_CAS Commands EventSel=04H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.WR DRAM RD_CAS and WR_CAS Commands; Counts the total number of DRAM Write CAS commands issued on this channel. EventSel=04H UMask=0CH
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.WR_RMM DRAM RD_CAS and WR_CAS Commands; Counts the total number of Opportunistic" DRAM Write CAS commands issued on this channel while in Read-Major-Mode. EventSel=04H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_CAS_COUNT.WR_WMM DRAM RD_CAS and WR_CAS Commands; Counts the total number or DRAM Write CAS commands issued on this channel while in Write-Major-Mode. EventSel=04H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_DCLOCKTICKS DRAM Clockticks EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_DRAM_PRE_ALL Counts the number of times that the precharge all command was sent. EventSel=06H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_DRAM_REFRESH.HIGH Counts the number of refreshes issued. EventSel=05H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_DRAM_REFRESH.PANIC Counts the number of refreshes issued. EventSel=05H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_ECC_CORRECTABLE_ERRORS Counts the number of ECC errors detected and corrected by the iMC on this channel. This counter is only useful with ECC DRAM devices. This count will increment one time for each correction regardless of the number of bits corrected. The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode. EventSel=09H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_MAJOR_MODES.ISOCH Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; We group these two modes together so that we can use four counters to track each of the major modes at one time. These major modes are used whenever there is an ISOCH txn in the memory controller. In these mode, only ISOCH transactions are processed. EventSel=07H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_MAJOR_MODES.PARTIAL Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode is used to drain starved underfill reads. Regular reads and writes are blocked and only underfill reads will be processed. EventSel=07H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_MAJOR_MODES.READ Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode is the default mode for the iMC, as reads are generally more critical to forward progress than writes. EventSel=07H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_MAJOR_MODES.WRITE Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel. Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is triggered when the WPQ hits high occupancy and causes writes to be higher priority than reads. This can cause blips in the available read bandwidth in the system and temporarily increase read latencies in order to achieve better bus utilizations and higher bandwidth. EventSel=07H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CHANNEL_DLLOFF Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode. EventSel=84H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CHANNEL_PPD Number of cycles when all the ranks in the channel are in PPD mode. If IBT=off is enabled, then this can be used to count those cycles. If it is not enabled, then this can count the number of cycles when that could have been taken advantage of. EventSel=85H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK0 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK1 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK2 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK3 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK4 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK5 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK6 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CKE_CYCLES.RANK7 Number of cycles spent in CKE ON mode. The filter allows you to select a rank to monitor. If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation. Multiple counters will need to be used to track multiple ranks simultaneously. There is no distinction between the different CKE modes (APD, PPDS, PPDF). This can be determined based on the system programming. These events should commonly be used with Invert to get the number of cycles in power saving mode. Edge Detect is also useful here. Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary). EventSel=83H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_CRITICAL_THROTTLE_CYCLES Counts the number of cycles when the iMC is in critical thermal throttling. When this happens, all traffic is blocked. This should be rare unless something bad is going on in the platform. There is no filtering by rank for this event. EventSel=86H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_PCU_THROTTLING UNC_M_POWER_PCU_THROTTLING EventSel=42H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_SELF_REFRESH Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock. This happens in some package C-states. For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing. One use of this is for Monroe technology. Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases. EventSel=43H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK0 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.; Thermal throttling is performed per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by ID. EventSel=41H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK1 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK2 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK3 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK4 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK5 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK6 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_POWER_THROTTLE_CYCLES.RANK7 Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling. It is not possible to distinguish between the two. This can be filtered by rank. If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. EventSel=41H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_PRE_COUNT.BYP Counts the number of DRAM Precharge commands sent on this channel. EventSel=02H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_PRE_COUNT.PAGE_CLOSE Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of the page close counter expiring. This does not include implicit precharge commands sent in auto-precharge mode. EventSel=02H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_PRE_COUNT.PAGE_MISS Counts the number of DRAM Precharge commands sent on this channel.; Counts the number of DRAM Precharge commands sent on this channel as a result of page misses. This does not include explicit precharge commands sent with CAS commands in Auto-Precharge mode. This does not include PRE commands sent as a result of the page close counter expiration. EventSel=02H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_PRE_COUNT.RD Counts the number of DRAM Precharge commands sent on this channel. EventSel=02H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_PRE_COUNT.WR Counts the number of DRAM Precharge commands sent on this channel. EventSel=02H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_PREEMPTION.RD_PREEMPT_RD Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts another read. EventSel=08H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_PREEMPTION.RD_PREEMPT_WR Counts the number of times a read in the iMC preempts another read or write. Generally reads to an open page are issued ahead of requests to closed pages. This improves the page hit rate of the system. However, high priority requests can cause pages of active requests to be closed in order to get them out. This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.; Filter for when a read preempts a write. EventSel=08H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_PRIO.HIGH Read CAS issued with HIGH priority EventSel=A0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_PRIO.LOW Read CAS issued with LOW priority EventSel=A0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_PRIO.MED Read CAS issued with MEDIUM priority EventSel=A0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_PRIO.PANIC Read CAS issued with PANIC NON ISOCH priority (starved) EventSel=A0H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK0 RD_CAS Access to Rank 0; Bank 0 EventSel=B0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK1 RD_CAS Access to Rank 0; Bank 1 EventSel=B0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK2 RD_CAS Access to Rank 0; Bank 2 EventSel=B0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK3 RD_CAS Access to Rank 0; Bank 3 EventSel=B0H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK4 RD_CAS Access to Rank 0; Bank 4 EventSel=B0H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK5 RD_CAS Access to Rank 0; Bank 5 EventSel=B0H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK6 RD_CAS Access to Rank 0; Bank 6 EventSel=B0H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK0.BANK7 RD_CAS Access to Rank 0; Bank 7 EventSel=B0H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK0 RD_CAS Access to Rank 1; Bank 0 EventSel=B1H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK1 RD_CAS Access to Rank 1; Bank 1 EventSel=B1H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK2 RD_CAS Access to Rank 1; Bank 2 EventSel=B1H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK3 RD_CAS Access to Rank 1; Bank 3 EventSel=B1H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK4 RD_CAS Access to Rank 1; Bank 4 EventSel=B1H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK5 RD_CAS Access to Rank 1; Bank 5 EventSel=B1H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK6 RD_CAS Access to Rank 1; Bank 6 EventSel=B1H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK1.BANK7 RD_CAS Access to Rank 1; Bank 7 EventSel=B1H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK0 RD_CAS Access to Rank 2; Bank 0 EventSel=B2H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK1 RD_CAS Access to Rank 2; Bank 1 EventSel=B2H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK2 RD_CAS Access to Rank 2; Bank 2 EventSel=B2H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK3 RD_CAS Access to Rank 2; Bank 3 EventSel=B2H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK4 RD_CAS Access to Rank 2; Bank 4 EventSel=B2H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK5 RD_CAS Access to Rank 2; Bank 5 EventSel=B2H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK6 RD_CAS Access to Rank 2; Bank 6 EventSel=B2H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK2.BANK7 RD_CAS Access to Rank 2; Bank 7 EventSel=B2H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK0 RD_CAS Access to Rank 3; Bank 0 EventSel=B3H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK1 RD_CAS Access to Rank 3; Bank 1 EventSel=B3H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK2 RD_CAS Access to Rank 3; Bank 2 EventSel=B3H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK3 RD_CAS Access to Rank 3; Bank 3 EventSel=B3H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK4 RD_CAS Access to Rank 3; Bank 4 EventSel=B3H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK5 RD_CAS Access to Rank 3; Bank 5 EventSel=B3H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK6 RD_CAS Access to Rank 3; Bank 6 EventSel=B3H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK3.BANK7 RD_CAS Access to Rank 3; Bank 7 EventSel=B3H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK0 RD_CAS Access to Rank 4; Bank 0 EventSel=B4H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK1 RD_CAS Access to Rank 4; Bank 1 EventSel=B4H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK2 RD_CAS Access to Rank 4; Bank 2 EventSel=B4H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK3 RD_CAS Access to Rank 4; Bank 3 EventSel=B4H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK4 RD_CAS Access to Rank 4; Bank 4 EventSel=B4H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK5 RD_CAS Access to Rank 4; Bank 5 EventSel=B4H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK6 RD_CAS Access to Rank 4; Bank 6 EventSel=B4H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK4.BANK7 RD_CAS Access to Rank 4; Bank 7 EventSel=B4H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK0 RD_CAS Access to Rank 5; Bank 0 EventSel=B5H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK1 RD_CAS Access to Rank 5; Bank 1 EventSel=B5H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK2 RD_CAS Access to Rank 5; Bank 2 EventSel=B5H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK3 RD_CAS Access to Rank 5; Bank 3 EventSel=B5H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK4 RD_CAS Access to Rank 5; Bank 4 EventSel=B5H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK5 RD_CAS Access to Rank 5; Bank 5 EventSel=B5H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK6 RD_CAS Access to Rank 5; Bank 6 EventSel=B5H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK5.BANK7 RD_CAS Access to Rank 5; Bank 7 EventSel=B5H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK0 RD_CAS Access to Rank 6; Bank 0 EventSel=B6H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK1 RD_CAS Access to Rank 6; Bank 1 EventSel=B6H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK2 RD_CAS Access to Rank 6; Bank 2 EventSel=B6H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK3 RD_CAS Access to Rank 6; Bank 3 EventSel=B6H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK4 RD_CAS Access to Rank 6; Bank 4 EventSel=B6H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK5 RD_CAS Access to Rank 6; Bank 5 EventSel=B6H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK6 RD_CAS Access to Rank 6; Bank 6 EventSel=B6H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK6.BANK7 RD_CAS Access to Rank 6; Bank 7 EventSel=B6H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK0 RD_CAS Access to Rank 7; Bank 0 EventSel=B7H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK1 RD_CAS Access to Rank 7; Bank 1 EventSel=B7H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK2 RD_CAS Access to Rank 7; Bank 2 EventSel=B7H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK3 RD_CAS Access to Rank 7; Bank 3 EventSel=B7H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK4 RD_CAS Access to Rank 7; Bank 4 EventSel=B7H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK5 RD_CAS Access to Rank 7; Bank 5 EventSel=B7H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK6 RD_CAS Access to Rank 7; Bank 6 EventSel=B7H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_RD_CAS_RANK7.BANK7 RD_CAS Access to Rank 7; Bank 7 EventSel=B7H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_RPQ_CYCLES_NE Counts the number of cycles that the Read Pending Queue is not empty. This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests. EventSel=11H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_RPQ_INSERTS Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. EventSel=10H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_VMSE_MXB_WR_OCCUPANCY VMSE MXB write buffer occupancy EventSel=91H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_VMSE_WR_PUSH.RMM VMSE WR PUSH issued; VMSE write PUSH issued in RMM EventSel=90H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_VMSE_WR_PUSH.WMM VMSE WR PUSH issued; VMSE write PUSH issued in WMM EventSel=90H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WMM_TO_RMM.LOW_THRESH Transition from WMM to RMM because of low threshold; Transition from WMM to RMM because of starve counter EventSel=C0H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WMM_TO_RMM.STARVE Transition from WMM to RMM because of low threshold EventSel=C0H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WMM_TO_RMM.VMSE_RETRY Transition from WMM to RMM because of low threshold EventSel=C0H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WPQ_CYCLES_FULL Counts the number of cycles when the Write Pending Queue is full. When the WPQ is full, the HA will not be able to issue any additional read requests into the iMC. This count should be similar count in the HA which tracks the number of cycles that the HA has no WPQ credits, just somewhat smaller to account for the credit return overhead. EventSel=22H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_WPQ_CYCLES_NE Counts the number of cycles that the Write Pending Queue is not empty. This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. EventSel=21H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_WPQ_INSERTS Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. EventSel=20H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_WPQ_READ_HIT Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections. EventSel=23H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_WPQ_WRITE_HIT Counts the number of times a request hits in the WPQ (write-pending queue). The iMC allows writes and reads to pass up other writes to different addresses. Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address. When reads hit, they are able to directly pull their data from the WPQ instead of going to memory. Writes that hit will overwrite the existing data. Partial writes that hit will not need to do underfill reads and will simply update their relevant sections. EventSel=24H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK0 WR_CAS Access to Rank 0; Bank 0 EventSel=B8H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK1 WR_CAS Access to Rank 0; Bank 1 EventSel=B8H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK2 WR_CAS Access to Rank 0; Bank 2 EventSel=B8H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK3 WR_CAS Access to Rank 0; Bank 3 EventSel=B8H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK4 WR_CAS Access to Rank 0; Bank 4 EventSel=B8H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK5 WR_CAS Access to Rank 0; Bank 5 EventSel=B8H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK6 WR_CAS Access to Rank 0; Bank 6 EventSel=B8H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK0.BANK7 WR_CAS Access to Rank 0; Bank 7 EventSel=B8H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK0 WR_CAS Access to Rank 1; Bank 0 EventSel=B9H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK1 WR_CAS Access to Rank 1; Bank 1 EventSel=B9H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK2 WR_CAS Access to Rank 1; Bank 2 EventSel=B9H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK3 WR_CAS Access to Rank 1; Bank 3 EventSel=B9H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK4 WR_CAS Access to Rank 1; Bank 4 EventSel=B9H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK5 WR_CAS Access to Rank 1; Bank 5 EventSel=B9H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK6 WR_CAS Access to Rank 1; Bank 6 EventSel=B9H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK1.BANK7 WR_CAS Access to Rank 1; Bank 7 EventSel=B9H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK0 WR_CAS Access to Rank 2; Bank 0 EventSel=BAH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK1 WR_CAS Access to Rank 2; Bank 1 EventSel=BAH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK2 WR_CAS Access to Rank 2; Bank 2 EventSel=BAH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK3 WR_CAS Access to Rank 2; Bank 3 EventSel=BAH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK4 WR_CAS Access to Rank 2; Bank 4 EventSel=BAH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK5 WR_CAS Access to Rank 2; Bank 5 EventSel=BAH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK6 WR_CAS Access to Rank 2; Bank 6 EventSel=BAH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK2.BANK7 WR_CAS Access to Rank 2; Bank 7 EventSel=BAH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK0 WR_CAS Access to Rank 3; Bank 0 EventSel=BBH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK1 WR_CAS Access to Rank 3; Bank 1 EventSel=BBH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK2 WR_CAS Access to Rank 3; Bank 2 EventSel=BBH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK3 WR_CAS Access to Rank 3; Bank 3 EventSel=BBH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK4 WR_CAS Access to Rank 3; Bank 4 EventSel=BBH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK5 WR_CAS Access to Rank 3; Bank 5 EventSel=BBH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK6 WR_CAS Access to Rank 3; Bank 6 EventSel=BBH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK3.BANK7 WR_CAS Access to Rank 3; Bank 7 EventSel=BBH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK0 WR_CAS Access to Rank 4; Bank 0 EventSel=BCH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK1 WR_CAS Access to Rank 4; Bank 1 EventSel=BCH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK2 WR_CAS Access to Rank 4; Bank 2 EventSel=BCH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK3 WR_CAS Access to Rank 4; Bank 3 EventSel=BCH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK4 WR_CAS Access to Rank 4; Bank 4 EventSel=BCH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK5 WR_CAS Access to Rank 4; Bank 5 EventSel=BCH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK6 WR_CAS Access to Rank 4; Bank 6 EventSel=BCH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK4.BANK7 WR_CAS Access to Rank 4; Bank 7 EventSel=BCH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK0 WR_CAS Access to Rank 5; Bank 0 EventSel=BDH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK1 WR_CAS Access to Rank 5; Bank 1 EventSel=BDH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK2 WR_CAS Access to Rank 5; Bank 2 EventSel=BDH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK3 WR_CAS Access to Rank 5; Bank 3 EventSel=BDH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK4 WR_CAS Access to Rank 5; Bank 4 EventSel=BDH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK5 WR_CAS Access to Rank 5; Bank 5 EventSel=BDH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK6 WR_CAS Access to Rank 5; Bank 6 EventSel=BDH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK5.BANK7 WR_CAS Access to Rank 5; Bank 7 EventSel=BDH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK0 WR_CAS Access to Rank 6; Bank 0 EventSel=BEH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK1 WR_CAS Access to Rank 6; Bank 1 EventSel=BEH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK2 WR_CAS Access to Rank 6; Bank 2 EventSel=BEH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK3 WR_CAS Access to Rank 6; Bank 3 EventSel=BEH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK4 WR_CAS Access to Rank 6; Bank 4 EventSel=BEH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK5 WR_CAS Access to Rank 6; Bank 5 EventSel=BEH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK6 WR_CAS Access to Rank 6; Bank 6 EventSel=BEH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK6.BANK7 WR_CAS Access to Rank 6; Bank 7 EventSel=BEH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK0 WR_CAS Access to Rank 7; Bank 0 EventSel=BFH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK1 WR_CAS Access to Rank 7; Bank 1 EventSel=BFH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK2 WR_CAS Access to Rank 7; Bank 2 EventSel=BFH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK3 WR_CAS Access to Rank 7; Bank 3 EventSel=BFH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK4 WR_CAS Access to Rank 7; Bank 4 EventSel=BFH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK5 WR_CAS Access to Rank 7; Bank 5 EventSel=BFH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK6 WR_CAS Access to Rank 7; Bank 6 EventSel=BFH UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_M_WR_CAS_RANK7.BANK7 WR_CAS Access to Rank 7; Bank 7 EventSel=BFH UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_M_WRONG_MM Not getting the requested Major Mode EventSel=C1H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_I_ADDRESS_MATCH.MERGE_COUNT Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When two requests to the same address from the same source are received back to back, it is possible to merge the two of them together. EventSel=17H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_ADDRESS_MATCH.STALL_COUNT Counts the number of times when an inbound write (from a device to memory or another device) had an address match with another request in the write cache.; When it is not possible to merge two conflicting requests, a stall event occurs. This is bad for performance. EventSel=17H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. EventSel=14H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE Accumulates the number of writes that have acquired ownership but have not yet returned their data to the uncore. These writes are generally queued up in the switch trying to get to the head of their queues so that they can post their data. The queue occuapancy increments when the ACK is received, and decrements when either the data is returned OR a tickle is received and ownership is released. Note that a single tickle can result in multiple decrements.; Tracks all requests from any source port. EventSel=14H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_CACHE_OWN_OCCUPANCY.ANY Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks all requests from any source port. EventSel=13H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_OWN_OCCUPANCY.SOURCE Accumulates the number of writes (and write prefetches) that are outstanding in the uncore trying to acquire ownership in each cycle. This can be used with the write transaction count to calculate the average write latency in the uncore. The occupancy increments when a write request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. EventSel=13H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_CACHE_READ_OCCUPANCY.ANY Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks all requests from any source port. EventSel=10H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_READ_OCCUPANCY.SOURCE Accumulates the number of reads that are outstanding in the uncore in each cycle. This can be used with the read transaction count to calculate the average read latency in the uncore. The occupancy increments when a read request is issued, and decrements when the data is returned.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. EventSel=10H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_CACHE_TOTAL_OCCUPANCY.ANY Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests from any source port. EventSel=12H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE Accumulates the number of reads and writes that are outstanding in the uncore in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. EventSel=12H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_CACHE_WRITE_OCCUPANCY.ANY Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks all requests from any source port. EventSel=11H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE Accumulates the number of writes (and write prefetches) that are outstanding in the uncore in each cycle. This can be used with the transaction count event to calculate the average latency in the uncore. The occupancy increments when the ownership fetch/prefetch is issued, and decrements the data is returned to the uncore.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. EventSel=11H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_CLOCKTICKS Number of clocks in the IRP. EventSel=00H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_AK_CYCLES_FULL Counts the number of cycles when the AK Ingress is full. This queue is where the IRP receives responses from R2PCIe (the ring). EventSel=0BH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_AK_INSERTS Counts the number of allocations into the AK Ingress. This queue is where the IRP receives responses from R2PCIe (the ring). EventSel=0AH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_AK_OCCUPANCY Accumulates the occupancy of the AK Ingress in each cycles. This queue is where the IRP receives responses from R2PCIe (the ring). EventSel=0CH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_DRS_CYCLES_FULL Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=04H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_DRS_INSERTS Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=01H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_DRS_OCCUPANCY Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=07H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCB_CYCLES_FULL Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=05H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCB_INSERTS Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=02H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCB_OCCUPANCY Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=08H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCS_CYCLES_FULL Counts the number of cycles when the BL Ingress is full. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=06H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCS_INSERTS Counts the number of allocations into the BL Ingress. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=03H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_RxR_BL_NCS_OCCUPANCY Accumulates the occupancy of the BL Ingress in each cycles. This queue is where the IRP receives data from R2PCIe (the ring). It is used for data returns from read requets as well as outbound MMIO writes. EventSel=09H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_TICKLES.LOST_OWNERSHIP Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of requests that lost ownership as a result of a tickle. When a tickle comes in, if the request is not at the head of the queue in the switch, then that request as well as any requests behind it in the switch queue will lose ownership and have to re-acquire it later when they get to the head of the queue. This will therefore track the number of requests that lost ownership and not just the number of tickles. EventSel=16H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_TICKLES.TOP_OF_QUEUE Counts the number of tickles that are received. This is for both explicit (from Cbo) and implicit (internal conflict) tickles.; Tracks the number of cases when a tickle was received but the requests was at the head of the queue in the switch. In this case, data is returned rather than releasing ownership. EventSel=16H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_TRANSACTIONS.ORDERINGQ Counts the number of "Inbound" transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only those requests that come from the port specified in the IRP_PmonFilter.OrderingQ register. This register allows one to select one specific queue. It is not possible to monitor multiple queues at a time. If this bit is not set, then requests from all sources will be counted. EventSel=15H UMask=08H
    Counter=0,1
    Uncore
    UNC_I_TRANSACTIONS.PD_PREFETCHES Inbound Transaction Count: Read Prefetches EventSel=15H UMask=04H
    Counter=0,1
    Uncore
    UNC_I_TRANSACTIONS.RD_PREFETCHES Counts the number of "Inbound" transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks the number of read prefetches. EventSel=15H UMask=04H
    Counter=0,1
    Uncore
    UNC_I_TRANSACTIONS.READS Counts the number of "Inbound" transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Tracks only read requests (not including read prefetches). EventSel=15H UMask=01H
    Counter=0,1
    Uncore
    UNC_I_TRANSACTIONS.WRITES Counts the number of "Inbound" transactions from the IRP to the Uncore. This can be filtered based on request type in addition to the source queue. Note the special filtering equation. We do OR-reduction on the request type. If the SOURCE bit is set, then we also do AND qualification based on the source portID.; Trackes only write requests. Each write request should have a prefetch, so there is no need to explicitly track these requests. For writes that are tickled and have to retry, the counter will be incremented for each retry. EventSel=15H UMask=02H
    Counter=0,1
    Uncore
    UNC_I_TxR_AD_STALL_CREDIT_CYCLES Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available. EventSel=18H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_TxR_BL_STALL_CREDIT_CYCLES Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available. EventSel=19H UMask=00H
    Counter=0,1
    Uncore
    UNC_I_TxR_DATA_INSERTS_NCB Counts the number of requests issued to the switch (towards the devices). EventSel=0EH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_TxR_DATA_INSERTS_NCS Counts the number of requests issued to the switch (towards the devices). EventSel=0FH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_TxR_REQUEST_OCCUPANCY Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices). This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests. EventSel=0DH UMask=00H
    Counter=0,1
    Uncore
    UNC_I_WRITE_ORDERING_STALL_CYCLES Counts the number of cycles when there are pending write ACK's in the switch but the switch->IRP pipeline is not utilized. EventSel=1AH UMask=00H
    Counter=0,1
    Uncore
    UNC_P_CLOCKTICKS The PCU runs off a fixed 800 MHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time. EventSel=00H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE0_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=70H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE1_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=71H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE10_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=7AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE11_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=7BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE12_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=7CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE13_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=7DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE14_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=7EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE2_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=72H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE3_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=73H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE4_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=74H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE5_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=75H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE6_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=76H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE7_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=77H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE8_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=78H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_CORE9_TRANSITION_CYCLES Number of cycles spent performing core C state transitions. There is one event per core. EventSel=79H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE0 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=17H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE1 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=18H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE10 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=21H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE11 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=22H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE12 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=23H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE13 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=24H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE14 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=25H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE2 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=19H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE3 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE4 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE5 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE6 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE7 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE8 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=1FH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DELAYED_C_STATE_ABORT_CORE9 Number of times that a deep C state was requested, but the delayed C state algorithm "rejected" the deep sleep state. In other words, a wake event occurred before the timer expired that causes a transition into the deeper C state. EventSel=20H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE0 Counts the number of times when a configurable cores had a C-state demotion EventSel=1EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE1 Counts the number of times when a configurable cores had a C-state demotion EventSel=1FH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE10 Counts the number of times when a configurable cores had a C-state demotion EventSel=42H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE11 Counts the number of times when a configurable cores had a C-state demotion EventSel=43H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE12 Counts the number of times when a configurable cores had a C-state demotion EventSel=44H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE13 Counts the number of times when a configurable cores had a C-state demotion EventSel=45H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE14 Counts the number of times when a configurable cores had a C-state demotion EventSel=46H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE2 Counts the number of times when a configurable cores had a C-state demotion EventSel=20H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE3 Counts the number of times when a configurable cores had a C-state demotion EventSel=21H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE4 Counts the number of times when a configurable cores had a C-state demotion EventSel=22H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE5 Counts the number of times when a configurable cores had a C-state demotion EventSel=23H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE6 Counts the number of times when a configurable cores had a C-state demotion EventSel=24H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE7 Counts the number of times when a configurable cores had a C-state demotion EventSel=25H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE8 Counts the number of times when a configurable cores had a C-state demotion EventSel=40H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_DEMOTIONS_CORE9 Counts the number of times when a configurable cores had a C-state demotion EventSel=41H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_BAND0_CYCLES Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency. EventSel=0BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_BAND1_CYCLES Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency. EventSel=0CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_BAND2_CYCLES Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency. EventSel=0DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_BAND3_CYCLES Counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter. One can use all four counters with this event, so it is possible to track up to 4 configurable bands. One can use edge detect in conjunction with this event to track the number of times that we transitioned into a frequency greater than or equal to the configurable frequency. One can also use inversion to track cycles when we were less than the configured frequency. EventSel=0EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MAX_CURRENT_CYCLES Counts the number of cycles when current is the upper limit on frequency. EventSel=07H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES Counts the number of cycles when thermal conditions are the upper limit on frequency. This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input. EventSel=04H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MAX_OS_CYCLES Counts the number of cycles when the OS is the upper limit on frequency. EventSel=06H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MAX_POWER_CYCLES Counts the number of cycles when power is the upper limit on frequency. EventSel=05H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MIN_IO_P_CYCLES Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower. This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW. This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth. EventSel=61H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_MIN_PERF_P_CYCLES Perf P Limit Strongest Lower Limit Cycles EventSel=62H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_FREQ_TRANS_CYCLES Counts the number of cycles when the system is changing frequency. This can not be filtered by thread ID. One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system. EventSel=60H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_MEMORY_PHASE_SHEDDING_CYCLES Counts the number of cycles that the PCU has triggered memory phase shedding. This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency. EventSel=2FH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_EXIT_LATENCY Counts the number of cycles that the package is transitioning from package C2 to C3. EventSel=26H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_EXIT_LATENCY_SEL Package C State Exit Latency EventSel=26H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES Package C State Residency - C0 EventSel=2AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES Package C State Residency - C2 EventSel=2BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES Package C State Residency - C3 EventSel=2CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES Package C State Residency - C6 EventSel=2DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. EventSel=80H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. EventSel=80H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 This is an occupancy event that tracks the number of cores that are in the chosen C-State. It can be used by itself to get the average number of cores in that C-state with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details. EventSel=80H UMask=C0H
    Counter=0,1,2,3
    Uncore
    UNC_P_PROCHOT_EXTERNAL_CYCLES Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip. EventSel=0AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_PROCHOT_INTERNAL_CYCLES Counts the number of cycles that we are in Interal PROCHOT mode. This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip. EventSel=09H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_TOTAL_TRANSITION_CYCLES Number of cycles spent performing core C state transitions across all cores. EventSel=63H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_VOLT_TRANS_CYCLES_CHANGE Counts the number of cycles when the system is changing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. This event is calculated by or'ing together the increasing and decreasing events. EventSel=03H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_VOLT_TRANS_CYCLES_DECREASE Counts the number of cycles when the system is decreasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. EventSel=02H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_VOLT_TRANS_CYCLES_INCREASE Counts the number of cycles when the system is increasing voltage. There is no filtering supported with this event. One can use it as a simple event, or use it conjunction with the occupancy events to monitor the number of cores or threads that were impacted by the transition. EventSel=01H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_P_VR_HOT_CYCLES VR Hot EventSel=32H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_CLOCKTICKS Counts the number of clocks in the QPI LL. This clock runs at 1/8th the "GT/s" speed of the QPI link. For example, a 8GT/s link will have qfclk or 1GHz. JKT does not support dynamic link speeds, so this frequency is fixed. EventSel=14H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_CTO_COUNT Counts the number of CTO (cluster trigger outs) events that were asserted across the two slots. If both slots trigger in a given cycle, the event will increment by 2. You can use edge detect to count the number of cases when both events triggered. EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_CREDITS Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits. Had there been enough credits, the spawn would have worked as the RBT bit was set and the RBT tag matched. EventSel=13H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and there weren't enough Egress credits. The valid bit was set. EventSel=13H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because there were not enough Egress credits AND the RBT bit was not set, but the RBT tag matched. EventSel=13H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match, the valid bit was not set and there weren't enough Egress credits. EventSel=13H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_MISS Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match although the valid bit was set and there were enough Egress credits. EventSel=13H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the route-back table (RBT) specified that the transaction should not trigger a direct2core tranaction. This is common for IO transactions. There were enough Egress credits and the RBT tag matched but the valid bit was not set. EventSel=13H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn failed because the RBT tag did not match and the valid bit was not set although there were enough Egress credits. EventSel=13H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT Counts the number of DRS packets that we attempted to do direct2core on. There are 4 mutually exlusive filters. Filter [0] can be used to get successful spawns, while [1:3] provide the different failure cases. Note that this does not count packets that are not candidates for Direct2Core. The only candidates for Direct2Core are DRS packets destined for Cbos.; The spawn was successful. There were sufficient credits, the RBT valid bit was set and there was an RBT tag match. The message was marked to spawn direct2core. EventSel=13H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_L1_POWER_CYCLES Number of QPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a QPI link. Use edge detect to count the number of instances when the QPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode. EventSel=12H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MATCH_MASK UNC_Q_MATCH_MASK EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.AnyDataC UNC_Q_MESSAGE.DRS.AnyDataC EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.AnyResp UNC_Q_MESSAGE.DRS.AnyResp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.AnyResp11flits UNC_Q_MESSAGE.DRS.AnyResp11flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.AnyResp9flits UNC_Q_MESSAGE.DRS.AnyResp9flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_E UNC_Q_MESSAGE.DRS.DataC_E EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_E_Cmp UNC_Q_MESSAGE.DRS.DataC_E_Cmp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_F UNC_Q_MESSAGE.DRS.DataC_F EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_F_Cmp UNC_Q_MESSAGE.DRS.DataC_F_Cmp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.DataC_M UNC_Q_MESSAGE.DRS.DataC_M EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.WbEData UNC_Q_MESSAGE.DRS.WbEData EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.WbIData UNC_Q_MESSAGE.DRS.WbIData EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.DRS.WbSData UNC_Q_MESSAGE.DRS.WbSData EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.AnyReq UNC_Q_MESSAGE.HOM.AnyReq EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.AnyResp UNC_Q_MESSAGE.HOM.AnyResp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespFwd UNC_Q_MESSAGE.HOM.RespFwd EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespFwdI UNC_Q_MESSAGE.HOM.RespFwdI EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespFwdIWb UNC_Q_MESSAGE.HOM.RespFwdIWb EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespFwdS UNC_Q_MESSAGE.HOM.RespFwdS EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespFwdSWb UNC_Q_MESSAGE.HOM.RespFwdSWb EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespIWb UNC_Q_MESSAGE.HOM.RespIWb EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.HOM.RespSWb UNC_Q_MESSAGE.HOM.RespSWb EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCB.AnyInt UNC_Q_MESSAGE.NCB.AnyInt EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCB.AnyMsg UNC_Q_MESSAGE.NCB.AnyMsg EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCB.AnyMsg11flits UNC_Q_MESSAGE.NCB.AnyMsg11flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCB.AnyMsg9flits UNC_Q_MESSAGE.NCB.AnyMsg9flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCS.AnyMsg1or2flits UNC_Q_MESSAGE.NCS.AnyMsg1or2flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCS.AnyMsg3flits UNC_Q_MESSAGE.NCS.AnyMsg3flits EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NCS.NcRd UNC_Q_MESSAGE.NCS.NcRd EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.NDR.AnyCmp UNC_Q_MESSAGE.NDR.AnyCmp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_MESSAGE.SNP.AnySnp UNC_Q_MESSAGE.SNP.AnySnp EventSel=38H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_BYPASSED Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency. EventSel=09H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CRC_ERRORS.LINK_INIT Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during link initialization. EventSel=03H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CRC_ERRORS.NORMAL_OP Number of CRC errors detected in the QPI Agent. Each QPI flit incorporates 8 bits of CRC for error detection. This counts the number of flits where the CRC was able to detect an error. After an error has been detected, the QPI agent will send a request to the transmitting socket to resend the flit (as well as any flits that came after it).; CRC errors detected during normal operation. EventSel=03H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the DRS message class. EventSel=1EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the HOM message class. EventSel=1EH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCB message class. EventSel=1EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NCS message class. EventSel=1EH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the NDR message class. EventSel=1EH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN0 credit for the SNP message class. EventSel=1EH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the DRS message class. EventSel=39H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the HOM message class. EventSel=39H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCB message class. EventSel=39H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NCS message class. EventSel=39H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the NDR message class. EventSel=39H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed.; VN1 credit for the SNP message class. EventSel=39H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CREDITS_CONSUMED_VNA Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer). This includes packets that went through the RxQ and those that were bypasssed. EventSel=1DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. EventSel=0AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_DRS.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only. EventSel=0FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_DRS.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors DRS flits only. EventSel=0FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_HOM.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only. EventSel=12H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_HOM.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors HOM flits only. EventSel=12H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NCB.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only. EventSel=10H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NCB.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCB flits only. EventSel=10H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NCS.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only. EventSel=11H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NCS.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NCS flits only. EventSel=11H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NDR.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only. EventSel=14H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_NDR.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors NDR flits only. EventSel=14H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_SNP.VN0 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only. EventSel=13H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_CYCLES_NE_SNP.VN1 Counts the number of cycles that the QPI RxQ was not empty. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy Accumulator event to calculate the average occupancy. This monitors SNP flits only. EventSel=13H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G0.DATA Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flitsreceived over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets. EventSel=01H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G0.IDLE Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of flits received over QPI that do not hold protocol payload. When QPI is not in a power saving state, it continuously transmits flits across the link. When there are no protocol flits to send, it will send IDLE and NULL flits across. These flits sometimes do carry a payload, such as credit returns, but are generall not considered part of the QPI bandwidth. EventSel=01H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G0.NON_DATA Counts the number of flits received from the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits received across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets. EventSel=01H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.DRS Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. EventSel=02H UMask=18H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.DRS_DATA Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header). EventSel=02H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.DRS_NONDATA Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits received over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits received over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers. EventSel=02H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.HOM Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits received over QPI on the home channel. EventSel=02H UMask=06H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.HOM_NONREQ Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits received over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that. EventSel=02H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.HOM_REQ Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request received over QPI on the home channel. This basically counts the number of remote memory requests received over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses. EventSel=02H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G1.SNP Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits received over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are received on the home channel. EventSel=02H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NCB Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI. EventSel=03H UMask=0CH
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NCB_DATA Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not the NCB headers. EventSel=03H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NCB_NONDATA Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers. EventSel=03H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NCS Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits received over QPI. This includes extended headers. EventSel=03H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NDR_AD Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring. EventSel=03H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_FLITS_G2.NDR_AK Counts the number of flits received from the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits received over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket. EventSel=03H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. EventSel=08H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_DRS Rx Flit Buffer Allocations - DRS EventSel=09H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_DRS.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits. EventSel=09H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_DRS.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only DRS flits. EventSel=09H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_HOM Rx Flit Buffer Allocations - HOM EventSel=0CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_HOM.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits. EventSel=0CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_HOM.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only HOM flits. EventSel=0CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCB Rx Flit Buffer Allocations - NCB EventSel=0AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCB.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits. EventSel=0AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCB.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCB flits. EventSel=0AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCS Rx Flit Buffer Allocations - NCS EventSel=0BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCS.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits. EventSel=0BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NCS.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NCS flits. EventSel=0BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NDR Rx Flit Buffer Allocations - NDR EventSel=0EH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NDR.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits. EventSel=0EH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_NDR.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only NDR flits. EventSel=0EH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_SNP Rx Flit Buffer Allocations - SNP EventSel=0DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_SNP.VN0 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits. EventSel=0DH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_INSERTS_SNP.VN1 Number of allocations into the QPI Rx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. This monitors only SNP flits. EventSel=0DH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. EventSel=0BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_DRS RxQ Occupancy - DRS EventSel=15H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_DRS.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only. EventSel=15H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_DRS.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors DRS flits only. EventSel=15H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_HOM RxQ Occupancy - HOM EventSel=18H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_HOM.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only. EventSel=18H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_HOM.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors HOM flits only. EventSel=18H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCB RxQ Occupancy - NCB EventSel=16H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCB.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only. EventSel=16H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCB.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCB flits only. EventSel=16H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCS RxQ Occupancy - NCS EventSel=17H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCS.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only. EventSel=17H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NCS.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NCS flits only. EventSel=17H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NDR RxQ Occupancy - NDR EventSel=1AH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NDR.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only. EventSel=1AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_NDR.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors NDR flits only. EventSel=1AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_SNP RxQ Occupancy - SNP EventSel=19H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_SNP.VN0 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only. EventSel=19H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_OCCUPANCY_SNP.VN1 Accumulates the number of elements in the QPI RxQ in each cycle. Generally, when data is transmitted across QPI, it will bypass the RxQ and pass directly to the ring interface. If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency. This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime. This monitors SNP flits only. EventSel=19H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_DRS Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_HOM Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_NCB Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_NCS Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_NDR Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.BGF_SNP Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=35H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled a packet because there were insufficient BGF credits. For details on a message class granularity, use the Egress Credit Occupancy events. EventSel=35H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN0.GV Number of stalls trying to send to R3QPI on Virtual Network 0; Stalled because a GV transition (frequency transition) was taking place. EventSel=35H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_DRS Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the HOM message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_HOM Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the DRS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_NCB Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the SNP message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_NCS Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NDR message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_NDR Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCS message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL_STALLS_VN1.BGF_SNP Number of stalls trying to send to R3QPI on Virtual Network 1.; Stalled a packet from the NCB message class because there were not enough BGF credits. In bypass mode, we will stall on the packet boundary, while in RxQ mode we will stall on the flit boundary. EventSel=3AH UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL0_POWER_CYCLES Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event. EventSel=0FH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_RxL0P_POWER_CYCLES Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. EventSel=10H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_BYPASSED Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the QPI Link. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. EventSel=05H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is almost full, we block some but not all packets. EventSel=02H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_CRC_NO_CREDITS.FULL Number of cycles when the Tx side ran out of Link Layer Retry credits, causing the Tx to stall.; When LLR is totally full, we are not allowed to send any packets. EventSel=02H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_CYCLES_NE Counts the number of cycles when the TxQ is not empty. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. EventSel=06H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G0.DATA Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data flits transmitted over QPI. Each flit contains 64b of data. This includes both DRS and NCB data flits (coherent and non-coherent). This can be used to calculate the data bandwidth of the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This does not include the header flits that go in data packets. EventSel=00H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G0.NON_DATA Counts the number of flits transmitted across the QPI Link. It includes filters for Idle, protocol, and Data Flits. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL non-data flits transmitted across QPI. This basically tracks the protocol overhead on the QPI link. One can get a good picture of the QPI-link characteristics by evaluating the protocol flits, data flits, and idle/null flits. This includes the header flits for data packets. EventSel=00H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.DRS Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. EventSel=00H UMask=18H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.DRS_DATA Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of data flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the data flits (not the header). EventSel=00H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.DRS_NONDATA Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of protocol flits transmitted over QPI on the DRS (Data Response) channel. DRS flits are used to transmit data with coherency. This does not count data flits transmitted over the NCB channel which transmits non-coherent data. This includes only the header flits (not the data). This includes extended headers. EventSel=00H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.HOM Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of flits transmitted over QPI on the home channel. EventSel=00H UMask=06H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.HOM_NONREQ Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of non-request flits transmitted over QPI on the home channel. These are most commonly snoop responses, and this event can be used as a proxy for that. EventSel=00H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.HOM_REQ Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of data request transmitted over QPI on the home channel. This basically counts the number of remote memory requests transmitted over QPI. In conjunction with the local read count in the Home Agent, one can calculate the number of LLC Misses. EventSel=00H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G1.SNP Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for SNP, HOM, and DRS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the number of snoop request flits transmitted over QPI. These requests are contained in the snoop channel. This does not include snoop responses, which are transmitted on the home channel. EventSel=00H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NCB Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass flits. These packets are generally used to transmit non-coherent data across QPI. EventSel=01H UMask=0CH
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NCB_DATA Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass data flits. These flits are generally used to transmit non-coherent data across QPI. This does not include a count of the DRS (coherent) data flits. This only counts the data flits, not te NCB headers. EventSel=01H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NCB_NONDATA Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of Non-Coherent Bypass non-data flits. These packets are generally used to transmit non-coherent data across QPI, and the flits counted here are for headers and other non-data flits. This includes extended headers. EventSel=01H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NCS Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Number of NCS (non-coherent standard) flits transmitted over QPI. This includes extended headers. EventSel=01H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NDR_AD Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets to the local socket which use the AK ring. EventSel=01H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_FLITS_G2.NDR_AK Counts the number of flits trasmitted across the QPI Link. This is one of three "groups" that allow us to track flits. It includes filters for NDR, NCB, and NCS message classes. Each "flit" is made up of 80 bits of information (in addition to some ECC data). In full-width (L0) mode, flits are made up of four "fits", each of which contains 20 bits of data (along with some additional ECC data). In half-width (L0p) mode, the fits are only 10 bits, and therefore it takes twice as many fits to transmit a flit. When one talks about QPI "speed" (for example, 8.0 GT/s), the "transfers" here refer to "fits". Therefore, in L0, the system will transfer 1 "flit" at the rate of 1/4th the QPI speed. One can calculate the bandwidth of the link by taking: flits*80b/time. Note that this is not the same as "data" bandwidth. For example, when we are transfering a 64B cacheline across QPI, we will break it into 9 flits -- 1 with header information and 8 with 64 bits of actual "data" and an additional 16 bits of other information. To calculate "data" bandwidth, one should therefore do: data flits * 8B / time.; Counts the total number of flits transmitted over the NDR (Non-Data Response) channel. This channel is used to send a variety of protocol flits including grants and completions. This is only for NDR packets destined for Route-thru to a remote socket. EventSel=01H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_INSERTS Number of allocations into the QPI Tx Flit Buffer. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime. EventSel=04H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL_OCCUPANCY Accumulates the number of flits in the TxQ. Generally, when data is transmitted across QPI, it will bypass the TxQ and pass directly to the link. However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ. EventSel=07H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL0_POWER_CYCLES Number of QPI qfclk cycles spent in L0 power mode in the Link Layer. L0 is the default mode which provides the highest performance with the most power. Use edge detect to count the number of instances that the link entered L0. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. The phy layer sometimes leaves L0 for training, which will not be captured by this event. EventSel=0CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxL0P_POWER_CYCLES Number of QPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the QPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize QPI for snoops and their responses. Use edge detect to count the number of instances when the QPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. EventSel=0DH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD. EventSel=26H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Home messages on AD. EventSel=26H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD. EventSel=22H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for HOM messages on AD. EventSel=22H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD. EventSel=28H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for NDR messages on AD. EventSel=28H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD. EventSel=24H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO for NDR messages on AD. EventSel=24H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD. EventSel=27H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1 Number of link layer credits into the R3 (for transactions across the BGF) acquired each cycle. Flow Control FIFO for Snoop messages on AD. EventSel=27H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD. EventSel=23H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of link layer credits into the R3 (for transactions across the BGF) available in each cycle. Flow Control FIFO fro Snoop messages on AD. EventSel=23H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED Number of credits into the R3 (for transactions across the BGF) acquired each cycle. Local NDR message class to AK Egress. EventSel=29H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0 R3QPI Egress Credit Occupancy - AK NDR: for VN0 EventSel=29H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1 R3QPI Egress Credit Occupancy - AK NDR: for VN1 EventSel=29H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. Local NDR message class to AK Egress. EventSel=25H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0 R3QPI Egress Credit Occupancy - AK NDR: for VN0 EventSel=25H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1 R3QPI Egress Credit Occupancy - AK NDR: for VN1 EventSel=25H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress. EventSel=2AH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress. EventSel=2AH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. DRS message class to BL Egress. EventSel=2AH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress. EventSel=1FH UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress. EventSel=1FH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. DRS message class to BL Egress. EventSel=1FH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress. EventSel=2BH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCB message class to BL Egress. EventSel=2BH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress. EventSel=20H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCB message class to BL Egress. EventSel=20H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress. EventSel=2CH UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1 Number of credits into the R3 (for transactions across the BGF) acquired each cycle. NCS message class to BL Egress. EventSel=2CH UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress. EventSel=21H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1 Occupancy event that tracks the number of credits into the R3 (for transactions across the BGF) available in each cycle. NCS message class to BL Egress. EventSel=21H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY Number of VNA credits in the Rx side that are waitng to be returned back across the link. EventSel=1BH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_Q_VNA_CREDIT_RETURNS Number of VNA credits returned. EventSel=1CH UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_R2_CLOCKTICKS Counts the number of uclks in the R2PCIe uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the R2PCIe is close to the Ubox, they generally should not diverge by more than a handful of cycles. EventSel=01H UMask=00H
    Counter=0,1,2,3
    Uncore
    UNC_R2_IIO_CREDITS_ACQUIRED.DRS Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class. EventSel=33H UMask=08H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_ACQUIRED.NCB Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class. EventSel=33H UMask=10H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_ACQUIRED.NCS Counts the number of credits that are acquired in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class. EventSel=33H UMask=20H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_REJECT.DRS Counts the number of times that a request pending in the BL Ingress attempted to acquire either a NCB or NCS credit to transmit into the IIO, but was rejected because no credits were available. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class. EventSel=34H UMask=08H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_USED.DRS Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the DRS message class. EventSel=32H UMask=08H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_USED.NCB Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCB message class. EventSel=32H UMask=10H
    Counter=0,1
    Uncore
    UNC_R2_IIO_CREDITS_USED.NCS Counts the number of cycles when one or more credits in the R2PCIe agent for sending transactions into the IIO on either NCB or NCS are in use. Transactions from the BL ring going into the IIO Agent must first acquire a credit. These credits are for either the NCB or NCS message classes. NCB, or non-coherent bypass messages are used to transmit data without coherency (and are common). NCS is used for reads to PCIe (and should be used sparingly).; Credits to the IIO for the NCS message class. EventSel=32H UMask=20H
    Counter=0,1
    Uncore
    UNC_R2_RING_AD_USED.CCW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=07H UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CCW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=07H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CCW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=07H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CCW_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=07H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CCW_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=07H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=07H UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=07H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=07H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CW_VR1_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=07H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AD_USED.CW_VR1_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=07H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CCW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=08H UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CCW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=08H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CCW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=08H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CCW_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=08H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CCW_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=08H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=08H UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=08H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=08H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CW_VR1_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=08H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_AK_USED.CW_VR1_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=08H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CCW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=09H UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CCW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=09H UMask=04H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CCW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=09H UMask=08H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CCW_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 1. EventSel=09H UMask=40H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CCW_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 1. EventSel=09H UMask=80H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=09H UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=09H UMask=01H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=09H UMask=02H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CW_VR1_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 1. EventSel=09H UMask=10H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_BL_USED.CW_VR1_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 1. EventSel=09H UMask=20H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_IV_USED.ANY Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity EventSel=0AH UMask=FFH
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_IV_USED.CCW Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity EventSel=0AH UMask=CCH
    Counter=0,1,2,3
    Uncore
    UNC_R2_RING_IV_USED.CW Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity EventSel=0AH UMask=33H
    Counter=0,1,2,3
    Uncore
    UNC_R2_RxR_AK_BOUNCES AK Ingress Bounced EventSel=12H UMask=00H
    Counter=0
    Uncore
    UNC_R2_RxR_AK_BOUNCES.CCW Counts the number of times when a request destined for the AK ingress bounced. EventSel=12H UMask=02H
    Counter=0
    Uncore
    UNC_R2_RxR_AK_BOUNCES.CW Counts the number of times when a request destined for the AK ingress bounced. EventSel=12H UMask=01H
    Counter=0
    Uncore
    UNC_R2_RxR_CYCLES_NE.NCB Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue EventSel=10H UMask=10H
    Counter=0,1
    Uncore
    UNC_R2_RxR_CYCLES_NE.NCS Counts the number of cycles when the R2PCIe Ingress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue EventSel=10H UMask=20H
    Counter=0,1
    Uncore
    UNC_R2_RxR_INSERTS.NCB Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue EventSel=11H UMask=10H
    Counter=0,1
    Uncore
    UNC_R2_RxR_INSERTS.NCS Counts the number of allocations into the R2PCIe Ingress. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue EventSel=11H UMask=20H
    Counter=0,1
    Uncore
    UNC_R2_RxR_OCCUPANCY.DRS Accumulates the occupancy of a given R2PCIe Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the R2PCIe Ingress Not Empty event to calculate average occupancy or the R2PCIe Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue EventSel=13H UMask=08H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_FULL.AD Counts the number of cycles when the R2PCIe Egress buffer is full.; AD Egress Queue EventSel=25H UMask=01H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_FULL.AK Counts the number of cycles when the R2PCIe Egress buffer is full.; AK Egress Queue EventSel=25H UMask=02H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_FULL.BL Counts the number of cycles when the R2PCIe Egress buffer is full.; BL Egress Queue EventSel=25H UMask=04H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_NE.AD Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AD Egress Queue EventSel=23H UMask=01H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_NE.AK Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; AK Egress Queue EventSel=23H UMask=02H
    Counter=0
    Uncore
    UNC_R2_TxR_CYCLES_NE.BL Counts the number of cycles when the R2PCIe Egress is not empty. This tracks one of the three rings that are used by the R2PCIe agent. This can be used in conjunction with the R2PCIe Egress Occupancy Accumulator event in order to calculate average queue occupancy. Only a single Egress queue can be tracked at any given time. It is not possible to filter based on direction or polarity.; BL Egress Queue EventSel=23H UMask=04H
    Counter=0
    Uncore
    UNC_R2_TxR_NACK_CCW.AD AD CounterClockwise Egress Queue EventSel=28H UMask=01H
    Counter=0,1
    Uncore
    UNC_R2_TxR_NACK_CCW.AK AK CounterClockwise Egress Queue EventSel=28H UMask=02H
    Counter=0,1
    Uncore
    UNC_R2_TxR_NACK_CCW.BL BL CounterClockwise Egress Queue EventSel=28H UMask=04H
    Counter=0,1
    Uncore
    UNC_R2_TxR_NACK_CW.AD AD Clockwise Egress Queue EventSel=26H UMask=01H
    Counter=0,1
    Uncore
    UNC_R2_TxR_NACK_CW.AK AK Clockwise Egress Queue EventSel=26H UMask=02H
    Counter=0,1
    Uncore
    UNC_R2_TxR_NACK_CW.BL BL Clockwise Egress Queue EventSel=26H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 10 EventSel=2CH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 11 EventSel=2CH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 12 EventSel=2CH UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 13 EventSel=2CH UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 14&16 EventSel=2CH UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 8 EventSel=2CH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9 No credits available to send to Cbox on the AD Ring (covers higher CBoxes); Cbox 9 EventSel=2CH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 0 EventSel=2BH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 1 EventSel=2BH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 2 EventSel=2BH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 3 EventSel=2BH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 4 EventSel=2BH UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 5 EventSel=2BH UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 6 EventSel=2BH UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7 No credits available to send to Cbox on the AD Ring (covers lower CBoxes); Cbox 7 EventSel=2BH UMask=80H
    Counter=0,1
    Uncore
    UNC_R3_CLOCKTICKS Counts the number of uclks in the QPI uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the QPI Agent is close to the Ubox, they generally should not diverge by more than a handful of cycles. EventSel=01H UMask=00H
    Counter=0,1,2
    Uncore
    UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0 No credits available to send to either HA or R2 on the BL Ring; HA0 EventSel=2FH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1 No credits available to send to either HA or R2 on the BL Ring; HA1 EventSel=2FH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB No credits available to send to either HA or R2 on the BL Ring; R2 NCB Messages EventSel=2FH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS No credits available to send to either HA or R2 on the BL Ring; R2 NCS Messages EventSel=2FH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM No credits available to send to QPI0 on the AD Ring; VN0 HOM Messages EventSel=29H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR No credits available to send to QPI0 on the AD Ring; VN0 NDR Messages EventSel=29H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP No credits available to send to QPI0 on the AD Ring; VN0 SNP Messages EventSel=29H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM No credits available to send to QPI0 on the AD Ring; VN1 HOM Messages EventSel=29H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR No credits available to send to QPI0 on the AD Ring; VN1 NDR Messages EventSel=29H UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP No credits available to send to QPI0 on the AD Ring; VN1 SNP Messages EventSel=29H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA No credits available to send to QPI0 on the AD Ring; VNA EventSel=29H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM No credits available to send to QPI0 on the BL Ring; VN0 HOM Messages EventSel=2DH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR No credits available to send to QPI0 on the BL Ring; VN0 NDR Messages EventSel=2DH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP No credits available to send to QPI0 on the BL Ring; VN0 SNP Messages EventSel=2DH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM No credits available to send to QPI0 on the BL Ring; VN1 HOM Messages EventSel=2DH UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR No credits available to send to QPI0 on the BL Ring; VN1 NDR Messages EventSel=2DH UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP No credits available to send to QPI0 on the BL Ring; VN1 SNP Messages EventSel=2DH UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA No credits available to send to QPI0 on the BL Ring; VNA EventSel=2DH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM No credits available to send to QPI1 on the AD Ring; VN0 HOM Messages EventSel=2AH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR No credits available to send to QPI1 on the AD Ring; VN0 NDR Messages EventSel=2AH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP No credits available to send to QPI1 on the AD Ring; VN0 SNP Messages EventSel=2AH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM No credits available to send to QPI1 on the AD Ring; VN1 HOM Messages EventSel=2AH UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR No credits available to send to QPI1 on the AD Ring; VN1 NDR Messages EventSel=2AH UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP No credits available to send to QPI1 on the AD Ring; VN1 SNP Messages EventSel=2AH UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA No credits available to send to QPI1 on the AD Ring; VNA EventSel=2AH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM No credits available to send to QPI1 on the BL Ring; VN0 HOM Messages EventSel=2EH UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR No credits available to send to QPI1 on the BL Ring; VN0 NDR Messages EventSel=2EH UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP No credits available to send to QPI1 on the BL Ring; VN0 SNP Messages EventSel=2EH UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM No credits available to send to QPI1 on the BL Ring; VN1 HOM Messages EventSel=2EH UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR No credits available to send to QPI1 on the BL Ring; VN1 NDR Messages EventSel=2EH UMask=40H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP No credits available to send to QPI1 on the BL Ring; VN1 SNP Messages EventSel=2EH UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA No credits available to send to QPI1 on the BL Ring; VNA EventSel=2EH UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_RING_AD_USED.CCW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=07H UMask=CCH
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AD_USED.CCW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=07H UMask=04H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AD_USED.CCW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=07H UMask=08H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AD_USED.CW Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=07H UMask=33H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AD_USED.CW_VR0_EVEN Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=07H UMask=01H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AD_USED.CW_VR0_ODD Counts the number of cycles that the AD ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=07H UMask=02H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CCW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=08H UMask=CCH
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CCW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=08H UMask=04H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CCW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=08H UMask=08H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CW Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=08H UMask=33H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CW_VR0_EVEN Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=08H UMask=01H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_AK_USED.CW_VR0_ODD Counts the number of cycles that the AK ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=08H UMask=02H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CCW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=09H UMask=CCH
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CCW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Even ring polarity on Virtual Ring 0. EventSel=09H UMask=04H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CCW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Counterclockwise and Odd ring polarity on Virtual Ring 0. EventSel=09H UMask=08H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CW Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop. EventSel=09H UMask=33H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CW_VR0_EVEN Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Even ring polarity on Virtual Ring 0. EventSel=09H UMask=01H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_BL_USED.CW_VR0_ODD Counts the number of cycles that the BL ring is being used at this ring stop. This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.; Filters for the Clockwise and Odd ring polarity on Virtual Ring 0. EventSel=09H UMask=02H
    Counter=0,1,2
    Uncore
    UNC_R3_RING_IV_USED.ANY Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters any polarity EventSel=0AH UMask=FFH
    Counter=0,1,2
    Uncore
    UNC_R3_RING_IV_USED.CCW Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Counterclockwise polarity EventSel=0AH UMask=CCH
    Counter=0,1,2
    Uncore
    UNC_R3_RING_IV_USED.CW Counts the number of cycles that the IV ring is being used at this ring stop. This includes when packets are passing by and when packets are being sent, but does not include when packets are being sunk into the ring stop. The IV ring is unidirectional. Whether UP or DN is used is dependent on the system programming. Thereofore, one should generally set both the UP and DN bits for a given polarity (or both) at a given time.; Filters for Clockwise polarity EventSel=0AH UMask=33H
    Counter=0,1,2
    Uncore
    UNC_R3_RxR_AD_BYPASSED Counts the number of times when the AD Ingress was bypassed and an incoming transaction was bypassed directly across the BGF and into the qfclk domain. EventSel=12H UMask=00H
    Counter=0,1
    Uncore
    UNC_R3_RxR_BYPASSED.AD Ingress Bypassed EventSel=12H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_RxR_CYCLES_NE.HOM Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue EventSel=10H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_RxR_CYCLES_NE.NDR Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue EventSel=10H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_RxR_CYCLES_NE.SNP Counts the number of cycles when the QPI Ingress is not empty. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue EventSel=10H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.DRS Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; DRS Ingress Queue EventSel=11H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.HOM Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; HOM Ingress Queue EventSel=11H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.NCB Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCB Ingress Queue EventSel=11H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.NCS Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NCS Ingress Queue EventSel=11H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.NDR Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; NDR Ingress Queue EventSel=11H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_RxR_INSERTS.SNP Counts the number of allocations into the QPI Ingress. This tracks one of the three rings that are used by the QPI agent. This can be used in conjunction with the QPI Ingress Occupancy Accumulator event in order to calculate average queue latency. Multiple ingress buffers can be tracked at a given time using multiple counters.; SNP Ingress Queue EventSel=11H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_RxR_OCCUPANCY.DRS Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; DRS Ingress Queue EventSel=13H UMask=08H
    Counter=0
    Uncore
    UNC_R3_RxR_OCCUPANCY.HOM Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; HOM Ingress Queue EventSel=13H UMask=01H
    Counter=0
    Uncore
    UNC_R3_RxR_OCCUPANCY.NCB Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCB Ingress Queue EventSel=13H UMask=10H
    Counter=0
    Uncore
    UNC_R3_RxR_OCCUPANCY.NCS Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NCS Ingress Queue EventSel=13H UMask=20H
    Counter=0
    Uncore
    UNC_R3_RxR_OCCUPANCY.NDR Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; NDR Ingress Queue EventSel=13H UMask=04H
    Counter=0
    Uncore
    UNC_R3_RxR_OCCUPANCY.SNP Accumulates the occupancy of a given QPI Ingress queue in each cycles. This tracks one of the three ring Ingress buffers. This can be used with the QPI Ingress Not Empty event to calculate average occupancy or the QPI Ingress Allocations event in order to calculate average queuing latency.; SNP Ingress Queue EventSel=13H UMask=02H
    Counter=0
    Uncore
    UNC_R3_TxR_NACK_CCW.AD BL CounterClockwise Egress Queue EventSel=28H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_TxR_NACK_CCW.AK AD Clockwise Egress Queue EventSel=28H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_TxR_NACK_CCW.BL AD CounterClockwise Egress Queue EventSel=28H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_TxR_NACK_CW.AD AD Clockwise Egress Queue EventSel=26H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_TxR_NACK_CW.AK AD CounterClockwise Egress Queue EventSel=26H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_TxR_NACK_CW.BL BL Clockwise Egress Queue EventSel=26H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.DRS Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS. EventSel=37H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.HOM Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=37H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.NCB Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns. EventSel=37H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.NCS Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? EventSel=37H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.NDR Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP). EventSel=37H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_REJECT.SNP Number of times a request failed to acquire a DRS VN0 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN0 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class. EventSel=37H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.DRS Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS. EventSel=36H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.HOM Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=36H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.NCB Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns. EventSel=36H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.NCS Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? EventSel=36H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.NDR Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP). EventSel=36H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VN0_CREDITS_USED.SNP Number of times a VN0 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN0. VNA is a shared pool used to achieve high performance. The VN0 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail. This counts the number of times a VN0 credit was used. Note that a single VN0 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN0 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class. EventSel=36H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.DRS Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS. EventSel=39H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.HOM Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=39H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.NCB Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns. EventSel=39H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.NCS Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? EventSel=39H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.NDR Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP). EventSel=39H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_REJECT.SNP Number of times a request failed to acquire a VN1 credit. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This therefore counts the number of times when a request failed to acquire either a VNA or VN1 credit and is delayed. This should generally be a rare situation.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class. EventSel=39H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.DRS Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS. EventSel=38H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.HOM Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=38H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.NCB Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns. EventSel=38H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.NCS Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Non-Coherent Standard (NCS). NCS is commonly used for ? EventSel=38H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.NDR Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP). EventSel=38H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VN1_CREDITS_USED.SNP Number of times a VN1 credit was used on the DRS message channel. In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into. There are two credit pools, VNA and VN1. VNA is a shared pool used to achieve high performance. The VN1 pool has reserved entries for each message class and is used to prevent deadlock. Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail. This counts the number of times a VN1 credit was used. Note that a single VN1 credit holds access to potentially multiple flit buffers. For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits. A transfer on VN1 will only count a single credit even though it may use multiple buffers.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class. EventSel=38H UMask=02H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDIT_CYCLES_OUT Number of QPI uclk cycles when the transmitted has no VNA credits available and therefore cannot send any requests on this channel. Note that this does not mean that no flits can be transmitted, as those holding VN0 credits will still (potentially) be able to transmit. Generally it is the goal of the uncore that VNA credits should not run out, as this can substantially throttle back useful QPI bandwidth. EventSel=31H UMask=00H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDIT_CYCLES_USED Number of QPI uclk cycles with one or more VNA credits in use. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average number of used VNA credits. EventSel=32H UMask=00H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_ACQUIRED VNA credit Acquisitions EventSel=33H UMask=00H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_ACQUIRED.AD Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=33H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_ACQUIRED.BL Number of QPI VNA Credit acquisitions. This event can be used in conjunction with the VNA In-Use Accumulator to calculate the average lifetime of a credit holder. VNA credits are used by all message classes in order to communicate across QPI. If a packet is unable to acquire credits, it will then attempt to use credts from the VN0 pool. Note that a single packet may require multiple flit buffers (i.e. when data is being transfered). Therefore, this event will increment by the number of credits acquired in each cycle. Filtering based on message class is not provided. One can count the number of packets transfered in a given message class using an qfclk event.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=33H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.DRS Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Data Response (DRS). DRS is generally used to transmit data with coherency. For example, remote reads and writes, or cache to cache transfers will transmit their data using DRS. EventSel=34H UMask=08H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.HOM Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for the Home (HOM) message class. HOM is generally used to send requests, request responses, and snoop responses. EventSel=34H UMask=01H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.NCB Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Broadcast (NCB). NCB is generally used to transmit data without coherency. For example, non-coherent read data returns. EventSel=34H UMask=10H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.NCS Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Non-Coherent Standard (NCS). EventSel=34H UMask=20H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.NDR Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; NDR packets are used to transmit a variety of protocol flits including grants and completions (CMP). EventSel=34H UMask=04H
    Counter=0,1
    Uncore
    UNC_R3_VNA_CREDITS_REJECT.SNP Number of attempted VNA credit acquisitions that were rejected because the VNA credit pool was full (or almost full). It is possible to filter this event by message class. Some packets use more than one flit buffer, and therefore must acquire multiple credits. Therefore, one could get a reject even if the VNA credits were not fully used up. The VNA pool is generally used to provide the bulk of the QPI bandwidth (as opposed to the VN0 pool which is used to guarantee forward progress). VNA credits can run out if the flit buffer on the receiving side starts to queue up substantially. This can happen if the rest of the uncore is unable to drain the requests fast enough.; Filter for Snoop (SNP) message class. SNP is used for outgoing snoops. Note that snoop responses flow on the HOM message class. EventSel=34H UMask=02H
    Counter=0,1
    Uncore
    UNC_U_CLOCKTICKS UNC_U_CLOCKTICKS EventSel=00H UMask=00H
    Counter=0,1
    Uncore
    UNC_U_EVENT_MSG.DOORBELL_RCVD Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=42H UMask=08H
    Counter=0,1
    Uncore
    UNC_U_EVENT_MSG.INT_PRIO Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=42H UMask=10H
    Counter=0,1
    Uncore
    UNC_U_EVENT_MSG.IPI_RCVD Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=42H UMask=04H
    Counter=0,1
    Uncore
    UNC_U_EVENT_MSG.MSI_RCVD Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=42H UMask=02H
    Counter=0,1
    Uncore
    UNC_U_EVENT_MSG.VLW_RCVD Virtual Logical Wire (legacy) message were received from Uncore. Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=42H UMask=01H
    Counter=0,1
    Uncore
    UNC_U_FILTER_MATCH.DISABLE Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=41H UMask=02H
    Counter=0,1
    Uncore
    UNC_U_FILTER_MATCH.ENABLE Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=41H UMask=01H
    Counter=0,1
    Uncore
    UNC_U_FILTER_MATCH.U2C_DISABLE Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=41H UMask=08H
    Counter=0,1
    Uncore
    UNC_U_FILTER_MATCH.U2C_ENABLE Filter match per thread (w/ or w/o Filter Enable). Specify the thread to filter on using NCUPMONCTRLGLCTR.ThreadID. EventSel=41H UMask=04H
    Counter=0,1
    Uncore
    UNC_U_LOCK_CYCLES Number of times an IDI Lock/SplitLock sequence was started EventSel=44H UMask=00H
    Counter=0,1
    Uncore
    UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK PHOLD cycles. Filter from source CoreID. EventSel=45H UMask=01H
    Counter=0,1
    Uncore
    UNC_U_RACU_REQUESTS RACU Request EventSel=46H UMask=00H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.CMC Events coming from Uncore can be sent to one or all cores EventSel=43H UMask=10H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.LIVELOCK Events coming from Uncore can be sent to one or all cores; Filter by core EventSel=43H UMask=04H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.LTERROR Events coming from Uncore can be sent to one or all cores; Filter by core EventSel=43H UMask=08H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.MONITOR_T0 Events coming from Uncore can be sent to one or all cores; Filter by core EventSel=43H UMask=01H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.MONITOR_T1 Events coming from Uncore can be sent to one or all cores; Filter by core EventSel=43H UMask=02H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.OTHER Events coming from Uncore can be sent to one or all cores; PREQ, PSMI, P2U, Thermal, PCUSMI, PMI EventSel=43H UMask=80H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.TRAP Events coming from Uncore can be sent to one or all cores EventSel=43H UMask=40H
    Counter=0,1
    Uncore
    UNC_U_U2C_EVENTS.UMC Events coming from Uncore can be sent to one or all cores EventSel=43H UMask=20H
    Counter=0,1
    Uncore
    OFFCORE Offcore