| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. | IA32_FIXED_CTR0 PEBS:[PreciseEventingIP] Architectural, Fixed, AtRetirement |
| CPU_CLK_UNHALTED.THREAD | Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. | IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.REF_TSC | Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. | IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| TOPDOWN.SLOTS | Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3). | IA32_FIXED_CTR3 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| BR_INST_RETIRED.ALL_BRANCHES | Counts all branch instructions retired. | EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES | Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. | EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| CPU_CLK_UNHALTED.REF_XCLK | Counts core crystal clock cycles when the thread is unhalted. | EventSel=3CH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| CPU_CLK_UNHALTED.THREAD_P | This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. | EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| INST_RETIRED.ANY_P | Counts the number of instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. | EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| LONGEST_LAT_CACHE.MISS | Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. | EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| LONGEST_LAT_CACHE.REFERENCE | Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3. | EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| TOPDOWN.SLOTS_P | Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. | EventSel=A4H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| ARITH.DIVIDER_ACTIVE | Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations. | EventSel=14H UMask=09H CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.ANY | Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists. | EventSel=C1H UMask=07H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ASSISTS.FP | Counts all microcode Floating Point assists. | EventSel=C1H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.ANY | Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore. | EventSel=E6H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| BR_INST_RETIRED.COND | Counts conditional branch instructions retired. | EventSel=C4H UMask=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_NTAKEN | Counts not taken branch instructions retired. | EventSel=C4H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN | Counts taken conditional branch instructions retired. | EventSel=C4H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH | Counts far branch instructions retired. | EventSel=C4H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT | Counts near indirect branch instructions retired excluding returns. TSX abort is an indirect branch. | EventSel=C4H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL | Counts both direct and indirect near call instructions retired. | EventSel=C4H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN | Counts return instructions retired. | EventSel=C4H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_TAKEN | Counts taken branch instructions retired. | EventSel=C4H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND | Counts mispredicted conditional branch instructions retired. | EventSel=C5H UMask=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_NTAKEN | Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken. | EventSel=C5H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN | Counts taken conditional mispredicted branch instructions retired. | EventSel=C5H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT | Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch). | EventSel=C5H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL | Counts retired mispredicted indirect (near taken) calls, including both register and memory indirect. | EventSel=C5H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN | Counts number of near branch instructions retired that were mispredicted and taken. | EventSel=C5H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.RET | This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. | EventSel=C5H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| CORE_POWER.LVL0_TURBO_LICENSE | Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes. | EventSel=28H UMask=07H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CORE_POWER.LVL1_TURBO_LICENSE | Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions. | EventSel=28H UMask=18H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CORE_POWER.LVL2_TURBO_LICENSE | Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions. | EventSel=28H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CORE_SNOOP_RESPONSE.I_FWD_FE | Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's cache, after the data is forwarded back to the requestor and indicating the data was found unmodified in the (FE) Forward or Exclusive State in this core’s caches cache. A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.I_FWD_M | Counts responses to snoops indicating the line will now be (I)nvalidated: removed from this core's caches, after the data is forwarded back to the requestor, and indicating the data was found modified(M) in this core’s caches cache (aka HitM response). A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.I_HIT_FSE | Counts responses to snoops indicating the line will now be (I)nvalidated in this core's caches without being forwarded back to the requestor. The line was in Forward, Shared or Exclusive (FSE) state in this core’s caches. A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.MISS | Counts responses to snoops indicating that the data was not found (IHitI) in this core's caches. A single snoop response from the core counts on all hyperthreads of the Core. | EventSel=EFH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.S_FWD_FE | Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (FS) Forward or Shared state. A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.S_FWD_M | Counts responses to snoops indicating the line may be kept on this core in the (S)hared state, after the data is forwarded back to the requestor, initially the data was found in the cache in the (M)odified state. A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CORE_SNOOP_RESPONSE.S_HIT_FSE | Counts responses to snoops indicating the line was kept on this core in the (S)hared state, and that the data was found unmodified but not forwarded back to the requestor, initially the data was found in the cache in the (FSE) Forward, Shared state or Exclusive state. A single snoop response from the core counts on all hyperthreads of the core. | EventSel=EFH UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] |
| CPU_CLK_UNHALTED.DISTRIBUTED | This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. | EventSel=ECH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE | Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted. | EventSel=3CH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CPU_CLK_UNHALTED.REF_DISTRIBUTED | This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread. | EventSel=3CH UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CYCLE_ACTIVITY.CYCLES_L1D_MISS | Cycles while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=08H CMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.CYCLES_L2_MISS | Cycles while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.CYCLES_MEM_ANY | Cycles while memory subsystem has an outstanding load. | EventSel=A3H UMask=10H CMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CYCLE_ACTIVITY.STALLS_L1D_MISS | Execution stalls while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=0CH CMask=0CH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_L2_MISS | Execution stalls while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=05H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_L3_MISS | Execution stalls while L3 cache miss demand load is outstanding. | EventSel=A3H UMask=06H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| CYCLE_ACTIVITY.STALLS_MEM_ANY | Execution stalls while memory subsystem has an outstanding load. | EventSel=A3H UMask=14H CMask=14H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| CYCLE_ACTIVITY.STALLS_TOTAL | Total execution stalls. | EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DSB2MITE_SWITCHES.COUNT | Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions. | EventSel=ABH UMask=02H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DSB2MITE_SWITCHES.PENALTY_CYCLES | Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE. | EventSel=ABH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.STLB_HIT | Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB). | EventSel=08H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load. | EventSel=08H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=08H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_1G | Counts completed page walks (1G sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=08H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=08H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=08H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_LOAD_MISSES.WALK_PENDING | Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle. | EventSel=08H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.STLB_HIT | Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB). | EventSel=49H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store. | EventSel=49H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=49H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_1G | Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=49H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=49H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault. | EventSel=49H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| DTLB_STORE_MISSES.WALK_PENDING | Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle. | EventSel=49H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| EXE_ACTIVITY.1_PORTS_UTIL | Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.2_PORTS_UTIL | Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.3_PORTS_UTIL | Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.4_PORTS_UTIL | Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty. | EventSel=A6H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| EXE_ACTIVITY.BOUND_ON_STORES | Counts cycles where the Store Buffer was full and no loads caused an execution stall. | EventSel=A6H UMask=40H CMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE | Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE | Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE | Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE | Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.4_FLOPS | Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=18H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE | Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE | Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.8_FLOPS | Number of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision and double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=60H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.SCALAR | Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.SCALAR_DOUBLE | Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.SCALAR_SINGLE | Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_ARITH_INST_RETIRED.VECTOR | Number of any Vector retired FP arithmetic instructions | EventSel=C7H UMask=FCH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ANY_DSB_MISS | Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.DSB_MISS | Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=11H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS | Counts retired Instructions that experienced iTLB (Instruction TLB) true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=14H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.L1I_MISS | Counts retired Instructions who experienced Instruction L1 Cache true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=12H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.L2_MISS | Counts retired Instructions who experienced Instruction L2 Cache true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=13H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_1 | Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500106H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_128 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=508006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_16 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=501006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2 | Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500206H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1 | Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=100206H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_256 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=510006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_32 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=502006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_4 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500406H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_512 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=520006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_64 | Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=504006H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.LATENCY_GE_8 | Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=500806H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.STLB_MISS | Counts retired Instructions that experienced STLB (2nd level TLB) true miss. | EventSel=C6H UMask=01H MSR_PEBS_FRONTEND(3F7H)=15H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| ICACHE_16B.IFDATA_STALL | Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. | EventSel=80H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ICACHE_64B.IFTAG_HIT | Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses. | EventSel=83H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ICACHE_64B.IFTAG_MISS | Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses. | EventSel=83H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ICACHE_64B.IFTAG_STALL | Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. | EventSel=83H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_CYCLES_ANY | Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. | EventSel=79H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_CYCLES_OK | Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ. | EventSel=79H UMask=08H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.DSB_UOPS | Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. | EventSel=79H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_CYCLES_ANY | Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_CYCLES_OK | Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MITE_UOPS | Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MS_SWITCHES | Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. | EventSel=79H UMask=30H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ.MS_UOPS | Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS. | EventSel=79H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CORE | Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE | Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H CMask=05H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK | Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle. | EventSel=9CH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ILD_STALL.LCP | Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. | EventSel=87H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| INST_DECODED.DECODERS | Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions. | EventSel=55H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| INST_RETIRED.NOP | Number of all retired NOP instructions. | EventSel=C0H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| INST_RETIRED.PREC_DIST | A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0. | IA32_FIXED_CTR0 PEBS:[PreciseEventingIP] Fixed, AtRetirement |
| INT_MISC.ALL_RECOVERY_CYCLES | Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall. | EventSel=0DH UMask=03H CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.CLEAR_RESTEER_CYCLES | Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path. | EventSel=0DH UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.CLEARS_COUNT | Counts the number of speculative clears due to any type of branch misprediction or machine clears | EventSel=0DH UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.RECOVERY_CYCLES | Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event. | EventSel=0DH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| INT_MISC.UOP_DROPPING | Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons | EventSel=0DH UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.STLB_HIT | Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB). | EventSel=85H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_ACTIVE | Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request. | EventSel=85H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED | Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=85H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED_2M_4M | Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=85H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K | Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault. | EventSel=85H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| ITLB_MISSES.WALK_PENDING | Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle. | EventSel=85H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D.REPLACEMENT | Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. | EventSel=51H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.FB_FULL | Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.FB_FULL_PERIODS | Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=02H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.L2_STALL | Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses. | EventSel=48H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.PENDING | Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. | EventSel=48H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L1D_PEND_MISS.PENDING_CYCLES | Counts duration of L1D miss outstanding in cycles. | EventSel=48H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_IN.ALL | Counts the number of L2 cache lines filling the L2. Counting does not cover rejects. | EventSel=F1H UMask=1FH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_OUT.NON_SILENT | Counts the number of lines that are evicted by the L2 cache due to L2 cache fills. Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities. | EventSel=F2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_LINES_OUT.SILENT | Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event. | EventSel=F2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_CODE_RD | Counts the total number of L2 code requests. | EventSel=24H UMask=E4H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_DEMAND_DATA_RD | Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted. | EventSel=24H UMask=E1H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_DEMAND_MISS | Counts demand requests that miss L2 cache. | EventSel=24H UMask=27H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.ALL_RFO | Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. | EventSel=24H UMask=E2H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.CODE_RD_HIT | Counts L2 cache hits when fetching instructions, code reads. | EventSel=24H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.CODE_RD_MISS | Counts L2 cache misses when fetching instructions. | EventSel=24H UMask=24H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_HIT | Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache. | EventSel=24H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.DEMAND_DATA_RD_MISS | Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted. | EventSel=24H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.RFO_HIT | Counts the RFO (Read-for-Ownership) requests that hit L2 cache. | EventSel=24H UMask=C2H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.RFO_MISS | Counts the RFO (Read-for-Ownership) requests that miss L2 cache. | EventSel=24H UMask=22H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.SWPF_HIT | Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. | EventSel=24H UMask=C8H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_RQSTS.SWPF_MISS | Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full. | EventSel=24H UMask=28H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| L2_TRANS.L2_WB | Counts L2 writebacks that access L2 cache. | EventSel=F0H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS.NO_SR | Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. | EventSel=03H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS.STORE_FORWARD | Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide. | EventSel=03H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LD_BLOCKS_PARTIAL.ADDRESS_ALIAS | Counts the number of times a load got blocked due to false dependencies due to partial compare on address. | EventSel=07H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LOAD_HIT_PREFETCH.SWPF | Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions. | EventSel=4CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LSD.CYCLES_ACTIVE | Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector). | EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LSD.CYCLES_OK | Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector). | EventSel=A8H UMask=01H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| LSD.UOPS | Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector). | EventSel=A8H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| MACHINE_CLEARS.COUNT | Counts the number of machine clears (nukes) of any type. | EventSel=C3H UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING | Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture | EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SMC | Counts self-modifying code (SMC) detected, which causes a machine clear. | EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_INST_RETIRED.ALL_LOADS | Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. | EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.ALL_STORES | Counts all retired store instructions. | EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.ANY | Counts all retired memory instructions - loads and stores. | EventSel=D0H UMask=83H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.LOCK_LOADS | Counts retired load instructions with locked access. | EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.SPLIT_LOADS | Counts retired load instructions that split across a cacheline boundary. | EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.SPLIT_STORES | Counts retired store instructions that split across a cacheline boundary. | EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_LOADS | Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). | EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_INST_RETIRED.STLB_MISS_STORES | Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). | EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD | Counts retired load instructions whose data sources were HitM responses from shared L3. | EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS | Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. | EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD | Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. | EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE | Counts retired load instructions whose data sources were hits in L3 without snoops required. | EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM | Retired load instructions which data sources missed L3 but serviced from local DRAM. | EventSel=D3H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM | Retired load instructions which data sources missed L3 but serviced from remote dram | EventSel=D3H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD | Retired load instructions whose data sources was forwarded from a remote cache. | EventSel=D3H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM | Retired load instructions whose data sources was remote HITM. | EventSel=D3H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM | Counts retired load instructions with remote Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). | EventSel=D3H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_MISC_RETIRED.UC | Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). | EventSel=D4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.FB_HIT | Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. | EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L1_HIT | Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. | EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L1_MISS | Counts retired load instructions with at least one uop that missed in the L1 cache. | EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L2_HIT | Counts retired load instructions with L2 cache hits as data sources. | EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L2_MISS | Counts retired load instructions missed L2 cache as data sources. | EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L3_HIT | Counts retired load instructions with at least one uop that hit in the L3 cache. | EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.L3_MISS | Counts retired load instructions with at least one uop that missed in the L3 cache. | EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_LOAD_RETIRED.LOCAL_PMM | Counts retired load instructions with local Intel® Optane™ DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode). | EventSel=D1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 | Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency. | EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISC_RETIRED.LBR_INSERTS | Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR to be enabled properly. | EventSel=CCH UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISC_RETIRED.PAUSE_INST | Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products. | EventSel=CCH UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP] AtRetirement |
| OFFCORE_REQUESTS.ALL_DATA_RD | Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. | EventSel=B0H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.ALL_REQUESTS | Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses. | EventSel=B0H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.DEMAND_CODE_RD | Counts both cacheable and non-cacheable code reads to the core. | EventSel=B0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.DEMAND_DATA_RD | Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. | EventSel=B0H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.DEMAND_RFO | Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. | EventSel=B0H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD | Counts demand data read requests that miss the L3 cache. | EventSel=B0H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD | For every cycle, increments by the number of outstanding data read requests pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD | Cycles where at least 1 outstanding data read request is pending. Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3. Reads due to page walks resulting from any request type will also be counted. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD | Cycles with outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO | Cycles where at least 1 outstanding Demand RFO request is pending. RFOs are initiated by a core as part of a data store operation. Demand RFO requests include RFOs, locks, and ItoM transactions. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD | Cycles where at least one demand data read request known to have missed the L3 cache is pending. Note that this does not capture all elapsed cycles while requests are outstanding - only cycles from when the requests were known to have missed the L3 cache. | EventSel=60H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD | For every cycle, increments by the number of outstanding code read requests pending. Code Read requests include both cacheable and non-cacheable Code Reads. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD | For every cycle, increments by the number of outstanding demand data read requests pending. Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor. | EventSel=60H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6 | Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cache. Note that this event does not capture all elapsed cycles while the requests are outstanding - only cycles from when the requests were known to have missed the L3 cache. | EventSel=60H UMask=10H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| RESOURCE_STALLS.SB | Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end. | EventSel=A2H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RESOURCE_STALLS.SCOREBOARD | Counts cycles where the pipeline is stalled due to serializing operations. | EventSel=A2H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RS_EVENTS.EMPTY_CYCLES | Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into starvation periods (e.g. branch mispredictions or i-cache misses) | EventSel=5EH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RS_EVENTS.EMPTY_END | Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events) | EventSel=5EH UMask=01H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| RTM_RETIRED.ABORTED | Counts the number of times RTM abort was triggered. | EventSel=C9H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_EVENTS | Counts the number of times an RTM execution aborted due to none of the previous 3 categories (e.g. interrupt). | EventSel=C9H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_MEM | Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts). | EventSel=C9H UMask=08H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_MEMTYPE | Counts the number of times an RTM execution aborted due to incompatible memory type. | EventSel=C9H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.ABORTED_UNFRIENDLY | Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions. | EventSel=C9H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.COMMIT | Counts the number of times RTM commit succeeded. | EventSel=C9H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| RTM_RETIRED.START | Counts the number of times we entered an RTM region. Does not count nested transactions. | EventSel=C9H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| SQ_MISC.BUS_LOCK | Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically. Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory. | EventSel=F4H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SQ_MISC.SQ_FULL | Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries. | EventSel=F4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.ANY | Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed. | EventSel=32H UMask=0FH Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.NTA | Counts the number of PREFETCHNTA instructions executed. | EventSel=32H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.PREFETCHW | Counts the number of PREFETCHW instructions executed. | EventSel=32H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.T0 | Counts the number of PREFETCHT0 instructions executed. | EventSel=32H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| SW_PREFETCH_ACCESS.T1_T2 | Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed. | EventSel=32H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TLB_FLUSH.DTLB_THREAD | Counts the number of DTLB flush attempts of the thread-specific entries. | EventSel=BDH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TLB_FLUSH.STLB_ANY | Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.). | EventSel=BDH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TOPDOWN.BACKEND_BOUND_SLOTS | Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources. | EventSel=A4H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TX_EXEC.MISC2 | Counts Unfriendly TSX abort triggered by a vzeroupper instruction. | EventSel=5DH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TX_EXEC.MISC3 | Counts Unfriendly TSX abort triggered by a nest count that is too deep. | EventSel=5DH UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TX_MEM.ABORT_CAPACITY_READ | Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads | EventSel=54H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TX_MEM.ABORT_CAPACITY_WRITE | Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes. | EventSel=54H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| TX_MEM.ABORT_CONFLICT | Counts the number of times a TSX line had a cache conflict. | EventSel=54H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| UOPS_DECODED.DEC0 | Uops exclusively fetched by decoder 0 | EventSel=56H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative |
| UOPS_DISPATCHED.PORT_0 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0. | EventSel=A1H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_1 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1. | EventSel=A1H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_2_3 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3. | EventSel=A1H UMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_4_9 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9. | EventSel=A1H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_5 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5. | EventSel=A1H UMask=20H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_6 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6. | EventSel=A1H UMask=40H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_DISPATCHED.PORT_7_8 | Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8. | EventSel=A1H UMask=80H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_1 | Counts cycles when at least 1 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_2 | Counts cycles when at least 2 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_3 | Counts cycles when at least 3 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CORE_CYCLES_GE_4 | Counts cycles when at least 4 micro-ops are executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_1 | Cycles where at least 1 uop was executed per-thread. | EventSel=B1H UMask=01H CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_2 | Cycles where at least 2 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_3 | Cycles where at least 3 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=03H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.CYCLES_GE_4 | Cycles where at least 4 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=04H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.STALL_CYCLES | Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. | EventSel=B1H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.THREAD | Counts the number of uops to be executed per-thread each cycle. | EventSel=B1H UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_EXECUTED.X87 | Counts the number of x87 uops executed. | EventSel=B1H UMask=10H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_ISSUED.ANY | Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS). | EventSel=0EH UMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_ISSUED.STALL_CYCLES | Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread. | EventSel=0EH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_ISSUED.VECTOR_WIDTH_MISMATCH | Counts the number of Blend Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS) in order to preserve upper bits of vector registers. Starting with the Skylake microarchitecture, these Blend uops are needed since every Intel SSE instruction executed in Dirty Upper State needs to preserve bits 128-255 of the destination register. For more information, refer to 'Mixing Intel AVX and Intel SSE Code' section of the Optimization Guide. | EventSel=0EH UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.SLOTS | Counts the retirement slots used each cycle. | EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.STALL_CYCLES | This event counts cycles without actually retired uops. | EventSel=C2H UMask=02H Invert=1 CMask=01H Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.TOTAL_CYCLES | Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event. | EventSel=C2H UMask=02H Invert=1 CMask=0AH Counter=0,1,2,3,4,5,6,7 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT | This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD | EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement, Deprecated |
| MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM | This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD | EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3] AtRetirement, Deprecated |
| OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD | This event is deprecated. | EventSel=60H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3] Speculative, Deprecated |
| UNCORE | ||
| UNC_M_HCLOCKTICKS | Half clockticks for IMC | MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_U_CLOCKTICKS | Clockticks in the UBOX using a dedicated 48-bit Fixed Counter | MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_CHA_CLOCKTICKS | Clockticks of the uncore caching and home agent (CHA) | EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_CHA_CMS_CLOCKTICKS | CMS Clockticks | EventSel=C0H UMask=00H |
| UNC_CHA_DIR_UPDATE.HA | Counts only multi-socket cacheline directory state updates memory writes issued from the home agent (HA) pipe. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. | EventSel=54H UMask=01H |
| UNC_CHA_DIR_UPDATE.TOR | Counts only multi-socket cacheline directory state updates due to memory writes issued from the table of requests (TOR) pipe which are the result of remote transaction hitting the SF/LLC and returning data Core2Core. This does not include memory write requests which are for I (Invalid) or E (Exclusive) cachelines. | EventSel=54H UMask=02H |
| UNC_CHA_IMC_READS_COUNT.NORMAL | Counts when a normal (Non-Isochronous) read is issued to any of the memory controller channels from the CHA. | EventSel=59H UMask=01H |
| UNC_CHA_IMC_WRITES_COUNT.FULL | Counts when a normal (Non-Isochronous) full line write is issued from the CHA to any of the memory controller channels. | EventSel=5BH UMask=01H |
| UNC_CHA_LLC_LOOKUP.DATA_READ | Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2. This has numerous filters available. Note the non-standard filtering equation. This event will count requests that lookup the cache multiple times with multiple increments. One must ALWAYS set umask bit 0 and select a state or states to match. Otherwise, the event will count nothing. CHAFilter0[24:21,17] bits correspond to [FMESI] state. Read transactions | EventSel=34H UMask=FFH UMaskExt=1BC1H Counter=0,1,2,3 |
| UNC_CHA_LLC_VICTIMS.ALL | Lines Victimized : All Lines Victimized : Counts the number of lines that were victimized on a fill. This can be filtered by the state that the line was in. | EventSel=37H UMask=0FH UMaskExt=00H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL | Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. | EventSel=50H UMask=10H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_REMOTE | Counts the total number of requests coming from a remote socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. | EventSel=50H UMask=20H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS | Counts read requests made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write) . | EventSel=50H UMask=03H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL | Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). | EventSel=50H UMask=01H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_REMOTE | Counts read requests coming from a remote socket made into the CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). | EventSel=50H UMask=02H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES | Counts write requests made into the CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. | EventSel=50H UMask=0CH Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL | Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. | EventSel=50H UMask=04H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_REMOTE | Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO). Writes include all writes (streaming, evictions, HitM, etc). | EventSel=50H UMask=08H Counter=0,1,2,3 |
| UNC_CHA_SF_EVICTION.E_STATE | Counts snoop filter capacity evictions for entries tracking exclusive lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. | EventSel=3DH UMask=02H |
| UNC_CHA_SF_EVICTION.M_STATE | Counts snoop filter capacity evictions for entries tracking modified lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. | EventSel=3DH UMask=01H |
| UNC_CHA_SF_EVICTION.S_STATE | Counts snoop filter capacity evictions for entries tracking shared lines in the cores? cache.? Snoop filter capacity evictions occur when the snoop filter is full and evicts an existing entry to track a new entry.? Does not count clean evictions such as when a core?s cache replaces a tracked cacheline with a new cacheline. | EventSel=3DH UMask=04H |
| UNC_CHA_TOR_INSERTS.IA | TOR Inserts : All requests from iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH | TOR Inserts : CLFlushes issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD | TOR Inserts : CRDs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_PREF | TOR Inserts : DRd_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C897FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT | TOR Inserts : All requests from iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD | TOR Inserts : CRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF | TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD | TOR Inserts : DRds issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C817FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF | TOR Inserts : DRd_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C897FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CCC7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO | TOR Inserts : RFOs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA | TOR Inserts : LLCPrefData issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CCD7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CCC7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS | TOR Inserts : All requests from iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD | TOR Inserts : CRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF | TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD | TOR Inserts : DRds issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C817FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR | TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C81786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL | TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C816FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR | TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C81686H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM | TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8168AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM | TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8178AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF | TOR Inserts : DRd_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C897FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL | TOR Inserts; Data read prefetch from local IA that misses in the snoop filter | EventSel=35H UMask=01H UMaskExt=C896FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE | TOR Inserts; Data read prefetch from remote IA that misses in the snoop filter | EventSel=35H UMask=01H UMaskExt=C8977EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE | TOR Inserts : DRds issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8177EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR | TOR Inserts : DRds issued by iA Cores targeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C81706H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM | TOR Inserts : DRds issued by iA Cores targeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8170AH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR | TOR Inserts; Data read from local IA that misses in the snoop filter | EventSel=35H UMask=01H UMaskExt=C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA | TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CCD7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CCC7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR | TOR Inserts; Data read from local IA that misses in the snoop filter | EventSel=35H UMask=01H UMaskExt=C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO | TOR Inserts : RFOs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL | TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C806FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL | TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C886FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE | TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8877EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE | TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed remotely : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C8077EH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO | TOR Inserts : RFOs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_SPECITOM | TOR Inserts : SpecItoMs issued by iA Cores : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=01H UMaskExt=CC57FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO | TOR Inserts : All requests from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT | TOR Inserts : All requests from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C001FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM | TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL | TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CC42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE | TOR Inserts : ItoMs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CC437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CD42FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CD437FH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS | TOR Inserts : All requests from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM | TOR Inserts : ItoMs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL | TOR Inserts : PCIRdCurs issued by IO Devices and targets local memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C8F2FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE | TOR Inserts : PCIRdCurs issued by IO Devices and targets remote memory : Counts the number of entries successfully inserted into the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=35H UMask=04H UMaskExt=C8F37FH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA | TOR Occupancy : All requests from iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD | TOR Occupancy : CRDs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_DRD | TOR Occupancy : DRds issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C817FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT | TOR Occupancy : All requests from iA Cores that Hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS | TOR Occupancy : All requests from iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD | TOR Occupancy : CRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD | TOR Occupancy : DRds issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C817FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR | TOR Occupancy : DRds issued by iA Cores targeting DDR Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C81786H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL | TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed locally : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C816FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM | TOR Occupancy : DRds issued by iA Cores targeting PMM Mem that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C8178AH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE | TOR Occupancy : DRds issued by iA Cores that Missed the LLC - HOMed remotely : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C8177EH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO | TOR Occupancy : RFOs issued by iA Cores that Missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO | TOR Occupancy : RFOs issued by iA Cores : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=01H UMaskExt=C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO | TOR Occupancy : All requests from IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=04H UMaskExt=C001FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT | TOR Occupancy : All requests from IO Devices that hit the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=04H UMaskExt=C001FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS | TOR Occupancy : All requests from IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=04H UMaskExt=C001FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR | TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=04H UMaskExt=C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR | TOR Occupancy : PCIRdCurs issued by IO Devices : For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent. Does not include addressless requests such as locks and interrupts. | EventSel=36H UMask=04H UMaskExt=C8F3FFH Counter=0 |
| UNC_IIO_CLOCKTICKS | Clockticks of the integrated IO (IIO) traffic controller : Increments counter once every Traffic Controller clock, the LSCLK (500MHz) | EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS_FREERUN | Free running counter that increments for integrated IO (IIO) traffic controller clockticks | EventSel=00H UMask=00H UMaskExt=00H FCMask=00H PortMask=00H Counter=0 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS | PCIe Completion Buffer Inserts of completions with data : Part 0-7 | EventSel=C2H UMask=03H FCMask=04H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0 | PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=C2H UMask=03H FCMask=04H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1 | PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 | EventSel=C2H UMask=03H FCMask=04H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2 | PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 | EventSel=C2H UMask=03H FCMask=04H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3 | PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 | EventSel=C2H UMask=03H FCMask=04H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4 | PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 | EventSel=C2H UMask=03H FCMask=04H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5 | PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 | EventSel=C2H UMask=03H FCMask=04H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6 | PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 | EventSel=C2H UMask=03H FCMask=04H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7 | PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 | EventSel=C2H UMask=03H FCMask=04H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS | PCIe Completion Buffer Occupancy : Part 0-7 | EventSel=D5H UMask=FFH FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0 | PCIe Completion Buffer Occupancy : Part 0 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=D5H UMask=01H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1 | PCIe Completion Buffer Occupancy : Part 1 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 1 | EventSel=D5H UMask=02H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2 | PCIe Completion Buffer Occupancy : Part 2 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 2 | EventSel=D5H UMask=04H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3 | PCIe Completion Buffer Occupancy : Part 3 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 3 | EventSel=D5H UMask=08H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4 | PCIe Completion Buffer Occupancy : Part 4 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 4 | EventSel=D5H UMask=10H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5 | PCIe Completion Buffer Occupancy : Part 5 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 5 | EventSel=D5H UMask=20H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6 | PCIe Completion Buffer Occupancy : Part 6 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 6 | EventSel=D5H UMask=40H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7 | PCIe Completion Buffer Occupancy : Part 7 : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 7 | EventSel=D5H UMask=80H FCMask=04H PortMask=00H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=C0H UMask=04H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=C0H UMask=04H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=C0H UMask=04H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=C0H UMask=04H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=C0H UMask=04H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=C0H UMask=04H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=C0H UMask=04H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7 | Data requested by the CPU : Core reporting completion of Card read from Core DRAM : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=C0H UMask=04H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=C0H UMask=01H FCMask=07H PortMask=01H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=C0H UMask=01H FCMask=07H PortMask=02H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=C0H UMask=01H FCMask=07H PortMask=04H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=C0H UMask=01H FCMask=07H PortMask=08H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=C0H UMask=01H FCMask=07H PortMask=10H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=C0H UMask=01H FCMask=07H PortMask=20H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=C0H UMask=01H FCMask=07H PortMask=40H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 | Data requested by the CPU : Core writing to Card's MMIO space : Number of DWs (4 bytes) requested by the main die. Includes all requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=C0H UMask=01H FCMask=07H PortMask=80H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=80H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=80H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=83H UMask=80H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=80H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=83H UMask=80H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=83H UMask=80H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=83H UMask=80H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7 | Data requested of the CPU : CmpD - device sending completion to CPU request : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=83H UMask=80H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=04H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=04H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=83H UMask=04H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=04H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=83H UMask=04H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=83H UMask=04H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=83H UMask=04H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 | Data requested of the CPU : Card reading from DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=83H UMask=04H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=83H UMask=01H FCMask=07H PortMask=01H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=83H UMask=01H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=83H UMask=01H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=83H UMask=01H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=83H UMask=01H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=83H UMask=01H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=83H UMask=01H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 | Data requested of the CPU : Card writing to DRAM : Number of DWs (4 bytes) the card requests of the main die. Includes all requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=83H UMask=01H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL | Number requests PCIe makes of the main die : All : Counts full PCIe requests before they're broken into a series of cache-line size requests as measured by DATA_REQ_OF_CPU and TXN_REQ_OF_CPU. | EventSel=85H UMask=01H FCMask=07H PortMask=FFH Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=C1H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=C1H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=C1H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=C1H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=C1H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=C1H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=C1H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 | Number Transactions requested by the CPU : Core reading from Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=C1H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=C1H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=C1H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=C1H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=C1H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=C1H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=C1H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=C1H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 | Number Transactions requested by the CPU : Core writing to Card's MMIO space : Also known as Outbound. Number of requests initiated by the main die, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=C1H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=84H UMask=80H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=84H UMask=80H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=84H UMask=80H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=84H UMask=80H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=84H UMask=80H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=84H UMask=80H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=84H UMask=80H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7 | Number Transactions requested of the CPU : CmpD - device sending completion to CPU request : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=84H UMask=80H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=84H UMask=04H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=84H UMask=04H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=84H UMask=04H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=84H UMask=04H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=84H UMask=04H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=84H UMask=04H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=84H UMask=04H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 | Number Transactions requested of the CPU : Card reading from DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=84H UMask=04H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 0/1/2/3, Or x8 card plugged in to Lane 0/1, Or x4 card is plugged in to slot 0 | EventSel=84H UMask=01H FCMask=07H PortMask=01H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 1 | EventSel=84H UMask=01H FCMask=07H PortMask=02H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 2/3, Or x4 card is plugged in to slot 2 | EventSel=84H UMask=01H FCMask=07H PortMask=04H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 3 | EventSel=84H UMask=01H FCMask=07H PortMask=08H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x16 card plugged in to Lane 4/5/6/7, Or x8 card plugged in to Lane 4/5, Or x4 card is plugged in to slot 4 | EventSel=84H UMask=01H FCMask=07H PortMask=10H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 5 | EventSel=84H UMask=01H FCMask=07H PortMask=20H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x8 card plugged in to Lane 6/7, Or x4 card is plugged in to slot 6 | EventSel=84H UMask=01H FCMask=07H PortMask=40H Counter=0,1,2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 | Number Transactions requested of the CPU : Card writing to DRAM : Also known as Inbound. Number of 64B cache line requests initiated by the Card, including reads and writes. : x4 card is plugged in to slot 7 | EventSel=84H UMask=01H FCMask=07H PortMask=80H Counter=0,1,2,3 |
| UNC_M_ACT_COUNT.ALL | DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel. Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS. One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates. | EventSel=01H UMask=0BH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.ALL | Counts the total number of DRAM CAS commands issued on this channel. | EventSel=04H UMask=3FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.RD | Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel. This includes underfills. | EventSel=04H UMask=0FH Counter=0,1,2,3 |
| UNC_M_CAS_COUNT.WR | Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel. | EventSel=04H UMask=30H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS | DRAM Clockticks | EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.HIGH | Number of DRAM Refreshes Issued : Counts the number of refreshes issued. | EventSel=45H UMask=04H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.OPPORTUNISTIC | Number of DRAM Refreshes Issued : Counts the number of refreshes issued. | EventSel=45H UMask=01H Counter=0,1,2,3 |
| UNC_M_DRAM_REFRESH.PANIC | Number of DRAM Refreshes Issued : Counts the number of refreshes issued. | EventSel=45H UMask=02H Counter=0,1,2,3 |
| UNC_M_PMM_CMD1.ALL | PMM Commands : All : Counts all commands issued to PMM | EventSel=EAH UMask=01H |
| UNC_M_PMM_CMD1.RD | PMM Commands : Reads - RPQ : Counts read requests issued to the PMM RPQ | EventSel=EAH UMask=02H |
| UNC_M_PMM_CMD1.UFILL_RD | PMM Commands : Underfill reads : Counts underfill read commands, due to a partial write, issued to PMM | EventSel=EAH UMask=08H |
| UNC_M_PMM_CMD1.WR | PMM Commands : Writes : Counts write commands issued to PMM | EventSel=EAH UMask=04H |
| UNC_M_PMM_RPQ_INSERTS | PMM Read Queue Inserts : Counts number of read requests allocated in the PMM Read Pending Queue. This includes both ISOCH and non-ISOCH requests. | EventSel=E3H UMask=00H |
| UNC_M_PMM_RPQ_OCCUPANCY.ALL | PMM Read Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Read Pending Queue. | EventSel=E0H UMask=01H |
| UNC_M_PMM_WPQ_INSERTS | PMM Write Queue Inserts : Counts number of write requests allocated in the PMM Write Pending Queue. | EventSel=E7H UMask=00H |
| UNC_M_PMM_WPQ_OCCUPANCY.ALL | PMM Write Pending Queue Occupancy : Accumulates the per cycle occupancy of the PMM Write Pending Queue. | EventSel=E4H UMask=01H |
| UNC_M_PRE_COUNT.ALL | DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel. | EventSel=02H UMask=1CH Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT | DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table | EventSel=02H UMask=10H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.RD | DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler | EventSel=02H UMask=04H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.WR | DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler | EventSel=02H UMask=08H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH0 | Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. | EventSel=10H UMask=01H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.PCH1 | Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue. This queue is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. This includes both ISOCH and non-ISOCH requests. | EventSel=10H UMask=02H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH0 | Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. | EventSel=80H UMask=00H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_PCH1 | Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle. This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The RPQ is used to schedule reads out to the memory controller and to track the requests. Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory. | EventSel=81H UMask=00H Counter=0,1,2,3 |
| UNC_M_TAGCHK.HIT | 2LM Tag Check : Hit in Near Memory Cache | EventSel=D3H UMask=01H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_CLEAN | 2LM Tag Check : Miss, no data in this line | EventSel=D3H UMask=02H Counter=0,1,2,3 |
| UNC_M_TAGCHK.MISS_DIRTY | 2LM Tag Check : Miss, existing data may be evicted to Far Memory | EventSel=D3H UMask=04H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_RD_HIT | 2LM Tag Check : Read Hit in Near Memory Cache | EventSel=D3H UMask=08H Counter=0,1,2,3 |
| UNC_M_TAGCHK.NM_WR_HIT | 2LM Tag Check : Write Hit in Near Memory Cache | EventSel=D3H UMask=10H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH0 | Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. | EventSel=20H UMask=01H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.PCH1 | Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue. This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. | EventSel=20H UMask=02H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH0 | Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. | EventSel=82H UMask=00H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_PCH1 | Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle. This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations). The WPQ is used to schedule write out to the memory controller and to track the writes. Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after being issued to DRAM. Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have "posted" to the iMC. This is not to be confused with actually performing the write to DRAM. Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies. So, we provide filtering based on if the request has posted or not. By using the "not posted" filter, we can track how long writes spent in the iMC before completions were sent to the HA. The "posted" filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory. High average occupancies will generally coincide with high write major mode counts. | EventSel=83H UMask=00H Counter=0,1,2,3 |
| UNC_I_CACHE_TOTAL_OCCUPANCY.MEM | Total IRP occupancy of inbound read and write requests to coherent memory. This is effectively the sum of read occupancy and write occupancy. | EventSel=0FH UMask=04H Counter=0,1 |
| UNC_I_CLOCKTICKS | Clockticks of the IO coherency tracker (IRP) | EventSel=01H UMask=00H Counter=0,1 |
| UNC_I_COHERENT_OPS.PCITOM | PCIITOM request issued by the IRP unit to the mesh with the intention of writing a full cacheline to coherent memory, without a RFO. PCIITOM is a speculative Invalidate to Modified command that requests ownership of the cacheline and does not move data from the mesh to IRP cache. | EventSel=10H UMask=10H Counter=0,1 |
| UNC_I_COHERENT_OPS.WBMTOI | Coherent Ops : WbMtoI : Counts the number of coherency related operations serviced by the IRP | EventSel=10H UMask=40H Counter=0,1 |
| UNC_I_FAF_FULL | FAF RF full | EventSel=17H UMask=00H Counter=0,1 |
| UNC_I_FAF_INSERTS | Inbound read requests to coherent memory, received by the IRP and inserted into the Fire and Forget queue (FAF), a queue used for processing inbound reads in the IRP. | EventSel=18H UMask=00H Counter=0,1 |
| UNC_I_FAF_OCCUPANCY | Occupancy of the IRP Fire and Forget (FAF) queue, a queue used for processing inbound reads in the IRP. | EventSel=19H UMask=00H Counter=0,1 |
| UNC_I_FAF_TRANSACTIONS | FAF allocation -- sent to ADQ | EventSel=16H UMask=00H Counter=0,1 |
| UNC_I_IRP_ALL.INBOUND_INSERTS | : All Inserts Inbound (p2p + faf + cset) | EventSel=20H UMask=01H Counter=0,1 |
| UNC_I_MISC1.LOST_FWD | Misc Events - Set 1 : Lost Forward : Snoop pulled away ownership before a write was committed | EventSel=1FH UMask=10H Counter=0,1 |
| UNC_I_SNOOP_RESP.ALL_HIT_M | Responses to snoops of any type (code, data, invalidate) that hit M line in the IIO cache | EventSel=12H UMask=78H Counter=0,1 |
| UNC_I_TRANSACTIONS.WR_PREF | Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. | EventSel=11H UMask=08H Counter=0,1 |
| UNC_M2M_CLOCKTICKS | Clockticks of the mesh to memory (M2M) | EventSel=00H UMask=00H |
| UNC_M2M_CMS_CLOCKTICKS | CMS Clockticks | EventSel=C0H UMask=00H |
| UNC_M2M_DIRECTORY_LOOKUP.ANY | Multi-socket cacheline Directory Lookups : Found in any state | EventSel=2DH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_A | Multi-socket cacheline Directory Lookups : Found in A state | EventSel=2DH UMask=08H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_I | Multi-socket cacheline Directory Lookups : Found in I state | EventSel=2DH UMask=02H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_LOOKUP.STATE_S | Multi-socket cacheline Directory Lookups : Found in S state | EventSel=2DH UMask=04H Counter=0,1,2,3 |
| UNC_M2M_DIRECTORY_UPDATE.ANY | Multi-socket cacheline Directory Updates : From/to any state. Note: event counts are incorrect in 2LM mode. | EventSel=2EH UMask=01H Counter=0,1,2,3 |
| UNC_M2M_IMC_READS.TO_PMM | M2M Reads Issued to iMC : PMM - All Channels | EventSel=37H UMask=20H UMaskExt=07H Counter=0,1,2,3 |
| UNC_M2M_IMC_WRITES.TO_PMM | M2M Writes Issued to iMC : PMM - All Channels | EventSel=38H UMask=80H UMaskExt=1CH Counter=0,1,2,3 |
| UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN | Tag Hit : Clean NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts clean full line read hits (reads and RFOs). | EventSel=2CH UMask=01H |
| UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY | Tag Hit : Dirty NearMem Read Hit : Tag Hit indicates when a request sent to the iMC hit in Near Memory. : Counts dirty full line read hits (reads and RFOs). | EventSel=2CH UMask=02H |
| UNC_M2P_CLOCKTICKS | Clockticks of the mesh to PCI (M2P) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles. | EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_M2P_CMS_CLOCKTICKS | CMS Clockticks | EventSel=C0H UMask=00H |
| UNC_M3UPI_CLOCKTICKS | Clockticks of the mesh to UPI (M3UPI) : Counts the number of uclks in the M3 uclk domain. This could be slightly different than the count in the Ubox because of enable/freeze delays. However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles. | EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS | Clockticks of the power control unit (PCU) : The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time. | EventSel=00H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_CLOCKTICKS | Number of kfclks : Counts the number of clocks in the UPI LL. This clock runs at 1/8th the "GT/s" speed of the UPI link. For example, a 8GT/s link will have qfclk or 1GHz. Current products do not support dynamic link speeds, so this frequency is fixed. | EventSel=01H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_L1_POWER_CYCLES | Cycles in L1 : Number of UPI qfclk cycles spent in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use edge detect to count the number of instances when the UPI link entered L1. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode. | EventSel=21H UMask=00H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_DATA | Valid Flits Received : All Data : Shows legal flit time (hides impact of L0p and L0c). | EventSel=03H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.ALL_NULL | Valid Flits Received : Null FLITs received from any slot : Shows legal flit time (hides impact of L0p and L0c). | EventSel=03H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_RxL_FLITS.NON_DATA | Valid Flits Received : All Non Data : Shows legal flit time (hides impact of L0p and L0c). | EventSel=03H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_DATA | Valid Flits Sent : All Data : Shows legal flit time (hides impact of L0p and L0c). | EventSel=02H UMask=0FH Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.ALL_NULL | Valid Flits Sent : Null FLITs transmitted to any slot : Shows legal flit time (hides impact of L0p and L0c). | EventSel=02H UMask=27H Counter=0,1,2,3 |
| UNC_UPI_TxL_FLITS.NON_DATA | Valid Flits Sent : All Non Data : Shows legal flit time (hides impact of L0p and L0c). | EventSel=02H UMask=97H Counter=0,1,2,3 |
| UNC_UPI_TxL0P_POWER_CYCLES | Cycles in L0p : Number of UPI qfclk cycles spent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lanes, decreasing our bandwidth in order to save power. It increases snoop and data transfer latencies and decreases overall bandwidth. This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses. Use edge detect to count the number of instances when the UPI link entered L0p. Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. | EventSel=27H UMask=00H Counter=0,1,2,3 |
| OFFCORE | ||
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD | Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM | Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD | Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM | Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H |
| OCR.DEMAND_DATA_RD.ANY_RESPONSE | Counts demand data reads that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_RD.L3_MISS | Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00001H |
| OCR.DEMAND_DATA_RD.LOCAL_DRAM | Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000001H |
| OCR.DEMAND_RFO.LOCAL_DRAM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000002H |
| OCR.DEMAND_CODE_RD.ANY_RESPONSE | Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OCR.DEMAND_CODE_RD.L3_MISS | Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00004H |
| OCR.DEMAND_CODE_RD.LOCAL_DRAM | Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000004H |
| OCR.HWPF_L1D_AND_SWPF.L3_MISS | Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00400H |
| OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM | Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000400H |
| OCR.STREAMING_WR.ANY_RESPONSE | Counts streaming stores that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OCR.OTHER.ANY_RESPONSE | Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H |
| OCR.OTHER.L3_MISS | Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC08000H |
| OCR.HWPF_L3.ANY_RESPONSE | Counts hardware prefetches to the L3 only that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=12380H |
| OCR.DEMAND_DATA_RD.REMOTE_DRAM | Counts demand data reads that were supplied by DRAM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=730000001H |
| OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM | Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1030000001H |
| OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=830000001H |
| OCR.DEMAND_DATA_RD.DRAM | Counts demand data reads that were supplied by DRAM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000001H |
| OCR.DEMAND_DATA_RD.REMOTE_PMM | Counts demand data reads that were supplied by PMM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703000001H |
| OCR.DEMAND_DATA_RD.L3_MISS_LOCAL | Counts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400001H |
| OCR.DEMAND_DATA_RD.LOCAL_PMM | Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100400001H |
| OCR.DEMAND_DATA_RD.PMM | Counts demand data reads that were supplied by PMM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703C00001H |
| OCR.DEMAND_RFO.DRAM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000002H |
| OCR.DEMAND_RFO.REMOTE_PMM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703000002H |
| OCR.DEMAND_RFO.LOCAL_PMM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100400002H |
| OCR.DEMAND_RFO.PMM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703C00002H |
| OCR.DEMAND_CODE_RD.DRAM | Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000004H |
| OCR.DEMAND_CODE_RD.L3_MISS_LOCAL | Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400004H |
| OCR.HWPF_L1D_AND_SWPF.DRAM | Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000400H |
| OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL | Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84400400H |
| OCR.OTHER.L3_MISS_LOCAL | Counts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84408000H |
| OCR.DEMAND_DATA_RD.SNC_PMM | Counts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=700800001H |
| OCR.DEMAND_RFO.SNC_PMM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=700800002H |
| OCR.DEMAND_DATA_RD.L3_HIT | Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0001H |
| OCR.DEMAND_RFO.L3_HIT | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0002H |
| OCR.DEMAND_CODE_RD.L3_HIT | Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0004H |
| OCR.HWPF_L1D_AND_SWPF.L3_HIT | Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0400H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0477H |
| OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1030000477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=830000477H |
| OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified). | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1830000477H |
| OCR.READS_TO_CORE.DRAM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=73C000477H |
| OCR.READS_TO_CORE.LOCAL_DRAM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000477H |
| OCR.READS_TO_CORE.REMOTE_DRAM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=730000477H |
| OCR.READS_TO_CORE.REMOTE_PMM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=703000477H |
| OCR.READS_TO_CORE.LOCAL_PMM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100400477H |
| OCR.READS_TO_CORE.SNC_PMM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=700800477H |
| OCR.DEMAND_DATA_RD.SNC_DRAM | Counts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000001H |
| OCR.DEMAND_RFO.SNC_DRAM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000002H |
| OCR.DEMAND_CODE_RD.SNC_DRAM | Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000004H |
| OCR.READS_TO_CORE.SNC_DRAM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=708000477H |
| OCR.DEMAND_RFO.ANY_RESPONSE | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FFC0002H |
| OCR.READS_TO_CORE.ANY_RESPONSE | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FFC0477H |
| OCR.STREAMING_WR.L3_HIT | Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80080800H |
| OCR.HWPF_L3.L3_HIT | Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80082380H |
| OCR.READS_TO_CORE.L3_HIT | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F003C0477H |
| OCR.DEMAND_RFO.L3_MISS_LOCAL | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F04400002H |
| OCR.READS_TO_CORE.L3_MISS_LOCAL | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F04400477H |
| OCR.STREAMING_WR.L3_MISS_LOCAL | Counts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000800H |
| OCR.HWPF_L3.L3_MISS_LOCAL | Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84002380H |
| OCR.ITOM.L3_MISS_LOCAL | Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000002H |
| OCR.READS_TO_CORE.REMOTE | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F33000477H |
| OCR.HWPF_L3.REMOTE | Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=90002380H |
| OCR.ITOM.REMOTE | Counts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=90000002H |
| OCR.DEMAND_RFO.L3_MISS | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FC00002H |
| OCR.READS_TO_CORE.L3_MISS | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F3FC00477H |
| OCR.STREAMING_WR.L3_MISS | Counts streaming stores that missed the local socket's L1, L2, and L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=94000800H |
| OCR.HWPF_L3.L3_MISS | Counts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 caches. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=94002380H |
| OCR.PREFETCHES.L3_MISS_LOCAL | Counts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locally. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F844027F0H |
| OCR.PREFETCHES.L3_HIT | Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C27F0H |
| OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD | Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000001H |
| OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000002H |
| OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD | Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000004H |
| OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=808000477H |
| OCR.DEMAND_DATA_RD.SNC_CACHE.HITM | Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000001H |
| OCR.DEMAND_RFO.SNC_CACHE.HITM | Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000002H |
| OCR.DEMAND_CODE_RD.SNC_CACHE.HITM | Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000004H |
| OCR.READS_TO_CORE.SNC_CACHE.HITM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1008000477H |
| OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=70CC00477H |
| OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=70C000477H |
| OCR.READS_TO_CORE.LOCAL_SOCKET_PMM | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=700C00477H |
| OCR.HWPF_L2.ANY_RESPONSE | Counts hardware prefetch (which bring data to L2) that have any type of response. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10070H |
| OCR.READS_TO_CORE.REMOTE_MEMORY | Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socket. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=731800477H |
| OCR.WRITE_ESTIMATE.MEMORY | Counts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=FBFF80822H |