| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | Fixed Counter: Counts the number of instructions retired | IA32_FIXED_CTR0 PEBS:[PreciseEventingIP, PDISTCounter=32] Architectural, Fixed, AtRetirement |
| CPU_CLK_UNHALTED.CORE | Fixed Counter: Counts the number of unhalted core clock cycles | IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.THREAD | Fixed Counter: Counts the number of unhalted core clock cycles | IA32_FIXED_CTR1 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| CPU_CLK_UNHALTED.REF_TSC | Fixed Counter: Counts the number of unhalted reference clock cycles | IA32_FIXED_CTR2 PEBS:[NonPreciseEventingIP] Architectural, Fixed, Speculative |
| BR_INST_RETIRED.ALL_BRANCHES | Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. | EventSel=C4H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| BR_MISP_RETIRED.ALL_BRANCHES | Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. | EventSel=C5H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| CPU_CLK_UNHALTED.CORE_P | Counts the number of unhalted core clock cycles | EventSel=3CH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| CPU_CLK_UNHALTED.REF_TSC_P | Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. | EventSel=3CH UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| INST_RETIRED.ANY_P | Counts the number of instructions retired | EventSel=C0H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, AtRetirement |
| LONGEST_LAT_CACHE.MISS | Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. | EventSel=2EH UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| LONGEST_LAT_CACHE.REFERENCE | Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. | EventSel=2EH UMask=4FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Architectural, Speculative |
| ARITH.DIV_ACTIVE | Counts the number of cycles when any of the dividers are active. | EventSel=CDH UMask=03H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ARITH.FPDIV_ACTIVE | Counts the number of cycles when any of the floating point dividers are active. | EventSel=CDH UMask=02H CMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BACLEARS.ANY | Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. | EventSel=E6H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| BR_INST_RETIRED.COND | Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. | EventSel=C4H UMask=7EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.COND_TAKEN | Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. | EventSel=C4H UMask=FEH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.FAR_BRANCH | Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. | EventSel=C4H UMask=BFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT | Counts the number of near indirect JMP and near indirect CALL branch instructions retired. | EventSel=C4H UMask=EBH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.INDIRECT_CALL | Counts the number of near indirect CALL branch instructions retired. | EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_CALL | Counts the number of near CALL branch instructions retired. | EventSel=C4H UMask=F9H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.NEAR_RETURN | Counts the number of near RET branch instructions retired. | EventSel=C4H UMask=F7H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND | Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. | EventSel=C5H UMask=7EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.COND_TAKEN | Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. | EventSel=C5H UMask=FEH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT | Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired. | EventSel=C5H UMask=EBH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.INDIRECT_CALL | Counts the number of mispredicted near indirect CALL branch instructions retired. | EventSel=C5H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.NEAR_TAKEN | Counts the number of mispredicted near taken branch instructions retired. | EventSel=C5H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_MISP_RETIRED.RETURN | Counts the number of mispredicted near RET branch instructions retired. | EventSel=C5H UMask=F7H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| DTLB_LOAD_MISSES.STLB_HIT | Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB. | EventSel=08H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED | Counts the number of page walks completed due to load DTLB misses. | EventSel=08H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M | Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. | EventSel=08H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K | Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. | EventSel=08H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_LOAD_MISSES.WALK_PENDING | Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. | EventSel=08H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.STLB_HIT | Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all pages sizes. Will result in a DTLB write from STLB. | EventSel=49H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED | Counts the number of page walks completed due to store DTLB misses to a 1G page. | EventSel=49H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M | Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. | EventSel=49H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K | Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. | EventSel=49H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| DTLB_STORE_MISSES.WALK_PENDING | Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. | EventSel=49H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| FP_FLOPS_RETIRED.ALL | Counts the number of all types of floating point operations per uop with all default weighting | EventSel=C8H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.128B_DP | Counts the total number of floating point retired instructions. | EventSel=C7H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.128B_SP | Counts the number of retired instructions whose sources are a packed 128 bit single precision floating point. This may be SSE or AVX.128 operations. | EventSel=C7H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.256B_DP | Counts the number of retired instructions whose sources are a packed 256 bit double precision floating point. | EventSel=C7H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.32B_SP | Counts the number of retired instructions whose sources are a scalar 32bit single precision floating point. | EventSel=C7H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FP_INST_RETIRED.64B_DP | Counts the number of retired instructions whose sources are a scalar 64 bit double precision floating point. | EventSel=C7H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| FRONTEND_RETIRED.ITLB_MISS | Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss | EventSel=C6H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| ICACHE.ACCESSES | Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump. | EventSel=80H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ICACHE.MISSES | Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present. - | EventSel=80H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.MISS_CAUSED_WALK | Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs. | EventSel=85H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.STLB_HIT | Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB. | EventSel=85H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED | Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. | EventSel=85H UMask=0EH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED_2M_4M | Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. | EventSel=85H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_COMPLETED_4K | Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. | EventSel=85H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| ITLB_MISSES.WALK_PENDING | Counts the number of page walks outstanding for iside in PMH every cycle. A PMH page walk is outstanding from page walk start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. Walks could be counted by edge detecting on this event, but would count restarted suspended walks. | EventSel=85H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_BLOCKS.ADDRESS_ALIAS | Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check. | EventSel=03H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_BLOCKS.DATA_UNKNOWN | Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready. | EventSel=03H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_BLOCKS.STORE_FORWARD | Counts the number of retired loads that are blocked because its address partially overlapped with an older store. | EventSel=03H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| LD_HEAD.ANY_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires. | EventSel=05H UMask=FFH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.DTLB_MISS_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss. | EventSel=05H UMask=90H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_BOUND_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring. | EventSel=05H UMask=F4H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.L1_MISS_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss. | EventSel=05H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.OTHER_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc. | EventSel=05H UMask=C0H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.PGWALK_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk. | EventSel=05H UMask=A0H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| LD_HEAD.ST_ADDR_AT_RET | Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match. | EventSel=05H UMask=84H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.DISAMBIGUATION | Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU. | EventSel=C3H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.FP_ASSIST | Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops. | EventSel=C3H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.MEMORY_ORDERING | Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation. | EventSel=C3H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.PAGE_FAULT | Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs. | EventSel=C3H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SLOW | Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP. | EventSel=C3H UMask=6FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MACHINE_CLEARS.SMC | Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page. | EventSel=C3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.ALL | Counts the number of unhalted cycles when the core is stalled due to an instruction cache or TLB miss. | EventSel=35H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.L2_HIT | Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache. | EventSel=35H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.LLC_HIT | Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which hit in the LLC. | EventSel=35H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_IFETCH.LLC_MISS | Counts the number of unhalted cycles when the core is stalled due to an icache or itlb miss which missed all the caches. | EventSel=35H UMask=78H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.ALL | Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss. | EventSel=34H UMask=7FH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.L2_HIT | Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache. | EventSel=34H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_HIT | Counts the number of unhalted cycles when the core is stalled due to a demand load miss which hit in the LLC. | EventSel=34H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_BOUND_STALLS_LOAD.LLC_MISS | Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches. | EventSel=34H UMask=78H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM | Counts the number of load ops retired that miss the L3 cache and hit in DRAM | EventSel=D3H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_HIT | Counts the number of load ops retired that hit the L1 data cache. | EventSel=D1H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L1_MISS | Counts the number of load ops retired that miss in the L1 data cache. | EventSel=D1H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_HIT | Counts the number of load ops retired that hit in the L2 cache. | EventSel=D1H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L2_MISS | Counts the number of load ops retired that miss in the L2 cache. | EventSel=D1H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.L3_HIT | Counts the number of load ops retired that hit in the L3 cache. | EventSel=D1H UMask=1CH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_LOAD_UOPS_RETIRED.WCB_HIT | Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate. | EventSel=D1H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_SCHEDULER_BLOCK.ALL | Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full. | EventSel=04H UMask=07H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.LD_BUF | Counts the number of cycles that uops are blocked due to a load buffer full condition. | EventSel=04H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.RSV | Counts the number of cycles that uops are blocked due to an RSV full condition. | EventSel=04H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_SCHEDULER_BLOCK.ST_BUF | Counts the number of cycles that uops are blocked due to a store buffer full condition. | EventSel=04H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| MEM_UOPS_RETIRED.ALL_LOADS | Counts the number of load ops retired. | EventSel=D0H UMask=81H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.ALL_STORES | Counts the number of store ops retired. | EventSel=D0H UMask=82H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8 | Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled. | EventSel=D0H UMask=05H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=0,1 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1] AtRetirement |
| MEM_UOPS_RETIRED.LOCK_LOADS | Counts the number of load uops retired that performed one or more locks | EventSel=D0H UMask=21H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT | Counts the number of memory uops retired that were splits. | EventSel=D0H UMask=43H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_LOADS | Counts the number of retired split load uops. | EventSel=D0H UMask=41H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.SPLIT_STORES | Counts the number of retired split store uops. | EventSel=D0H UMask=42H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MEM_UOPS_RETIRED.STORE_LATENCY | Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES | EventSel=D0H UMask=06H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, DataLinearAddress, Latency, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISALIGN_MEM_REF.LOAD_PAGE_SPLIT | Counts misaligned loads that are 4K page splits. | EventSel=13H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISALIGN_MEM_REF.STORE_PAGE_SPLIT | Counts misaligned stores that are 4K page splits. | EventSel=13H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| MISC_RETIRED.LBR_INSERTS | Counts the number of Last Branch Record (LBR) entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. | EventSel=E4H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| SERIALIZATION.C01_MS_SCB | Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. | EventSel=75H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.ALL_P | Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. | EventSel=73H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.FASTNUKE | Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes | EventSel=73H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS | Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. | EventSel=73H UMask=03H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.MISPREDICT | Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict | EventSel=73H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BAD_SPECULATION.NUKE | Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke). | EventSel=73H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALL_P | Counts the number of retirement slots not consumed due to backend stalls | EventSel=74H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS | Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions | EventSel=74H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.MEM_SCHEDULER | Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop). This could be caused by RSV full or load/store buffer block. | EventSel=74H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER | Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop. ) | EventSel=74H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REGISTER | Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST). | EventSel=74H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.REORDER_BUFFER | Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full | EventSel=74H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_BE_BOUND.SERIALIZATION | Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb | EventSel=74H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ALL_P | Counts the number of retirement slots not consumed due to front end stalls | EventSel=71H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_DETECT | Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear | EventSel=71H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.BRANCH_RESTEER | Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear | EventSel=71H UMask=40H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.CISC | Counts the number of issue slots every cycle that were not delivered by the frontend due to ms | EventSel=71H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.DECODE | Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall | EventSel=71H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH | Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations. | EventSel=71H UMask=8DH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.FRONTEND_LATENCY | Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses. | EventSel=71H UMask=72H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ICACHE | Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss | EventSel=71H UMask=20H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.ITLB_MISS | Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss | EventSel=71H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.OTHER | Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall | EventSel=71H UMask=80H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_FE_BOUND.PREDECODE | Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong | EventSel=71H UMask=04H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| TOPDOWN_RETIRING.ALL_P | Counts the number of consumed retirement slots. | EventSel=72H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_ISSUED.ANY | Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued. | EventSel=0EH UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] Speculative |
| UOPS_RETIRED.ALL | Counts the total number of uops retired. | EventSel=C2H UMask=00H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.FPDIV | Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt). | EventSel=C2H UMask=08H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.IDIV | Counts the number of integer divide uops retired. | EventSel=C2H UMask=10H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.MS | Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. | EventSel=C2H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| UOPS_RETIRED.X87 | Counts the number of x87 uops retired, includes those in ms flows | EventSel=C2H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement |
| BR_INST_RETIRED.IND_CALL | This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL | EventSel=C4H UMask=FBH Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| FP_FLOPS_RETIRED.DP | This event is deprecated. | EventSel=C8H UMask=01H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| FP_FLOPS_RETIRED.SP | This event is deprecated. | EventSel=C8H UMask=02H Counter=0,1,2,3,4,5,6,7 PEBS:[NonPreciseEventingIP, Counter=0,1,2,3,4,5,6,7] AtRetirement, Deprecated |
| UNCORE | ||
| UNC_B2CMI_CLOCKTICKS | Clockticks of the mesh to memory (B2CMI) | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_B2CMI_DIRECT2CORE_TAKEN | Counts the number of times B2CMI egress did D2C (direct to core) | EventSel=16H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE | Counts the number of times D2C wasn't honoured even though the incoming request had d2c set for non cisgress txn | EventSel=18H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_READS.ALL | Counts any read | EventSel=24H UMask=04H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_READS.NORMAL | Counts normal reads issue to CMI | EventSel=24H UMask=01H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.ALL | All Writes - All Channels | EventSel=25H UMask=10H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.FULL | Full Non-ISOCH - All Channels | EventSel=25H UMask=01H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_IMC_WRITES.PARTIAL | Partial Non-ISOCH - All Channels | EventSel=25H UMask=02H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH | Prefetch CAM Inserts : XPT - All Channels | EventSel=56H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_TRACKER_INSERTS.CH0 | Tracker Inserts : Channel 0 | EventSel=32H UMask=04H UMaskExt=00000001H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_B2CMI_TRACKER_OCCUPANCY.CH0 | Tracker Occupancy : Channel 0 | EventSel=33H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_CLOCKTICKS | Clockticks of the uncore caching and home agent (CHA) | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_ANY | Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR or IRQ (immediate cause for triggering). | EventSel=59H UMask=03H UMaskExt=00000000H FCMask=00H PortMask=000H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ | Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in IRQ (immediate cause for triggering). | EventSel=59H UMask=01H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_DISTRESS_ASSERTED.DPT_TOR | Distress signal assertion for dynamic prefetch throttle (DPT). Threshold for distress signal assertion reached in TOR (immediate cause for triggering). | EventSel=59H UMask=02H UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_CHA_MISC.RFO_HIT_S | Cbo Misc : RFO HitS | EventSel=39H UMask=08H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_OSB.RFO_HITS_SNP_BCAST | OSB Snoop Broadcast : RFO HitS Snoop Broadcast | EventSel=55H UMask=10H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE | HA Read and Write Requests : InvalItoE | EventSel=50H UMask=30H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.INVITOE_LOCAL | Counts the total number of requests coming from a unit on this socket for exclusive ownership of a cache line without receiving data (INVITOE) to the CHA. | EventSel=50H UMask=10H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS | HA Read and Write Requests : Reads | EventSel=50H UMask=03H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.READS_LOCAL | Counts read requests coming from a unit on this socket made into this CHA. Reads include all read opcodes (including RFO: the Read for Ownership issued before a write). | EventSel=50H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES | HA Read and Write Requests : Writes | EventSel=50H UMask=0CH UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_REQUESTS.WRITES_LOCAL | Counts write requests coming from a unit on this socket made into this CHA, including streaming, evictions, HitM (Reads from another core to a Modified cacheline), etc. | EventSel=50H UMask=04H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSH | TOR Inserts : CLFlushes issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C8C7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT | TOR Inserts : CLFlushOpts issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C8D7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD | TOR Inserts : CRDs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C80FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_CRD_PREF | TOR Inserts; Code read prefetch from local IA that misses in the snoop filter | EventSel=35H UMask=01H UMaskExt=00C88FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT | TOR Inserts : DRd_Opts issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C827FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF | TOR Inserts : DRd_Opt_Prefs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C8A7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD | TOR Inserts : CRds issued by iA Cores that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00C80FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF | TOR Inserts : CRd_Prefs issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00C88FFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT | TOR Inserts : DRd_Opts issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00C827FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF | TOR Inserts : DRd_Opt_Prefs issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00C8A7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_ITOM | TOR Inserts : ItoMs issued by iA Cores that Hit LLC | EventSel=35H UMask=01H UMaskExt=00CC47FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE | TOR Inserts : LLCPrefCode issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00CCCFFDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA | TOR Inserts : LLCPrefData issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00CCD7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores that hit the LLC | EventSel=35H UMask=01H UMaskExt=00CCC7FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO | TOR Inserts : RFOs issued by iA Cores that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00C807FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00C887FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_ITOM | TOR Inserts : ItoMs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CC47FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CD47FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE | TOR Inserts : LLCPrefCode issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CCCFFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA | TOR Inserts : LLCPrefData issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CCD7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CCC7FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS | TOR Inserts : All requests from iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C001FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD | TOR Inserts : CRds issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C80FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL | TOR Inserts : CRd issued by iA Cores that Missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C80EFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF | TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C88FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL | TOR Inserts : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C88EFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT | TOR Inserts : DRd_Opt issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00C827FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL | TOR Inserts : DRd_Opt issued by iA Cores that Missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C826FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF | TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00C8A7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL | TOR Inserts : DRd_Opt_Prefs issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00C8A6FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_ITOM | TOR Inserts : ItoMs issued by iA Cores that Missed LLC | EventSel=35H UMask=01H UMaskExt=00CC47FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE | TOR Inserts : LLCPrefCode issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00CCCFFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA | TOR Inserts : LLCPrefData issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00CCD7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO | TOR Inserts : LLCPrefRFO issued by iA Cores that missed the LLC | EventSel=35H UMask=01H UMaskExt=00CCC7FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR | TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C86E86H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR | TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C86686H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO | TOR Inserts : RFOs issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C807FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL | TOR Inserts : RFOs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C806FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C887FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL | TOR Inserts : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=35H UMask=01H UMaskExt=00C886FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF | TOR Inserts : UCRdFs issued by iA Cores that Missed LLC | EventSel=35H UMask=01H UMaskExt=00C877DEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCIL | TOR Inserts : WCiLs issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C86FFEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR | TOR Inserts : WCiLs issued by iA Cores targeting DDR that missed the LLC | EventSel=35H UMask=01H UMaskExt=00C86F86H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCILF | TOR Inserts : WCiLF issued by iA Cores that Missed the LLC | EventSel=35H UMask=01H UMaskExt=00C867FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR | TOR Inserts : WCiLFs issued by iA Cores targeting DDR that missed the LLC | EventSel=35H UMask=01H UMaskExt=00C86786H Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_MISS_WIL | TOR Inserts : WiLs issued by iA Cores that Missed LLC | EventSel=35H UMask=01H UMaskExt=00C87FDEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO | TOR Inserts : RFOs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C807FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_RFO_PREF | TOR Inserts : RFO_Prefs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C887FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_SPECITOM | TOR Inserts : SpecItoMs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CC57FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBEFTOE | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00CC3FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBEFTOI | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00CC37FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBMTOE | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00CC2FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBMTOI | TOR Inserts : WbMtoIs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00CC27FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WBSTOI | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC | EventSel=35H UMask=01H UMaskExt=00CC67FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WCIL | TOR Inserts : WCiLs issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C86FFFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IA_WCILF | TOR Inserts : WCiLF issued by iA Cores | EventSel=35H UMask=01H UMaskExt=00C867FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_CLFLUSH | TOR Inserts : CLFlushes issued by IO Devices | EventSel=35H UMask=04H UMaskExt=00C8C3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOM | TOR Inserts : ItoMs issued by IO Devices that Hit the LLC | EventSel=35H UMask=04H UMaskExt=00CC43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC | EventSel=35H UMask=04H UMaskExt=00CD43FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices that hit the LLC | EventSel=35H UMask=04H UMaskExt=00C8F3FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_HIT_RFO | TOR Inserts : RFOs issued by IO Devices that hit the LLC | EventSel=35H UMask=04H UMaskExt=00C803FDH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOM | TOR Inserts : ItoMs issued by IO Devices | EventSel=35H UMask=04H UMaskExt=00CC43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices | EventSel=35H UMask=04H UMaskExt=00CD43FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOM | TOR Inserts : ItoMs issued by IO Devices that missed the LLC | EventSel=35H UMask=04H UMaskExt=00CC43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR | TOR Inserts : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC | EventSel=35H UMask=04H UMaskExt=00CD43FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices that missed the LLC | EventSel=35H UMask=04H UMaskExt=00C8F3FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_MISS_RFO | TOR Inserts : RFOs issued by IO Devices that missed the LLC | EventSel=35H UMask=04H UMaskExt=00C803FEH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_PCIRDCUR | TOR Inserts : PCIRdCurs issued by IO Devices | EventSel=35H UMask=04H UMaskExt=00C8F3FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_RFO | TOR Inserts : RFOs issued by IO Devices | EventSel=35H UMask=04H UMaskExt=00C803FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.IO_WBMTOI | TOR Inserts : WbMtoIs issued by IO Devices | EventSel=35H UMask=04H UMaskExt=00CC23FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS | TOR allocation occurred as a result of SF/LLC evictions (came from the ISMQ) | EventSel=35H UMask=02H UMaskExt=00C001FFH Counter=0,1,2,3 |
| UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH | TOR Occupancy : CLFlushes issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C8C7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT | TOR Occupancy : CLFlushOpts issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C8D7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD | TOR Occupancy : CRDs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C80FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF | TOR Occupancy; Code read prefetch from local IA that misses in the snoop filter | EventSel=36H UMask=01H UMaskExt=00C88FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD | TOR Occupancy : CRds issued by iA Cores that Hit the LLC | EventSel=36H UMask=01H UMaskExt=00C80FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF | TOR Occupancy : CRd_Prefs issued by iA Cores that hit the LLC | EventSel=36H UMask=01H UMaskExt=00C88FFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM | TOR Occupancy : ItoMs issued by iA Cores that Hit LLC | EventSel=36H UMask=01H UMaskExt=00CC47FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE | TOR Occupancy : LLCPrefCode issued by iA Cores that hit the LLC | EventSel=36H UMask=01H UMaskExt=00CCCFFDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA | TOR Occupancy : LLCPrefData issued by iA Cores that hit the LLC | EventSel=36H UMask=01H UMaskExt=00CCD7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO | TOR Occupancy : LLCPrefRFO issued by iA Cores that hit the LLC | EventSel=36H UMask=01H UMaskExt=00CCC7FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO | TOR Occupancy : RFOs issued by iA Cores that Hit the LLC | EventSel=36H UMask=01H UMaskExt=00C807FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF | TOR Occupancy : RFO_Prefs issued by iA Cores that Hit the LLC | EventSel=36H UMask=01H UMaskExt=00C887FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_ITOM | TOR Occupancy : ItoMs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CC47FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR | TOR Occupancy : ItoMCacheNears issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CD47FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE | TOR Occupancy : LLCPrefCode issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CCCFFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA | TOR Occupancy : LLCPrefData issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CCD7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO | TOR Occupancy : LLCPrefRFO issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CCC7FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD | TOR Occupancy : CRds issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C80FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL | TOR Occupancy : CRd issued by iA Cores that Missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C80EFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF | TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C88FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL | TOR Occupancy : CRd_Prefs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C88EFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM | TOR Occupancy : ItoMs issued by iA Cores that Missed LLC | EventSel=36H UMask=01H UMaskExt=00CC47FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE | TOR Occupancy : LLCPrefCode issued by iA Cores that missed the LLC | EventSel=36H UMask=01H UMaskExt=00CCCFFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA | TOR Occupancy : LLCPrefData issued by iA Cores that missed the LLC | EventSel=36H UMask=01H UMaskExt=00CCD7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO | TOR Occupancy : LLCPrefRFO issued by iA Cores that missed the LLC | EventSel=36H UMask=01H UMaskExt=00CCC7FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR | TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C86E86H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR | TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C86686H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO | TOR Occupancy : RFOs issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C807FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL | TOR Occupancy : RFOs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C806FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF | TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C887FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL | TOR Occupancy : RFO_Prefs issued by iA Cores that Missed the LLC - HOMed locally | EventSel=36H UMask=01H UMaskExt=00C886FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF | TOR Occupancy : UCRdFs issued by iA Cores that Missed LLC | EventSel=36H UMask=01H UMaskExt=00C877DEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL | TOR Occupancy : WCiLs issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C86FFEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR | TOR Occupancy : WCiLs issued by iA Cores targeting DDR that missed the LLC | EventSel=36H UMask=01H UMaskExt=00C86F86H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF | TOR Occupancy : WCiLF issued by iA Cores that Missed the LLC | EventSel=36H UMask=01H UMaskExt=00C867FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR | TOR Occupancy : WCiLFs issued by iA Cores targeting DDR that missed the LLC | EventSel=36H UMask=01H UMaskExt=00C86786H Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL | TOR Occupancy : WiLs issued by iA Cores that Missed LLC | EventSel=36H UMask=01H UMaskExt=00C87FDEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO | TOR Occupancy : RFOs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C807FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF | TOR Occupancy : RFO_Prefs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C887FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM | TOR Occupancy : SpecItoMs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CC57FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI | TOR Occupancy : WbMtoIs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00CC27FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WCIL | TOR Occupancy : WCiLs issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C86FFFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IA_WCILF | TOR Occupancy : WCiLF issued by iA Cores | EventSel=36H UMask=01H UMaskExt=00C867FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH | TOR Occupancy : CLFlushes issued by IO Devices | EventSel=36H UMask=04H UMaskExt=00C8C3FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM | TOR Occupancy : ItoMs issued by IO Devices that Hit the LLC | EventSel=36H UMask=04H UMaskExt=00CC43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR | TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that hit the LLC | EventSel=36H UMask=04H UMaskExt=00CD43FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR | TOR Occupancy : PCIRdCurs issued by IO Devices that hit the LLC | EventSel=36H UMask=04H UMaskExt=00C8F3FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO | TOR Occupancy : RFOs issued by IO Devices that hit the LLC | EventSel=36H UMask=04H UMaskExt=00C803FDH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_ITOM | TOR Occupancy : ItoMs issued by IO Devices | EventSel=36H UMask=04H UMaskExt=00CC43FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR | TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices | EventSel=36H UMask=04H UMaskExt=00CD43FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM | TOR Occupancy : ItoMs issued by IO Devices that missed the LLC | EventSel=36H UMask=04H UMaskExt=00CC43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR | TOR Occupancy : ItoMCacheNears, indicating a partial write request, from IO Devices that missed the LLC | EventSel=36H UMask=04H UMaskExt=00CD43FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR | TOR Occupancy : PCIRdCurs issued by IO Devices that missed the LLC | EventSel=36H UMask=04H UMaskExt=00C8F3FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO | TOR Occupancy : RFOs issued by IO Devices that missed the LLC | EventSel=36H UMask=04H UMaskExt=00C803FEH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR | TOR Occupancy : PCIRdCurs issued by IO Devices | EventSel=36H UMask=04H UMaskExt=00C8F3FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_RFO | TOR Occupancy : RFOs issued by IO Devices | EventSel=36H UMask=04H UMaskExt=00C803FFH Counter=0 |
| UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI | TOR Occupancy : WbMtoIs issued by IO Devices | EventSel=36H UMask=04H UMaskExt=00CC23FFH Counter=0 |
| UNC_CHACMS_CLOCKTICKS | Clockticks for CMS units attached to CHA | EventSel=01H UMask=00H UMaskExt=00000000H FCMask=00H PortMask=000H Counter=0,1,2,3 |
| UNC_IIO_CLOCKTICKS | IIO Clockticks | EventSel=01H UMask=00H UMaskExt=00000000H FCMask=00H PortMask=000H Counter=0,1,2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS | Data requested by the CPU : Core reporting completion of Card read from Core DRAM | EventSel=C0H UMask=04H UMaskExt=00070FF0H FCMask=07H PortMask=0FFH Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070FF0H FCMask=07H PortMask=0FFH Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7 | Data requested by the CPU : Core writing to Cards MMIO space | EventSel=C0H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7 | Four byte data request of the CPU : Card reading from DRAM | EventSel=83H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=02H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=04H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=08H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=10H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=20H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=40H Counter=0,1 |
| UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7 | Four byte data request of the CPU : Card writing to DRAM | EventSel=83H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=80H Counter=0,1 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7 | Number Transactions requested by the CPU : Core reading from Cards MMIO space | EventSel=C1H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=2,3 |
| UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7 | Number Transactions requested by the CPU : Core writing to Cards MMIO space | EventSel=C1H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=2,3 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7 | Number Transactions requested of the CPU : Card reading from DRAM | EventSel=84H UMask=04H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070010H FCMask=07H PortMask=001H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070020H FCMask=07H PortMask=002H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070040H FCMask=07H PortMask=004H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070080H FCMask=07H PortMask=008H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070100H FCMask=07H PortMask=010H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070200H FCMask=07H PortMask=020H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070400H FCMask=07H PortMask=040H Counter=0,1 |
| UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7 | Number Transactions requested of the CPU : Card writing to DRAM | EventSel=84H UMask=01H UMaskExt=00070800H FCMask=07H PortMask=080H Counter=0,1 |
| UNC_M_ACT_COUNT.ALL | DRAM Activate Count | EventSel=02H UMask=F7H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.ALL | CAS count for SubChannel 0, all CAS operations | EventSel=05H UMask=FFH UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD | CAS count for SubChannel 0, all reads | EventSel=05H UMask=CFH UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD_REG | CAS count for SubChannel 0 regular reads | EventSel=05H UMask=C1H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL | CAS count for SubChannel 0 underfill reads | EventSel=05H UMask=C4H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH0.WR | CAS count for SubChannel 0, all writes | EventSel=05H UMask=F0H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.ALL | CAS count for SubChannel 1, all CAS operations | EventSel=06H UMask=FFH UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD | CAS count for SubChannel 1, all reads | EventSel=06H UMask=CFH UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD_REG | CAS count for SubChannel 1 regular reads | EventSel=06H UMask=C1H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL | CAS count for SubChannel 1 underfill reads | EventSel=06H UMask=C4H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CAS_COUNT_SCH1.WR | CAS count for SubChannel 1, all writes | EventSel=06H UMask=F0H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_CLOCKTICKS | DRAM Clockticks | EventSel=01H UMask=01H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.ALL | DRAM Precharge commands. | EventSel=03H UMask=FFH UMaskExt=00000000H FCMask=00H PortMask=00H Counter=0,1,2,3 |
| UNC_M_PRE_COUNT.PGT | DRAM Precharge commands. | EventSel=03H UMask=F8H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RDB_OCCUPANCY_SCH0 | Read buffer occupancy on subchannel 0 | EventSel=1AH UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RDB_OCCUPANCY_SCH1 | Read buffer occupancy on subchannel 1 | EventSel=1BH UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH0_PCH0 | Read Pending Queue inserts for subchannel 0, pseudochannel 0 | EventSel=10H UMask=10H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH0_PCH1 | Read Pending Queue inserts for subchannel 0, pseudochannel 1 | EventSel=10H UMask=20H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH1_PCH0 | Read Pending Queue inserts for subchannel 1, pseudochannel 0 | EventSel=10H UMask=40H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_INSERTS.SCH1_PCH1 | Read Pending Queue inserts for subchannel 1, pseudochannel 1 | EventSel=10H UMask=80H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH0_PCH0 | Read pending queue occupancy for subchannel 0, pseudochannel 0 | EventSel=80H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH0_PCH1 | Read pending queue occupancy for subchannel 0, pseudochannel 1 | EventSel=81H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH1_PCH0 | Read pending queue occupancy for subchannel 1, pseudochannel 0 | EventSel=82H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_RPQ_OCCUPANCY_SCH1_PCH1 | Read pending queue occupancy for subchannel 1, pseudochannel 1 | EventSel=83H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH0_PCH0 | Write Pending Queue inserts for subchannel 0, pseudochannel 0 | EventSel=22H UMask=10H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH0_PCH1 | Write Pending Queue inserts for subchannel 0, pseudochannel 1 | EventSel=22H UMask=20H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH1_PCH0 | Write Pending Queue inserts for subchannel 1, pseudochannel 0 | EventSel=22H UMask=40H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_INSERTS.SCH1_PCH1 | Write Pending Queue inserts for subchannel 1, pseudochannel 1 | EventSel=22H UMask=80H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH0_PCH0 | Write pending queue occupancy for subchannel 0, pseudochannel 0 | EventSel=84H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH0_PCH1 | Write pending queue occupancy for subchannel 0, pseudochannel 1 | EventSel=85H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH1_PCH0 | Write pending queue occupancy for subchannel 1, pseudochannel 0 | EventSel=86H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_M_WPQ_OCCUPANCY_SCH1_PCH1 | Write pending queue occupancy for subchannel 1, pseudochannel 1 | EventSel=87H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| UNC_I_CLOCKTICKS | IRP Clockticks | EventSel=01H UMask=00H UMaskExt=00000000H FCMask=00H Counter=0,1,2,3 |
| UNC_I_FAF_INSERTS | Inbound read requests received by the IRP and inserted into the FAF queue | EventSel=18H UMask=00H UMaskExt=00000000H FCMask=00H Counter=0,1,2,3 |
| UNC_I_TRANSACTIONS.WR_PREF | Inbound write (fast path) requests to coherent memory, received by the IRP resulting in write ownership requests issued by IRP to the mesh. | EventSel=11H UMask=08H UMaskExt=00000000H FCMask=00H Counter=0,1,2,3 |
| UNC_P_CLOCKTICKS | PCU Clockticks: The PCU runs off a fixed 1 GHz clock. This event counts the number of pclk cycles measured while the counter was enabled. The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time. | EventSel=01H UMask=00H UMaskExt=00000000H Counter=0,1,2,3 |
| OFFCORE | ||
| OCR.DEMAND_DATA_RD.ANY_RESPONSE | Counts demand data reads that have any type of response. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OCR.DEMAND_DATA_RD.L3_MISS | Counts demand data reads that were not supplied by the L3 cache. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00001H |
| OCR.DEMAND_RFO.ANY_RESPONSE | Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OCR.DEMAND_RFO.L3_MISS | Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3FBFC00002H |
| OCR.STREAMING_WR.ANY_RESPONSE | Counts streaming stores that have any type of response. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD | Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H |
| OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM | Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM | Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. | EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |