| Programming Info | Definition |
|---|---|
| AnyThread | This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR. Set the AnyThread bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. |
| Architectural | This event is architecturally defined as described in Chapter 18.2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. |
| AtRetirement | Event counts only when the instruction/microoperation that caused/experienced the event retires (is committed to architectural state). |
| CMask | This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR. Set the CMask bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. |
| Cn_MSR_PMON_BOX_FILTER1 | Cn_MSR_PMON_BOX_FILTER1 refer to the filter registers as described in the Uncore Programming Guide for your platform |
| Counter | For core events this field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX) counters that can be used to count the event. For uncore events this refers to the counter MSR for the component being monitored in the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| CounterHTOff | This field lists the programmable (IA32_PMCx) counters that can be used to count the event when Intel® Hyper-Threading Technology (Intel® HT Technology) is disabled. |
| Deprecated | In future generations, this event has its name changed or is no longer supported. It remains supported in this generation. |
| EdgeDetect | This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.Set the EdgeDetect bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. |
| EventSel | For a core or offcore event this field corresponds to the Event Select in the IA32_PERFEVTSELx[7:0] MSR. Set these bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3. For an uncore event this field corresponds to the Event Select field in the Counter Control Register for the component being monitored in the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| FCMask | This field corresponds to the fc_mask. Set the fc_mask bits in the IIOn_MSR_PMON_CTLx to the value specified. These bits are defined in the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| Fixed | This event uses a Fixed-function Performance Counter Register, as defined in Chapter 18.2.2 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B or in the component of the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| Invert | This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR. Set the Invert bit to the value specified. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set this bit to 0. |
| MSR_PEBS_FRONTEND | Set the MSR_PEBS_FRONTEND bits to the value specified. These bits are defined in Chapter 18.13.1.4 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. |
| MSR_PEBS_LD_LAT_THRESHOLD | Set the MSR_PEBS_LD_LAT_THRESHOLD bits to the value specified. These bits are defined in Chapter 18.8.1.2 and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, Performance Monitoring. |
| OS | This field corresponds to the OS bit of IA32_PERFEVTSELx[17] MSR. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set the bit according to the desired scope.When set, the counter will count events when the logical processor is operating at privilege level 0. This flag can be used with the USR flag. |
| PEBS:Counters | This field is only relevant to PEBS events. It lists the counters where the event can be sampled when it is programmed as a PEBS event. |
| PEBS:DataLinearAddress | This indicates the event supports the Load/Store Data Linear Address field as described in Chapter 18 of the "SDM" under Processor Event Based Sampling (PEBS) Facility |
| PEBS:Latency | This indicates the event supports the latency value field as described in Chapter 18 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B under Processor Event Based Sampling (PEBS) Facility |
| PEBS:NonPreciseEventingIP | Can be used with the Processor Event Based Sampling Facility. A PEBS record due to a non-precise event will be generated at the next opportunity after the counter overflow has been detected. The Instruction Pointer field of the PEBS Record will contain the address of the instruction most recently retired at the time the record was generated, and may not indicate an instruction that caused/experienced the event. |
| PEBS:PDISTCounter | This field is only relevant to PEBS events. It lists the counters where the event can be sampled with precise distribution, such that the PEBS record is guaranteed to capture the EventingIP of the instruction that caused the counter to overflow, without any skid |
| PEBS:PreciseEventingIP | Can be used with the Processor Event Based Sampling Facility. A PEBS record due to a precise event will be generated after an instruction that caused/experienced the event once the counter has overflowed. The Instruction Pointer field of the PEBS Record will contain the address of an instruction that caused/experienced the event. |
| PortMask | This field corresponds to the ch_mask. Set the ch_mask bits in the IIOn_MSR_PMON_CTLx to the value specified. These bits are defined in the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| Precise | The Processor Event Based Sampling (PEBS) facility is capable of capturing the exact machine state after the instruction that experienced this event retires, including R/EIP of the next instruction. In some generations, information about the instruction that experienced the event is also available. See Section 18.4.4, “Processor Event Based Sampling (PEBS),” and the relevant PEBS sub-sections across the core PMU sections in Chapter 18, 'Performance Monitoring.' |
| Speculative | Event counts when the event occurs. For example, may count for an instruction/microoperation that was eventually cleared due to a branch mispredict, or for events unrelated to instructions/microoperations such as cycles. |
| UMask | For a core or offcore event this field corresponds to the UMASK in the IA32_PERFEVTSELx[15:8] MSR. Set these bits to the value specified. These bits are defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. For an uncore event this field corresponds to the umask field in the Counter Control Register for the component being monitored in the corresponding Uncore Performance Monitoring Reference Manual for your platform. |
| USR | This field corresponds to the USR bit of IA32_PERFEVTSELx[16] MSR. This bit is defined in Chapter 18.2.1.1 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B. Unless specified, set the bit according to the desired scope.When set, the counter will count events when the logical processor is operating at privilege levels 1, 2 or 3. This flag can be used with the OS flag. |