Intel® Microarchitecture Code Named Tremont Events
This section provides reference for hardware events that can be monitored for the CPU(s):
  • Intel® Microarchitecture Code Named Tremont
  • CORE
    Event Name Description Additional Info EventType
    INST_RETIRED.ANY Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. IA32_FIXED_CTR0
    PEBS:[PreciseEventingIP, PDISTCounter=0]
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.CORE Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. IA32_FIXED_CTR1
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed
    CoreOnly
    CPU_CLK_UNHALTED.REF_TSC Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2. IA32_FIXED_CTR2
    PEBS:[NonPreciseEventingIP]
    Architectural, Fixed
    CoreOnly
    BR_INST_RETIRED.ALL_BRANCHES Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for. EventSel=C4H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    Architectural
    CoreOnly
    BR_MISP_RETIRED.ALL_BRANCHES Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path. EventSel=C5H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.CORE_P Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter. EventSel=3CH UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.REF Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2. EventSel=3CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Architectural
    CoreOnly
    CPU_CLK_UNHALTED.REF_TSC_P Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter. EventSel=3CH UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Architectural
    CoreOnly
    INST_RETIRED.ANY_P Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter. EventSel=C0H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    Architectural
    CoreOnly
    LONGEST_LAT_CACHE.MISS Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. EventSel=2EH UMask=41H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Architectural, Speculative
    CoreOnly
    LONGEST_LAT_CACHE.REFERENCE Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis. EventSel=2EH UMask=4FH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Architectural, Speculative
    CoreOnly
    BACLEARS.ANY Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. EventSel=E6H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BACLEARS.COND Counts the number of BACLEARS due to a conditional jump. EventSel=E6H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BACLEARS.INDIRECT Counts the number of BACLEARS due to an indirect branch. EventSel=E6H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BACLEARS.RETURN Counts the number of BACLEARS due to a return branch. EventSel=E6H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BACLEARS.UNCOND Counts the number of BACLEARS due to a non-indirect, non-conditional jump. EventSel=E6H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BR_INST_RETIRED.CALL Counts the number of near CALL branch instructions retired. EventSel=C4H UMask=F9H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.FAR_BRANCH Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return. EventSel=C4H UMask=BFH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.IND_CALL Counts the number of near indirect CALL branch instructions retired. EventSel=C4H UMask=FBH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.JCC Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches. EventSel=C4H UMask=7EH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.NON_RETURN_IND Counts the number of near indirect JMP and near indirect CALL branch instructions retired. EventSel=C4H UMask=EBH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.REL_CALL Counts the number of near relative CALL branch instructions retired. EventSel=C4H UMask=FDH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.RETURN Counts the number of near RET branch instructions retired. EventSel=C4H UMask=F7H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_INST_RETIRED.TAKEN_JCC Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired. EventSel=C4H UMask=FEH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_MISP_RETIRED.IND_CALL Counts the number of mispredicted near indirect CALL branch instructions retired. EventSel=C5H UMask=FBH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_MISP_RETIRED.JCC Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired. EventSel=C5H UMask=7EH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_MISP_RETIRED.RETURN Counts the number of mispredicted near RET branch instructions retired. EventSel=C5H UMask=F7H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BR_MISP_RETIRED.TAKEN_JCC Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired. EventSel=C5H UMask=FEH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    BTCLEAR.ANY Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch. EventSel=E8H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BUS_LOCK.ALL This event is deprecated. Refer to new event BUS_LOCK.SELF_LOCKS EventSel=63H UMask=00H EdgeDetect=1
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    BUS_LOCK.BLOCK_CYCLES Counts the number of unhalted cycles a core is blocked due to an accepted lock issued by other cores. Counts on a per core basis. EventSel=63H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BUS_LOCK.CYCLES_OTHER_BLOCK This event is deprecated. Refer to new event BUS_LOCK.BLOCK_CYCLES EventSel=63H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    BUS_LOCK.CYCLES_SELF_BLOCK This event is deprecated. Refer to new event BUS_LOCK.LOCK_CYCLES EventSel=63H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    BUS_LOCK.LOCK_CYCLES Counts the number of unhalted cycles a core is blocked due to an accepted lock it issued. Counts on a per core basis. EventSel=63H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    BUS_LOCK.SELF_LOCKS Counts the number of bus locks a core issued its self (e.g. lock to UC or Split Lock) and does not include cache locks. Counts on a per core basis. EventSel=63H UMask=00H EdgeDetect=1
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    C0_STALLS.LOAD_DRAM_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_DRAM_HIT EventSel=34H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    C0_STALLS.LOAD_L2_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_L2_HIT EventSel=34H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    C0_STALLS.LOAD_LLC_HIT This event is deprecated. Refer to new event MEM_BOUND_STALLS.LOAD_LLC_HIT EventSel=34H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    CYCLES_DIV_BUSY.ANY This event is deprecated. EventSel=CDH UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative, Deprecated
    CoreOnly
    CYCLES_DIV_BUSY.FPDIV Counts the number of cycles the floating point divider is busy. Does not imply a stall waiting for the divider. EventSel=CDH UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    CYCLES_DIV_BUSY.IDIV Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider. EventSel=CDH UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DECODE_RESTRICTION.PREDECODE_WRONG Counts the number of times a decode restriction reduces the decode throughput due to wrong instruction length prediction. EventSel=E9H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DL1.DIRTY_EVICTION Counts the number of first level data cacheline (dirty) evictions caused by misses, stores, and prefetches. Does not count evictions or dirty writebacks caused by snoops. Does not count a replacement unless a (dirty) line was written back. EventSel=51H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    DTLB_LOAD_MISSES.PDE_CACHE_MISS Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache. EventSel=08H UMask=80H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_LOAD_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to loads that did not start a page walk. Account for all pages sizes. Will result in a DTLB write from STLB. EventSel=08H UMask=20H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault. EventSel=08H UMask=0EH
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=08H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_LOAD_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=08H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_LOAD_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for loads every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. EventSel=08H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_STORE_MISSES.PDE_CACHE_MISS Counts the number of page walks due to storse that miss the PDE (Page Directory Entry) cache. EventSel=49H UMask=80H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=49H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_STORE_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=49H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    DTLB_STORE_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). Includes EPT-walk intervals. EventSel=49H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    EPT.EPDE_HIT Counts the number of Extended Page Directory Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    EPT.EPDE_MISS Counts the number Extended Page Directory Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    EPT.EPDPE_HIT Counts the number Extended Page Directory Pointer Entry hits. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    EPT.EPDPE_MISS Counts the number Extended Page Directory Pointer Entry misses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches. EventSel=4FH UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    HW_INTERRUPTS.MASKED Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not. EventSel=CBH UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    HW_INTERRUPTS.PENDING_AND_MASKED Counts the number of core cycles during which there are pending interrupts while interrupts are masked (disabled). Increments by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending (which means the APIC is telling the ROB to cause an INTR). This event does not increment if EFLAGS.IF is 0 but all interrupt in the APIC’s Interrupt Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR) – because in these cases the interrupts would be held up in the APIC and would not be pended to the ROB. This event does count when an interrupt is only inhibited by MOV/POP SS state machines or the STI state machine. These extra inhibits only last for a single instructions and would not be important. EventSel=CBH UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    HW_INTERRUPTS.RECEIVED Counts the number of hardware interrupts received by the processor. EventSel=CBH UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    ICACHE.ACCESSES Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. EventSel=80H UMask=03H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ICACHE.MISSES Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line. EventSel=80H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB.FILLS Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) and a new translation was filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB. EventSel=81H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB_MISSES.PDE_CACHE_MISS Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache. EventSel=85H UMask=80H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB_MISSES.STLB_HIT Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will results in a DTLB write from STLB. EventSel=85H UMask=20H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB_MISSES.WALK_COMPLETED_2M_4M Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks that page fault. EventSel=85H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB_MISSES.WALK_COMPLETED_4K Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that page fault. EventSel=85H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    ITLB_MISSES.WALK_PENDING Counts the number of page walks outstanding in the page miss handler (PMH) for instruction fetches every cycle. A page walk is outstanding from start till PMH becomes idle again (ready to serve next walk). EventSel=85H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Speculative
    CoreOnly
    MACHINE_CLEARS.ANY Counts the total number of machine clears including memory ordering, memory disambiguation, self-modifying code, page faults and floating point assist. EventSel=C3H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MACHINE_CLEARS.MEMORY_ORDERING Counts the number of memory ordering machine clears triggered by a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations. EventSel=C3H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.IFETCH_DRAM_HIT Counts the number of cycles a core is stalled due to an instruction cache or translation lookaside buffer (TLB) access which hit in DRAM or MMIO (non-DRAM). EventSel=34H UMask=20H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.IFETCH_L2_HIT Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the L2 cache. EventSel=34H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.IFETCH_LLC_HIT Counts the number of cycles a core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) access which hit in the Last Level Cache (LLC) or other core with HITE/F/M. EventSel=34H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.LOAD_DRAM_HIT Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM). EventSel=34H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.LOAD_L2_HIT Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache. EventSel=34H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.LOAD_LLC_HIT Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M. EventSel=34H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_BOUND_STALLS.STORE_BUFFER_FULL Counts the number of cycles a core is stalled due to a store buffer being full. EventSel=34H UMask=40H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.DRAM_HIT Counts the number of load ops retired that hit in DRAM. EventSel=D1H UMask=80H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_HIT Counts the number of load uops retired that hit in the L1 data cache. EventSel=D1H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L1_MISS Counts the number of load uops retired that miss in the L1 data cache. EventSel=D1H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_HIT Counts the number of load uops retired that hit in the L2 cache. EventSel=D1H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L2_MISS Counts the number of load uops retired that miss in the L2 cache. EventSel=D1H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_LOAD_UOPS_RETIRED.L3_HIT Counts the number of load uops retired that hit in the L3 cache. EventSel=D1H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_LOADS Counts the total number of load uops retired. EventSel=D0H UMask=81H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_UOPS_RETIRED.ALL_STORES Counts the total number of store uops retired. EventSel=D0H UMask=82H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_UOPS_RETIRED.DTLB_MISS Counts the number of memory retired ops that missed in the second level TLB. EventSel=D0H UMask=13H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_UOPS_RETIRED.DTLB_MISS_LOADS Counts the number of load ops retired that miss in the second Level TLB. EventSel=D0H UMask=11H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    MEM_UOPS_RETIRED.DTLB_MISS_STORES Counts the number of store ops retired that miss in the second level TLB. EventSel=D0H UMask=12H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, DataLinearAddress, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    TOPDOWN_BAD_SPECULATION.ALL Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear. EventSel=73H UMask=06H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BAD_SPECULATION.FASTNUKE Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears. EventSel=73H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation. EventSel=73H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BAD_SPECULATION.MISPREDICT Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts. EventSel=73H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BAD_SPECULATION.MONUKE This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE EventSel=73H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    TOPDOWN_BE_BOUND.ALL Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls. EventSel=74H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions. EventSel=74H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops. EventSel=74H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops. EventSel=74H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.REGISTER Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls). EventSel=74H UMask=20H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.REORDER_BUFFER Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls). EventSel=74H UMask=40H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.SERIALIZATION Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS). EventSel=74H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_BE_BOUND.STORE_BUFFER This event is deprecated. EventSel=74H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    Deprecated
    CoreOnly
    TOPDOWN_FE_BOUND.ALL Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls. EventSel=71H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.BRANCH_DETECT Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches. EventSel=71H UMask=02H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.BRANCH_RESTEER Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch. EventSel=71H UMask=40H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.CISC Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS). EventSel=71H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.DECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls. EventSel=71H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.ICACHE Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses. EventSel=71H UMask=20H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.ITLB Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses. EventSel=71H UMask=10H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.OTHER Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized. EventSel=71H UMask=80H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_FE_BOUND.PREDECODE Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes. EventSel=71H UMask=04H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[NonPreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    TOPDOWN_RETIRING.ALL Counts the total number of consumed retirement slots. EventSel=C2H UMask=00H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    UOPS_RETIRED.FPDIV Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt). EventSel=C2H UMask=08H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3, PDISTCounter=0]
    CoreOnly
    UOPS_RETIRED.MS Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows. EventSel=C2H UMask=01H
    Counter=0,1,2,3 CounterHTOff=NA
    PEBS:[PreciseEventingIP, Counter=0,1,2,3]
    CoreOnly
    UNCORE
    OFFCORE
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H Offcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H Offcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H Offcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H Offcore
    OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H Offcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0002H Offcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0002H Offcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H Offcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0002H Offcore
    OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0004H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0004H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0004H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0010H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0010H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0010H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0010H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0010H Offcore
    OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0020H Offcore
    OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0020H Offcore
    OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0020H Offcore
    OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0020H Offcore
    OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0020H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0040H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0040H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0040H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0040H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0040H Offcore
    OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED Counts uncached memory reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001003C0000H Offcore
    OCR.UC_RD.L3_HIT.SNOOP_MISS Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002003C0000H Offcore
    OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1004003C0000H Offcore
    OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1008003C0000H Offcore
    OCR.UC_RD.L3_HIT.SNOOP_HITM Counts uncached memory reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1010003C0000H Offcore
    OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED Counts all code reads that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0044H Offcore
    OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS Counts all code reads that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0044H Offcore
    OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0044H Offcore
    OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0044H Offcore
    OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM Counts all code reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0044H Offcore
    OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify only part of a 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=400000010000H Offcore
    OCR.PARTIAL_STREAMING_WR.L3_MISS Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H Offcore
    OCR.FULL_STREAMING_WR.ANY_RESPONSE Counts streaming stores which modify a full 64 byte cacheline that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=800000010000H Offcore
    OCR.FULL_STREAMING_WR.L3_MISS Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H Offcore
    OCR.L1WB_M.ANY_RESPONSE Counts modified writebacks from L1 cache that miss the L2 cache that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1000000010000H Offcore
    OCR.L1WB_M.L3_MISS Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H Offcore
    OCR.L2WB_M.ANY_RESPONSE Counts modified writeBacks from L2 cache that miss the L3 cache that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2000000010000H Offcore
    OCR.L2WB_M.L3_MISS Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H Offcore
    OCR.ALL_CODE_RD.ANY_RESPONSE Counts all code reads that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10044H Offcore
    OCR.ALL_CODE_RD.OUTSTANDING Counts all code reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000044H Offcore
    OCR.ALL_CODE_RD.DRAM Counts all code reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H Offcore
    OCR.ALL_CODE_RD.L3_MISS Counts all code reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H Offcore
    OCR.DEMAND_DATA_RD.ANY_RESPONSE This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H Offcore
    OCR.DEMAND_DATA_RD.OUTSTANDING This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H Offcore
    OCR.DEMAND_DATA_RD.DRAM This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
    OCR.DEMAND_DATA_RD.L3_MISS This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
    OCR.DEMAND_RFO.ANY_RESPONSE Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H Offcore
    OCR.DEMAND_RFO.OUTSTANDING Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000002H Offcore
    OCR.DEMAND_RFO.DRAM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H Offcore
    OCR.DEMAND_RFO.L3_MISS Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H Offcore
    OCR.DEMAND_CODE_RD.ANY_RESPONSE Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H Offcore
    OCR.DEMAND_CODE_RD.DRAM Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H Offcore
    OCR.DEMAND_CODE_RD.L3_MISS Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H Offcore
    OCR.COREWB_M.ANY_RESPONSE Counts modified writebacks from L1 cache and L2 cache that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3000000010000H Offcore
    OCR.COREWB_M.OUTSTANDING Counts modified writebacks from L1 cache and L2 cache that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8003000000000000H Offcore
    OCR.COREWB_M.L3_MISS Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H Offcore
    OCR.HWPF_L2_DATA_RD.ANY_RESPONSE Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H Offcore
    OCR.HWPF_L2_DATA_RD.DRAM Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H Offcore
    OCR.HWPF_L2_DATA_RD.L3_MISS Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H Offcore
    OCR.HWPF_L2_RFO.ANY_RESPONSE Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H Offcore
    OCR.HWPF_L2_RFO.OUTSTANDING Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000020H Offcore
    OCR.HWPF_L2_RFO.DRAM Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H Offcore
    OCR.HWPF_L2_RFO.L3_MISS Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H Offcore
    OCR.HWPF_L2_CODE_RD.ANY_RESPONSE Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10040H Offcore
    OCR.HWPF_L2_CODE_RD.OUTSTANDING Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000040H Offcore
    OCR.HWPF_L2_CODE_RD.DRAM Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H Offcore
    OCR.HWPF_L2_CODE_RD.L3_MISS Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H Offcore
    OCR.STREAMING_WR.ANY_RESPONSE Counts streaming stores that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10800H Offcore
    OCR.STREAMING_WR.L3_MISS Counts streaming stores that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H Offcore
    OCR.OTHER.ANY_RESPONSE Counts miscellaneous requests, such as I/O accesses, that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H Offcore
    OCR.OTHER.L3_MISS Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H Offcore
    OCR.UC_RD.ANY_RESPONSE Counts uncached memory reads that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100000010000H Offcore
    OCR.UC_RD.OUTSTANDING Counts uncached memory reads that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000100000000000H Offcore
    OCR.UC_RD.DRAM Counts uncached memory reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H Offcore
    OCR.UC_RD.L3_MISS Counts uncached memory reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H Offcore
    OCR.UC_WR.ANY_RESPONSE Counts uncached memory writes that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=200000010000H Offcore
    OCR.UC_WR.L3_MISS Counts uncached memory writes that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.DRAM Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
    OCR.DEMAND_DATA_RD.LOCAL_DRAM This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
    OCR.DEMAND_RFO.LOCAL_DRAM Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000002H Offcore
    OCR.DEMAND_CODE_RD.LOCAL_DRAM Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000004H Offcore
    OCR.HWPF_L2_DATA_RD.LOCAL_DRAM Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000010H Offcore
    OCR.HWPF_L2_RFO.LOCAL_DRAM Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000020H Offcore
    OCR.HWPF_L2_CODE_RD.LOCAL_DRAM Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000040H Offcore
    OCR.UC_RD.LOCAL_DRAM Counts uncached memory reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=100184000000H Offcore
    OCR.ALL_CODE_RD.LOCAL_DRAM Counts all code reads that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000044H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000001H Offcore
    OCR.DEMAND_DATA_RD.L3_MISS_LOCAL This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
    OCR.DEMAND_RFO.L3_MISS_LOCAL Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000002H Offcore
    OCR.DEMAND_CODE_RD.L3_MISS_LOCAL Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000004H Offcore
    OCR.COREWB_M.L3_MISS_LOCAL Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3002184000000H Offcore
    OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000010H Offcore
    OCR.HWPF_L2_RFO.L3_MISS_LOCAL Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000020H Offcore
    OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000040H Offcore
    OCR.STREAMING_WR.L3_MISS_LOCAL Counts streaming stores that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000800H Offcore
    OCR.OTHER.L3_MISS_LOCAL Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184008000H Offcore
    OCR.UC_RD.L3_MISS_LOCAL Counts uncached memory reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=102184000000H Offcore
    OCR.UC_WR.L3_MISS_LOCAL Counts uncached memory writes that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=202184000000H Offcore
    OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=402184000000H Offcore
    OCR.FULL_STREAMING_WR.L3_MISS_LOCAL Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=802184000000H Offcore
    OCR.L1WB_M.L3_MISS_LOCAL Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1002184000000H Offcore
    OCR.L2WB_M.L3_MISS_LOCAL Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2002184000000H Offcore
    OCR.ALL_CODE_RD.L3_MISS_LOCAL Counts all code reads that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000044H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000001H Offcore
    OCR.PREFETCHES.ANY_RESPONSE Counts all hardware and software prefetches that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10470H Offcore
    OCR.PREFETCHES.L3_MISS Counts all hardware and software prefetches that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000470H Offcore
    OCR.READS_TO_CORE.ANY_RESPONSE Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10477H Offcore
    OCR.READS_TO_CORE.OUTSTANDING Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have an outstanding request. Returns the number of cycles until the response is received (i.e. XQ to XQ latency). EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx(1A6H)=8000000000000477H Offcore
    OCR.READS_TO_CORE.DRAM Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H Offcore
    OCR.READS_TO_CORE.L3_MISS Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H Offcore
    OCR.READS_TO_CORE.LOCAL_DRAM Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=184000477H Offcore
    OCR.READS_TO_CORE.L3_MISS_LOCAL Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2184000477H Offcore
    OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where no snoop was needed to satisfy the request. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0477H Offcore
    OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent but the snoop missed. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0477H Offcore
    OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0477H Offcore
    OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=8003C0477H Offcore
    OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0477H Offcore
    OCR.DEMAND_DATA_RD.L3_HIT This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H Offcore
    OCR.DEMAND_RFO.L3_HIT Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0002H Offcore
    OCR.DEMAND_CODE_RD.L3_HIT Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0004H Offcore
    OCR.COREWB_M.L3_HIT Counts modified writebacks from L1 cache and L2 cache that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=3001F803C0000H Offcore
    OCR.HWPF_L2_DATA_RD.L3_HIT Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0010H Offcore
    OCR.HWPF_L2_RFO.L3_HIT Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0020H Offcore
    OCR.HWPF_L2_CODE_RD.L3_HIT Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0040H Offcore
    OCR.STREAMING_WR.L3_HIT Counts streaming stores that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0800H Offcore
    OCR.UC_RD.L3_HIT Counts uncached memory reads that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=101F803C0000H Offcore
    OCR.UC_WR.L3_HIT Counts uncached memory writes that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=201F803C0000H Offcore
    OCR.PARTIAL_STREAMING_WR.L3_HIT Counts streaming stores which modify only part of a 64 byte cacheline that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=401F803C0000H Offcore
    OCR.FULL_STREAMING_WR.L3_HIT Counts streaming stores which modify a full 64 byte cacheline that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=801F803C0000H Offcore
    OCR.L1WB_M.L3_HIT Counts modified writebacks from L1 cache that miss the L2 cache that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1001F803C0000H Offcore
    OCR.L2WB_M.L3_HIT Counts modified writeBacks from L2 cache that miss the L3 cache that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=2001F803C0000H Offcore
    OCR.ALL_CODE_RD.L3_HIT Counts all code reads that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0044H Offcore
    OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0001H Offcore
    OCR.READS_TO_CORE.L3_HIT Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by the L3 cache. EventSel=(B7H) UMask={01H,02H} MSR_OFFCORE_RSPx{1A6H,1A7H}=1F803C0477H Offcore