| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | Instructions retired (fixed counter) | IA32_FIXED_CTR0 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD | Cycles when thread is not halted (fixed counter) | IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.REF | Reference cycles when thread is not halted (fixed counter) | IA32_FIXED_CTR2 Architectural, Fixed |
| BR_INST_RETIRED.ALL_BRANCHES | Retired branch instructions (Precise Event) | EventSel=C4H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] Architectural |
| BR_MISP_RETIRED.ALL_BRANCHES | Mispredicted retired branch instructions (Precise Event) | EventSel=C5H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] Architectural |
| CPU_CLK_UNHALTED.REF_P | Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) | EventSel=3CH UMask=01H Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.THREAD_P | Cycles when thread is not halted (programmable counter) | EventSel=3CH UMask=00H Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.TOTAL_CYCLES | Total CPU cycles | EventSel=3CH UMask=00H Invert=1 CMask=02H Counter=0,1,2,3 Architectural |
| INST_RETIRED.ANY_P | Instructions retired (Programmable counter and Precise Event) | EventSel=C0H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] Architectural |
| LONGEST_LAT_CACHE.MISS | Longest latency cache miss | EventSel=2EH UMask=41H Counter=0,1,2,3 Architectural |
| LONGEST_LAT_CACHE.REFERENCE | Longest latency cache reference | EventSel=2EH UMask=4FH Counter=0,1,2,3 Architectural |
| ARITH.CYCLES_DIV_BUSY | Cycles the divider is busy | EventSel=14H UMask=01H Counter=0,1,2,3 |
| ARITH.DIV | Divide Operations executed | EventSel=14H UMask=01H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| ARITH.MUL | Multiply operations executed | EventSel=14H UMask=02H Counter=0,1,2,3 |
| BACLEAR.BAD_TARGET | BACLEAR asserted with bad target address | EventSel=E6H UMask=02H Counter=0,1,2,3 |
| BACLEAR.CLEAR | BACLEAR asserted, regardless of cause | EventSel=E6H UMask=01H Counter=0,1,2,3 |
| BACLEAR_FORCE_IQ | Instruction queue forced BACLEAR | EventSel=A7H UMask=01H Counter=0,1,2,3 |
| BPU_CLEARS.EARLY | Early Branch Prediciton Unit clears | EventSel=E8H UMask=01H Counter=0,1,2,3 |
| BPU_CLEARS.LATE | Late Branch Prediction Unit clears | EventSel=E8H UMask=02H Counter=0,1,2,3 |
| BPU_MISSED_CALL_RET | Branch prediction unit missed call or return | EventSel=E5H UMask=01H Counter=0,1,2,3 |
| BR_INST_DECODED | Branch instructions decoded | EventSel=E0H UMask=01H Counter=0,1,2,3 |
| BR_INST_EXEC.ANY | Branch instructions executed | EventSel=88H UMask=7FH Counter=0,1,2,3 |
| BR_INST_EXEC.COND | Conditional branch instructions executed | EventSel=88H UMask=01H Counter=0,1,2,3 |
| BR_INST_EXEC.DIRECT | Unconditional branches executed | EventSel=88H UMask=02H Counter=0,1,2,3 |
| BR_INST_EXEC.DIRECT_NEAR_CALL | Unconditional call branches executed | EventSel=88H UMask=10H Counter=0,1,2,3 |
| BR_INST_EXEC.INDIRECT_NEAR_CALL | Indirect call branches executed | EventSel=88H UMask=20H Counter=0,1,2,3 |
| BR_INST_EXEC.INDIRECT_NON_CALL | Indirect non call branches executed | EventSel=88H UMask=04H Counter=0,1,2,3 |
| BR_INST_EXEC.NEAR_CALLS | Call branches executed | EventSel=88H UMask=30H Counter=0,1,2,3 |
| BR_INST_EXEC.NON_CALLS | All non call branches executed | EventSel=88H UMask=07H Counter=0,1,2,3 |
| BR_INST_EXEC.RETURN_NEAR | Indirect return branches executed | EventSel=88H UMask=08H Counter=0,1,2,3 |
| BR_INST_EXEC.TAKEN | Taken branches executed | EventSel=88H UMask=40H Counter=0,1,2,3 |
| BR_INST_RETIRED.ALL_BRANCHES_PS | Retired branch instructions (Precise Event) | EventSel=C4H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL | Retired conditional branch instructions (Precise Event) | EventSel=C4H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL_PS | Retired conditional branch instructions (Precise Event) | EventSel=C4H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL | Retired near call instructions (Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_PS | Retired near call instructions (Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3 | Retired near call instructions Ring 3 only(Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3_PS | Retired near call instructions Ring 3 only(Precise Event) | EventSel=C4H UMask=02H CMask=0 Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_EXEC.ANY | Mispredicted branches executed | EventSel=89H UMask=7FH Counter=0,1,2,3 |
| BR_MISP_EXEC.COND | Mispredicted conditional branches executed | EventSel=89H UMask=01H Counter=0,1,2,3 |
| BR_MISP_EXEC.DIRECT | Mispredicted unconditional branches executed | EventSel=89H UMask=02H Counter=0,1,2,3 |
| BR_MISP_EXEC.DIRECT_NEAR_CALL | Mispredicted non call branches executed | EventSel=89H UMask=10H Counter=0,1,2,3 |
| BR_MISP_EXEC.INDIRECT_NEAR_CALL | Mispredicted indirect call branches executed | EventSel=89H UMask=20H Counter=0,1,2,3 |
| BR_MISP_EXEC.INDIRECT_NON_CALL | Mispredicted indirect non call branches executed | EventSel=89H UMask=04H Counter=0,1,2,3 |
| BR_MISP_EXEC.NEAR_CALLS | Mispredicted call branches executed | EventSel=89H UMask=30H Counter=0,1,2,3 |
| BR_MISP_EXEC.NON_CALLS | Mispredicted non call branches executed | EventSel=89H UMask=07H Counter=0,1,2,3 |
| BR_MISP_EXEC.RETURN_NEAR | Mispredicted return branches executed | EventSel=89H UMask=08H Counter=0,1,2,3 |
| BR_MISP_EXEC.TAKEN | Mispredicted taken branches executed | EventSel=89H UMask=40H Counter=0,1,2,3 |
| BR_MISP_RETIRED.ALL_BRANCHES_PS | Mispredicted retired branch instructions (Precise Event) | EventSel=C5H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL | Mispredicted conditional retired branches (Precise Event) | EventSel=C5H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL_PS | Mispredicted conditional retired branches (Precise Event) | EventSel=C5H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_CALL | Mispredicted near retired calls (Precise Event) | EventSel=C5H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_CALL_PS | Mispredicted near retired calls (Precise Event) | EventSel=C5H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| CACHE_LOCK_CYCLES.L1D | Cycles L1D locked | EventSel=63H UMask=02H Counter=0,1 |
| CACHE_LOCK_CYCLES.L1D_L2 | Cycles L1D and L2 locked | EventSel=63H UMask=01H Counter=0,1 |
| DTLB_LOAD_MISSES.ANY | DTLB load misses | EventSel=08H UMask=01H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED | DTLB load miss large page walks | EventSel=08H UMask=80H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.PDE_MISS | DTLB load miss caused by low part of address | EventSel=08H UMask=20H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.STLB_HIT | DTLB second level hit | EventSel=08H UMask=10H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.WALK_COMPLETED | DTLB load miss page walks complete | EventSel=08H UMask=02H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.WALK_CYCLES | DTLB load miss page walk cycles | EventSel=08H UMask=04H Counter=0,1,2,3 |
| DTLB_MISSES.ANY | DTLB misses | EventSel=49H UMask=01H Counter=0,1,2,3 |
| DTLB_MISSES.LARGE_WALK_COMPLETED | DTLB miss large page walks | EventSel=49H UMask=80H Counter=0,1,2,3 |
| DTLB_MISSES.PDE_MISS | DTLB misses casued by low part of address | EventSel=49H UMask=20H Counter=0,1,2,3 |
| DTLB_MISSES.STLB_HIT | DTLB first level misses but second level hit | EventSel=49H UMask=10H Counter=0,1,2,3 |
| DTLB_MISSES.WALK_COMPLETED | DTLB miss page walks | EventSel=49H UMask=02H Counter=0,1,2,3 |
| DTLB_MISSES.WALK_CYCLES | DTLB miss page walk cycles | EventSel=49H UMask=04H Counter=0,1,2,3 |
| EPT.WALK_CYCLES | Extended Page Table walk cycles | EventSel=4FH UMask=10H Counter=0,1,2,3 |
| ES_REG_RENAMES | ES segment renames | EventSel=D5H UMask=01H Counter=0,1,2,3 |
| FP_ASSIST.ALL | X87 Floating point assists (Precise Event) | EventSel=F7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.ALL_PS | X87 Floating point assists (Precise Event) | EventSel=F7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.INPUT | X87 Floating poiint assists for invalid input value (Precise Event) | EventSel=F7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.INPUT_PS | X87 Floating poiint assists for invalid input value (Precise Event) | EventSel=F7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.OUTPUT | X87 Floating point assists for invalid output value (Precise Event) | EventSel=F7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.OUTPUT_PS | X87 Floating point assists for invalid output value (Precise Event) | EventSel=F7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_COMP_OPS_EXE.MMX | MMX Uops | EventSel=10H UMask=02H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION | SSE* FP double precision Uops | EventSel=10H UMask=80H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP | SSE and SSE2 FP Uops | EventSel=10H UMask=04H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP_PACKED | SSE FP packed Uops | EventSel=10H UMask=10H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP_SCALAR | SSE FP scalar Uops | EventSel=10H UMask=20H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION | SSE* FP single precision Uops | EventSel=10H UMask=40H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE2_INTEGER | SSE2 integer Uops | EventSel=10H UMask=08H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.X87 | Computational floating-point operations executed | EventSel=10H UMask=01H Counter=0,1,2,3 |
| FP_MMX_TRANS.ANY | All Floating Point to and from MMX transitions | EventSel=CCH UMask=03H Counter=0,1,2,3 |
| FP_MMX_TRANS.TO_FP | Transitions from MMX to Floating Point instructions | EventSel=CCH UMask=01H Counter=0,1,2,3 |
| FP_MMX_TRANS.TO_MMX | Transitions from Floating Point to MMX instructions | EventSel=CCH UMask=02H Counter=0,1,2,3 |
| ILD_STALL.ANY | Any Instruction Length Decoder stall cycles | EventSel=87H UMask=0FH Counter=0,1,2,3 |
| ILD_STALL.IQ_FULL | Instruction Queue full stall cycles | EventSel=87H UMask=04H Counter=0,1,2,3 |
| ILD_STALL.LCP | Length Change Prefix stall cycles | EventSel=87H UMask=01H Counter=0,1,2,3 |
| ILD_STALL.MRU | Stall cycles due to BPU MRU bypass | EventSel=87H UMask=02H Counter=0,1,2,3 |
| ILD_STALL.REGEN | Regen stall cycles | EventSel=87H UMask=08H Counter=0,1,2,3 |
| INST_DECODED.DEC0 | Instructions that must be decoded by decoder 0 | EventSel=18H UMask=01H Counter=0,1,2,3 |
| INST_QUEUE_WRITE_CYCLES | Cycles instructions are written to the instruction queue | EventSel=1EH UMask=01H Counter=0,1,2,3 |
| INST_QUEUE_WRITES | Instructions written to instruction queue. | EventSel=17H UMask=01H Counter=0,1,2,3 |
| INST_RETIRED.ANY_P_PS | Instructions retired (Programmable counter and Precise Event) | EventSel=C0H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.MMX | Retired MMX instructions (Precise Event) | EventSel=C0H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.MMX_PS | Retired MMX instructions (Precise Event) | EventSel=C0H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.TOTAL_CYCLES | Total cycles (Precise Event) | EventSel=C0H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.TOTAL_CYCLES_PS | Total cycles (Precise Event) | EventSel=C0H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.X87 | Retired floating-point operations (Precise Event) | EventSel=C0H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.X87_PS | Retired floating-point operations (Precise Event) | EventSel=C0H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| IO_TRANSACTIONS | I/O transactions | EventSel=6CH UMask=01H Counter=0,1,2,3 |
| ITLB_FLUSH | ITLB flushes | EventSel=AEH UMask=01H Counter=0,1,2,3 |
| ITLB_MISS_RETIRED | Retired instructions that missed the ITLB (Precise Event) | EventSel=C8H UMask=20H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| ITLB_MISS_RETIRED_PS | Retired instructions that missed the ITLB (Precise Event) | EventSel=C8H UMask=20H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| ITLB_MISSES.ANY | ITLB miss | EventSel=85H UMask=01H Counter=0,1,2,3 |
| ITLB_MISSES.LARGE_WALK_COMPLETED | ITLB miss large page walks | EventSel=85H UMask=80H Counter=0,1,2,3 |
| ITLB_MISSES.WALK_COMPLETED | ITLB miss page walks | EventSel=85H UMask=02H Counter=0,1,2,3 |
| ITLB_MISSES.WALK_CYCLES | ITLB miss page walk cycles | EventSel=85H UMask=04H Counter=0,1,2,3 |
| L1D.M_EVICT | L1D cache lines replaced in M state | EventSel=51H UMask=04H Counter=0,1 |
| L1D.M_REPL | L1D cache lines allocated in the M state | EventSel=51H UMask=02H Counter=0,1 |
| L1D.M_SNOOP_EVICT | L1D snoop eviction of cache lines in M state | EventSel=51H UMask=08H Counter=0,1 |
| L1D.REPL | L1 data cache lines allocated | EventSel=51H UMask=01H Counter=0,1 |
| L1D_CACHE_PREFETCH_LOCK_FB_HIT | L1D prefetch load lock accepted in fill buffer | EventSel=52H UMask=01H Counter=0,1 |
| L1D_PREFETCH.MISS | L1D hardware prefetch misses | EventSel=4EH UMask=02H Counter=0,1 |
| L1D_PREFETCH.REQUESTS | L1D hardware prefetch requests | EventSel=4EH UMask=01H Counter=0,1 |
| L1D_PREFETCH.TRIGGERS | L1D hardware prefetch requests triggered | EventSel=4EH UMask=04H Counter=0,1 |
| L1D_WB_L2.E_STATE | L1 writebacks to L2 in E state | EventSel=28H UMask=04H Counter=0,1,2,3 |
| L1D_WB_L2.I_STATE | L1 writebacks to L2 in I state (misses) | EventSel=28H UMask=01H Counter=0,1,2,3 |
| L1D_WB_L2.M_STATE | L1 writebacks to L2 in M state | EventSel=28H UMask=08H Counter=0,1,2,3 |
| L1D_WB_L2.MESI | All L1 writebacks to L2 | EventSel=28H UMask=0FH Counter=0,1,2,3 |
| L1D_WB_L2.S_STATE | L1 writebacks to L2 in S state | EventSel=28H UMask=02H Counter=0,1,2,3 |
| L1I.CYCLES_STALLED | L1I instruction fetch stall cycles | EventSel=80H UMask=04H Counter=0,1,2,3 |
| L1I.HITS | L1I instruction fetch hits | EventSel=80H UMask=01H Counter=0,1,2,3 |
| L1I.MISSES | L1I instruction fetch misses | EventSel=80H UMask=02H Counter=0,1,2,3 |
| L1I.READS | L1I Instruction fetches | EventSel=80H UMask=03H Counter=0,1,2,3 |
| L2_DATA_RQSTS.ANY | All L2 data requests | EventSel=26H UMask=FFH Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.E_STATE | L2 data demand loads in E state | EventSel=26H UMask=04H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.I_STATE | L2 data demand loads in I state (misses) | EventSel=26H UMask=01H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.M_STATE | L2 data demand loads in M state | EventSel=26H UMask=08H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.MESI | L2 data demand requests | EventSel=26H UMask=0FH Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.S_STATE | L2 data demand loads in S state | EventSel=26H UMask=02H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.E_STATE | L2 data prefetches in E state | EventSel=26H UMask=40H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.I_STATE | L2 data prefetches in the I state (misses) | EventSel=26H UMask=10H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.M_STATE | L2 data prefetches in M state | EventSel=26H UMask=80H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.MESI | All L2 data prefetches | EventSel=26H UMask=F0H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.S_STATE | L2 data prefetches in the S state | EventSel=26H UMask=20H Counter=0,1,2,3 |
| L2_LINES_IN.ANY | L2 lines allocated | EventSel=F1H UMask=07H Counter=0,1,2,3 |
| L2_LINES_IN.E_STATE | L2 lines allocated in the E state | EventSel=F1H UMask=04H Counter=0,1,2,3 |
| L2_LINES_IN.S_STATE | L2 lines allocated in the S state | EventSel=F1H UMask=02H Counter=0,1,2,3 |
| L2_LINES_OUT.ANY | L2 lines evicted | EventSel=F2H UMask=0FH Counter=0,1,2,3 |
| L2_LINES_OUT.DEMAND_CLEAN | L2 lines evicted by a demand request | EventSel=F2H UMask=01H Counter=0,1,2,3 |
| L2_LINES_OUT.DEMAND_DIRTY | L2 modified lines evicted by a demand request | EventSel=F2H UMask=02H Counter=0,1,2,3 |
| L2_LINES_OUT.PREFETCH_CLEAN | L2 lines evicted by a prefetch request | EventSel=F2H UMask=04H Counter=0,1,2,3 |
| L2_LINES_OUT.PREFETCH_DIRTY | L2 modified lines evicted by a prefetch request | EventSel=F2H UMask=08H Counter=0,1,2,3 |
| L2_RQSTS.IFETCH_HIT | L2 instruction fetch hits | EventSel=24H UMask=10H Counter=0,1,2,3 |
| L2_RQSTS.IFETCH_MISS | L2 instruction fetch misses | EventSel=24H UMask=20H Counter=0,1,2,3 |
| L2_RQSTS.IFETCHES | L2 instruction fetches | EventSel=24H UMask=30H Counter=0,1,2,3 |
| L2_RQSTS.LD_HIT | L2 load hits | EventSel=24H UMask=01H Counter=0,1,2,3 |
| L2_RQSTS.LD_MISS | L2 load misses | EventSel=24H UMask=02H Counter=0,1,2,3 |
| L2_RQSTS.LOADS | L2 requests | EventSel=24H UMask=03H Counter=0,1,2,3 |
| L2_RQSTS.MISS | All L2 misses | EventSel=24H UMask=AAH Counter=0,1,2,3 |
| L2_RQSTS.PREFETCH_HIT | L2 prefetch hits | EventSel=24H UMask=40H Counter=0,1,2,3 |
| L2_RQSTS.PREFETCH_MISS | L2 prefetch misses | EventSel=24H UMask=80H Counter=0,1,2,3 |
| L2_RQSTS.PREFETCHES | All L2 prefetches | EventSel=24H UMask=C0H Counter=0,1,2,3 |
| L2_RQSTS.REFERENCES | All L2 requests | EventSel=24H UMask=FFH Counter=0,1,2,3 |
| L2_RQSTS.RFO_HIT | L2 RFO hits | EventSel=24H UMask=04H Counter=0,1,2,3 |
| L2_RQSTS.RFO_MISS | L2 RFO misses | EventSel=24H UMask=08H Counter=0,1,2,3 |
| L2_RQSTS.RFOS | L2 RFO requests | EventSel=24H UMask=0CH Counter=0,1,2,3 |
| L2_TRANSACTIONS.ANY | All L2 transactions | EventSel=F0H UMask=80H Counter=0,1,2,3 |
| L2_TRANSACTIONS.FILL | L2 fill transactions | EventSel=F0H UMask=20H Counter=0,1,2,3 |
| L2_TRANSACTIONS.IFETCH | L2 instruction fetch transactions | EventSel=F0H UMask=04H Counter=0,1,2,3 |
| L2_TRANSACTIONS.L1D_WB | L1D writeback to L2 transactions | EventSel=F0H UMask=10H Counter=0,1,2,3 |
| L2_TRANSACTIONS.LOAD | L2 Load transactions | EventSel=F0H UMask=01H Counter=0,1,2,3 |
| L2_TRANSACTIONS.PREFETCH | L2 prefetch transactions | EventSel=F0H UMask=08H Counter=0,1,2,3 |
| L2_TRANSACTIONS.RFO | L2 RFO transactions | EventSel=F0H UMask=02H Counter=0,1,2,3 |
| L2_TRANSACTIONS.WB | L2 writeback to LLC transactions | EventSel=F0H UMask=40H Counter=0,1,2,3 |
| L2_WRITE.LOCK.E_STATE | L2 demand lock RFOs in E state | EventSel=27H UMask=40H Counter=0,1,2,3 |
| L2_WRITE.LOCK.HIT | All demand L2 lock RFOs that hit the cache | EventSel=27H UMask=E0H Counter=0,1,2,3 |
| L2_WRITE.LOCK.I_STATE | L2 demand lock RFOs in I state (misses) | EventSel=27H UMask=10H Counter=0,1,2,3 |
| L2_WRITE.LOCK.M_STATE | L2 demand lock RFOs in M state | EventSel=27H UMask=80H Counter=0,1,2,3 |
| L2_WRITE.LOCK.MESI | All demand L2 lock RFOs | EventSel=27H UMask=F0H Counter=0,1,2,3 |
| L2_WRITE.LOCK.S_STATE | L2 demand lock RFOs in S state | EventSel=27H UMask=20H Counter=0,1,2,3 |
| L2_WRITE.RFO.HIT | All L2 demand store RFOs that hit the cache | EventSel=27H UMask=0EH Counter=0,1,2,3 |
| L2_WRITE.RFO.I_STATE | L2 demand store RFOs in I state (misses) | EventSel=27H UMask=01H Counter=0,1,2,3 |
| L2_WRITE.RFO.M_STATE | L2 demand store RFOs in M state | EventSel=27H UMask=08H Counter=0,1,2,3 |
| L2_WRITE.RFO.MESI | All L2 demand store RFOs | EventSel=27H UMask=0FH Counter=0,1,2,3 |
| L2_WRITE.RFO.S_STATE | L2 demand store RFOs in S state | EventSel=27H UMask=02H Counter=0,1,2,3 |
| LARGE_ITLB.HIT | Large ITLB hit | EventSel=82H UMask=01H Counter=0,1,2,3 |
| LOAD_BLOCK.OVERLAP_STORE | Loads that partially overlap an earlier store | EventSel=03H UMask=02H Counter=0,1,2,3 |
| LOAD_DISPATCH.ANY | All loads dispatched | EventSel=13H UMask=07H Counter=0,1,2,3 |
| LOAD_DISPATCH.MOB | Loads dispatched from the MOB | EventSel=13H UMask=04H Counter=0,1,2,3 |
| LOAD_DISPATCH.RS | Loads dispatched that bypass the MOB | EventSel=13H UMask=01H Counter=0,1,2,3 |
| LOAD_DISPATCH.RS_DELAYED | Loads dispatched from stage 305 | EventSel=13H UMask=02H Counter=0,1,2,3 |
| LOAD_HIT_PRE | Load operations conflicting with software prefetches | EventSel=4CH UMask=01H Counter=0,1 |
| LSD.ACTIVE | Cycles when uops were delivered by the LSD | EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3 |
| LSD.INACTIVE | Cycles no uops were delivered by the LSD | EventSel=A8H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| LSD_OVERFLOW | Loops that can't stream from the instruction queue | EventSel=20H UMask=01H Counter=0,1,2,3 |
| MACHINE_CLEARS.CYCLES | Cycles machine clear asserted | EventSel=C3H UMask=01H Counter=0,1,2,3 |
| MACHINE_CLEARS.MEM_ORDER | Execution pipeline restart due to Memory ordering conflicts | EventSel=C3H UMask=02H Counter=0,1,2,3 |
| MACHINE_CLEARS.SMC | Self-Modifying Code detected | EventSel=C3H UMask=04H Counter=0,1,2,3 |
| MACRO_INSTS.DECODED | Instructions decoded | EventSel=D0H UMask=01H Counter=0,1,2,3 |
| MACRO_INSTS.FUSIONS_DECODED | Macro-fused instructions decoded | EventSel=A6H UMask=01H Counter=0,1,2,3 |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0 | Memory instructions retired above 0 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=00H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024 | Memory instructions retired above 1024 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128 | Memory instructions retired above 128 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16 | Memory instructions retired above 16 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384 | Memory instructions retired above 16384 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=4000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048 | Memory instructions retired above 2048 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256 | Memory instructions retired above 256 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32 | Memory instructions retired above 32 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768 | Memory instructions retired above 32768 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=8000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4 | Memory instructions retired above 4 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096 | Memory instructions retired above 4096 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=1000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512 | Memory instructions retired above 512 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64 | Memory instructions retired above 64 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8 | Memory instructions retired above 8 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192 | Memory instructions retired above 8192 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=2000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LOADS | Instructions retired which contains a load (Precise Event) | EventSel=0BH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.LOADS_PS | Instructions retired which contains a load (Precise Event) | EventSel=0BH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.STORES | Instructions retired which contains a store (Precise Event) | EventSel=0BH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.STORES_PS | Instructions retired which contains a store (Precise Event) | EventSel=0BH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.DTLB_MISS | Retired loads that miss the DTLB (Precise Event) | EventSel=CBH UMask=80H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.DTLB_MISS_PS | Retired loads that miss the DTLB (Precise Event) | EventSel=CBH UMask=80H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.HIT_LFB | Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) | EventSel=CBH UMask=40H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.HIT_LFB_PS | Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) | EventSel=CBH UMask=40H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L1D_HIT | Retired loads that hit the L1 data cache (Precise Event) | EventSel=CBH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L1D_HIT_PS | Retired loads that hit the L1 data cache (Precise Event) | EventSel=CBH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L2_HIT | Retired loads that hit the L2 cache (Precise Event) | EventSel=CBH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L2_HIT_PS | Retired loads that hit the L2 cache (Precise Event) | EventSel=CBH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_MISS | Retired loads that miss the LLC cache (Precise Event) | EventSel=CBH UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_MISS_PS | Retired loads that miss the LLC cache (Precise Event) | EventSel=CBH UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_UNSHARED_HIT | Retired loads that hit valid versions in the LLC cache (Precise Event) | EventSel=CBH UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_UNSHARED_HIT_PS | Retired loads that hit valid versions in the LLC cache (Precise Event) | EventSel=CBH UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM | Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) | EventSel=CBH UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM_PS | Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) | EventSel=CBH UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_STORE_RETIRED.DTLB_MISS | Retired stores that miss the DTLB (Precise Event) | EventSel=0CH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_STORE_RETIRED.DTLB_MISS_PS | Retired stores that miss the DTLB (Precise Event) | EventSel=0CH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MISALIGN_MEM_REF.STORE | Misaligned store references | EventSel=05H UMask=02H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.ANY | All offcore requests | EventSel=B0H UMask=80H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.ANY.READ | Offcore read requests | EventSel=B0H UMask=08H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.ANY.RFO | Offcore RFO requests | EventSel=B0H UMask=10H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.DEMAND.READ_CODE | Offcore demand code read requests | EventSel=B0H UMask=02H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.DEMAND.READ_DATA | Offcore demand data read requests | EventSel=B0H UMask=01H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.DEMAND.RFO | Offcore demand RFO requests | EventSel=B0H UMask=04H Counter=0,1,2,3 |
| OFFCORE_REQUESTS.L1D_WRITEBACK | Offcore L1 data cache writebacks | EventSel=B0H UMask=40H Counter=0,1,2,3 |
| OFFCORE_REQUESTS_OUTSTANDING.ANY.READ | Outstanding offcore reads | EventSel=60H UMask=08H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY | Cycles offcore reads busy | EventSel=60H UMask=08H CMask=01H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE | Outstanding offcore demand code reads | EventSel=60H UMask=02H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EMPTY | Cycles offcore demand code read busy | EventSel=60H UMask=02H CMask=01H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA | Outstanding offcore demand data reads | EventSel=60H UMask=01H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EMPTY | Cycles offcore demand data read busy | EventSel=60H UMask=01H CMask=01H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO | Outstanding offcore demand RFOs | EventSel=60H UMask=04H Counter=0 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY | Cycles offcore demand RFOs busy | EventSel=60H UMask=04H CMask=01H Counter=0 |
| OFFCORE_REQUESTS_SQ_FULL | Offcore requests blocked due to Super Queue full | EventSel=B2H UMask=01H Counter=0,1,2,3 |
| PARTIAL_ADDRESS_ALIAS | False dependencies due to partial address aliasing | EventSel=07H UMask=01H Counter=0,1,2,3 |
| RAT_STALLS.ANY | All RAT stall cycles | EventSel=D2H UMask=0FH Counter=0,1,2,3 |
| RAT_STALLS.FLAGS | Flag stall cycles | EventSel=D2H UMask=01H Counter=0,1,2,3 |
| RAT_STALLS.REGISTERS | Partial register stall cycles | EventSel=D2H UMask=02H Counter=0,1,2,3 |
| RAT_STALLS.ROB_READ_PORT | ROB read port stalls cycles | EventSel=D2H UMask=04H Counter=0,1,2,3 |
| RAT_STALLS.SCOREBOARD | Scoreboard stall cycles | EventSel=D2H UMask=08H Counter=0,1,2,3 |
| RESOURCE_STALLS.ANY | Resource related stall cycles | EventSel=A2H UMask=01H Counter=0,1,2,3 |
| RESOURCE_STALLS.FPCW | FPU control word write stall cycles | EventSel=A2H UMask=20H Counter=0,1,2,3 |
| RESOURCE_STALLS.LOAD | Load buffer stall cycles | EventSel=A2H UMask=02H Counter=0,1,2,3 |
| RESOURCE_STALLS.MXCSR | MXCSR rename stall cycles | EventSel=A2H UMask=40H Counter=0,1,2,3 |
| RESOURCE_STALLS.OTHER | Other Resource related stall cycles | EventSel=A2H UMask=80H Counter=0,1,2,3 |
| RESOURCE_STALLS.ROB_FULL | ROB full stall cycles | EventSel=A2H UMask=10H Counter=0,1,2,3 |
| RESOURCE_STALLS.RS_FULL | Reservation Station full stall cycles | EventSel=A2H UMask=04H Counter=0,1,2,3 |
| RESOURCE_STALLS.STORE | Store buffer stall cycles | EventSel=A2H UMask=08H Counter=0,1,2,3 |
| SB_DRAIN.ANY | All Store buffer stall cycles | EventSel=04H UMask=07H Counter=0,1,2,3 |
| SEG_RENAME_STALLS | Segment rename stall cycles | EventSel=D4H UMask=01H Counter=0,1,2,3 |
| SIMD_INT_128.PACK | 128 bit SIMD integer pack operations | EventSel=12H UMask=04H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_ARITH | 128 bit SIMD integer arithmetic operations | EventSel=12H UMask=20H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_LOGICAL | 128 bit SIMD integer logical operations | EventSel=12H UMask=10H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_MPY | 128 bit SIMD integer multiply operations | EventSel=12H UMask=01H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_SHIFT | 128 bit SIMD integer shift operations | EventSel=12H UMask=02H Counter=0,1,2,3 |
| SIMD_INT_128.SHUFFLE_MOVE | 128 bit SIMD integer shuffle/move operations | EventSel=12H UMask=40H Counter=0,1,2,3 |
| SIMD_INT_128.UNPACK | 128 bit SIMD integer unpack operations | EventSel=12H UMask=08H Counter=0,1,2,3 |
| SIMD_INT_64.PACK | SIMD integer 64 bit pack operations | EventSel=FDH UMask=04H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_ARITH | SIMD integer 64 bit arithmetic operations | EventSel=FDH UMask=20H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_LOGICAL | SIMD integer 64 bit logical operations | EventSel=FDH UMask=10H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_MPY | SIMD integer 64 bit packed multiply operations | EventSel=FDH UMask=01H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_SHIFT | SIMD integer 64 bit shift operations | EventSel=FDH UMask=02H Counter=0,1,2,3 |
| SIMD_INT_64.SHUFFLE_MOVE | SIMD integer 64 bit shuffle/move operations | EventSel=FDH UMask=40H Counter=0,1,2,3 |
| SIMD_INT_64.UNPACK | SIMD integer 64 bit unpack operations | EventSel=FDH UMask=08H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HIT | Thread responded HIT to snoop | EventSel=B8H UMask=01H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HITE | Thread responded HITE to snoop | EventSel=B8H UMask=02H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HITM | Thread responded HITM to snoop | EventSel=B8H UMask=04H Counter=0,1,2,3 |
| SNOOPQ_REQUESTS.CODE | Snoop code requests | EventSel=B4H UMask=04H Counter=0,1,2,3 |
| SNOOPQ_REQUESTS.DATA | Snoop data requests | EventSel=B4H UMask=01H Counter=0,1,2,3 |
| SNOOPQ_REQUESTS.INVALIDATE | Snoop invalidate requests | EventSel=B4H UMask=02H Counter=0,1,2,3 |
| SNOOPQ_REQUESTS_OUTSTANDING.CODE | Outstanding snoop code requests | EventSel=B3H UMask=04H Counter=0 |
| SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY | Cycles snoop code requests queued | EventSel=B3H UMask=04H CMask=01H Counter=0 |
| SNOOPQ_REQUESTS_OUTSTANDING.DATA | Outstanding snoop data requests | EventSel=B3H UMask=01H Counter=0 |
| SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY | Cycles snoop data requests queued | EventSel=B3H UMask=01H CMask=01H Counter=0 |
| SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE | Outstanding snoop invalidate requests | EventSel=B3H UMask=02H Counter=0 |
| SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY | Cycles snoop invalidate requests queued | EventSel=B3H UMask=02H CMask=01H Counter=0 |
| SQ_FULL_STALL_CYCLES | Super Queue full stall cycles | EventSel=F6H UMask=01H Counter=0,1,2,3 |
| SQ_MISC.LRU_HINTS | Super Queue LRU hints sent to LLC | EventSel=F4H UMask=04H Counter=0,1,2,3 |
| SQ_MISC.SPLIT_LOCK | Super Queue lock splits across a cache line | EventSel=F4H UMask=10H Counter=0,1,2,3 |
| SSEX_UOPS_RETIRED.PACKED_DOUBLE | SIMD Packed-Double Uops retired (Precise Event) | EventSel=C7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_DOUBLE_PS | SIMD Packed-Double Uops retired (Precise Event) | EventSel=C7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_SINGLE | SIMD Packed-Single Uops retired (Precise Event) | EventSel=C7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_SINGLE_PS | SIMD Packed-Single Uops retired (Precise Event) | EventSel=C7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_DOUBLE | SIMD Scalar-Double Uops retired (Precise Event) | EventSel=C7H UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_DOUBLE_PS | SIMD Scalar-Double Uops retired (Precise Event) | EventSel=C7H UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_SINGLE | SIMD Scalar-Single Uops retired (Precise Event) | EventSel=C7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_SINGLE_PS | SIMD Scalar-Single Uops retired (Precise Event) | EventSel=C7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.VECTOR_INTEGER | SIMD Vector Integer Uops retired (Precise Event) | EventSel=C7H UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.VECTOR_INTEGER_PS | SIMD Vector Integer Uops retired (Precise Event) | EventSel=C7H UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| STORE_BLOCKS.AT_RET | Loads delayed with at-Retirement block code | EventSel=06H UMask=04H Counter=0,1,2,3 |
| STORE_BLOCKS.L1D_BLOCK | Cacheable loads delayed with L1D block code | EventSel=06H UMask=08H Counter=0,1,2,3 |
| TWO_UOP_INSTS_DECODED | Two Uop instructions decoded | EventSel=19H UMask=01H Counter=0,1,2,3 |
| UOP_UNFUSION | Uop unfusions due to FP exceptions | EventSel=DBH UMask=01H Counter=0,1,2,3 |
| UOPS_DECODED.ESP_FOLDING | Stack pointer instructions decoded | EventSel=D1H UMask=04H Counter=0,1,2,3 |
| UOPS_DECODED.ESP_SYNC | Stack pointer sync operations | EventSel=D1H UMask=08H Counter=0,1,2,3 |
| UOPS_DECODED.MS_CYCLES_ACTIVE | Uops decoded by Microcode Sequencer | EventSel=D1H UMask=02H CMask=01H Counter=0,1,2,3 |
| UOPS_DECODED.STALL_CYCLES | Cycles no Uops are decoded | EventSel=D1H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_ACTIVE_CYCLES | Cycles Uops executed on any port (core count) | EventSel=B1H UMask=3FH AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 | Cycles Uops executed on ports 0-4 (core count) | EventSel=B1H UMask=1FH AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_COUNT | Uops executed on any port (core count) | EventSel=B1H UMask=3FH EdgeDetect=1 AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5 | Uops executed on ports 0-4 (core count) | EventSel=B1H UMask=1FH EdgeDetect=1 AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_CYCLES | Cycles no Uops issued on any port (core count) | EventSel=B1H UMask=3FH AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5 | Cycles no Uops issued on ports 0-4 (core count) | EventSel=B1H UMask=1FH AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT0 | Uops executed on port 0 | EventSel=B1H UMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT015 | Uops issued on ports 0, 1 or 5 | EventSel=B1H UMask=40H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT015_STALL_CYCLES | Cycles no Uops issued on ports 0, 1 or 5 | EventSel=B1H UMask=40H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT1 | Uops executed on port 1 | EventSel=B1H UMask=02H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT2_CORE | Uops executed on port 2 (core count) | EventSel=B1H UMask=04H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT234_CORE | Uops issued on ports 2, 3 or 4 | EventSel=B1H UMask=80H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT3_CORE | Uops executed on port 3 (core count) | EventSel=B1H UMask=08H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT4_CORE | Uops executed on port 4 (core count) | EventSel=B1H UMask=10H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT5 | Uops executed on port 5 | EventSel=B1H UMask=20H Counter=0,1,2,3 |
| UOPS_ISSUED.ANY | Uops issued | EventSel=0EH UMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.CORE_STALL_CYCLES | Cycles no Uops were issued on any thread | EventSel=0EH UMask=01H AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.CYCLES_ALL_THREADS | Cycles Uops were issued on either thread | EventSel=0EH UMask=01H AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.FUSED | Fused Uops issued | EventSel=0EH UMask=02H Counter=0,1,2,3 |
| UOPS_ISSUED.STALL_CYCLES | Cycles no Uops were issued | EventSel=0EH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_RETIRED.ACTIVE_CYCLES | Cycles Uops are being retired | EventSel=C2H UMask=01H CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ACTIVE_CYCLES_PS | Cycles Uops are being retired | EventSel=C2H UMask=01H CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ANY | Uops retired (Precise Event) | EventSel=C2H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ANY_PS | Uops retired (Precise Event) | EventSel=C2H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.MACRO_FUSED | Macro-fused Uops retired (Precise Event) | EventSel=C2H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.MACRO_FUSED_PS | Macro-fused Uops retired (Precise Event) | EventSel=C2H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS | Retirement slots used (Precise Event) | EventSel=C2H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS_PS | Retirement slots used (Precise Event) | EventSel=C2H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES | Cycles Uops are not retiring (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES_PS | Cycles Uops are not retiring (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES | Total cycles using precise uop retired event (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES_PS | Total cycles using precise uop retired event (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UNCORE | ||
| UNC_ADDR_OPCODE_MATCH.IOH.NONE | UNC_ADDR_OPCODE_MATCH.IOH.NONE | EventSel=35H UMask=01H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDI | UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDI | EventSel=35H UMask=01H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDS | UNC_ADDR_OPCODE_MATCH.IOH.RSPFWDS | EventSel=35H UMask=01H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.IOH.RSPIWB | UNC_ADDR_OPCODE_MATCH.IOH.RSPIWB | EventSel=35H UMask=01H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.LOCAL.NONE | UNC_ADDR_OPCODE_MATCH.LOCAL.NONE | EventSel=35H UMask=04H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.LOCAL.RSPFWDI | hitm in local LLC rfo snoop | EventSel=35H UMask=04H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.LOCAL.RSPFWDS | local LLC in F or S, load snoop | EventSel=35H UMask=04H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.LOCAL.RSPIWB | hitm in local LLC, load snoop | EventSel=35H UMask=04H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.REMOTE.NONE | UNC_ADDR_OPCODE_MATCH.REMOTE.NONE | EventSel=35H UMask=02H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.REMOTE.RSPFWDI | hitm in remote LLC, rfo | EventSel=35H UMask=02H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.REMOTE.RSPFWDS | remote LLC in F or S, load | EventSel=35H UMask=02H Counter=0 |
| UNC_ADDR_OPCODE_MATCH.REMOTE.RSPIWB | hitm in remote LLC, load | EventSel=35H UMask=02H Counter=0 |
| UNC_CLOCKTICKS | Uncore clockticks | EventSel=00H UMask=00H Counter=8 |
| UNC_CYCLES_UNHALTED_LLC_FULL_DISABLE | Cycles LLC disabled | EventSel=86H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_CYCLES_UNHALTED_LLC_FULL_ENABLE | Cycles package not halted | EventSel=85H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_OPEN.CH0 | DRAM Channel 0 open commands | EventSel=60H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_OPEN.CH1 | DRAM Channel 1 open commands | EventSel=60H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_OPEN.CH2 | DRAM Channel 2 open commands | EventSel=60H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_CLOSE.CH0 | DRAM Channel 0 page close | EventSel=61H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_CLOSE.CH1 | DRAM Channel 1 page close | EventSel=61H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_CLOSE.CH2 | DRAM Channel 2 page close | EventSel=61H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_MISS.CH0 | DRAM Channel 0 page miss | EventSel=62H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_MISS.CH1 | DRAM Channel 1 page miss | EventSel=62H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PAGE_MISS.CH2 | DRAM Channel 2 page miss | EventSel=62H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PRE_ALL.CH0 | DRAM Channel 0 precharge all commands | EventSel=66H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PRE_ALL.CH1 | DRAM Channel 1 precharge all commands | EventSel=66H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_PRE_ALL.CH2 | DRAM Channel 2 precharge all commands | EventSel=66H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.AUTOPRE_CH0 | DRAM Channel 0 read CAS auto page close commands | EventSel=63H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.AUTOPRE_CH1 | DRAM Channel 1 read CAS auto page close commands | EventSel=63H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.AUTOPRE_CH2 | DRAM Channel 2 read CAS auto page close commands | EventSel=63H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.CH0 | DRAM Channel 0 read CAS commands | EventSel=63H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.CH1 | DRAM Channel 1 read CAS commands | EventSel=63H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_READ_CAS.CH2 | DRAM Channel 2 read CAS commands | EventSel=63H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_REFRESH.CH0 | DRAM Channel 0 refresh commands | EventSel=65H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_REFRESH.CH1 | DRAM Channel 1 refresh commands | EventSel=65H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_REFRESH.CH2 | DRAM Channel 2 refresh commands | EventSel=65H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_THERMAL_THROTTLED | Cycles DRAM thermal throttled | EventSel=67H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.AUTOPRE_CH0 | DRAM Channel 0 write CAS auto page close commands | EventSel=64H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.AUTOPRE_CH1 | DRAM Channel 1 write CAS auto page close commands | EventSel=64H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.AUTOPRE_CH2 | DRAM Channel 2 write CAS auto page close commands | EventSel=64H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.CH0 | DRAM Channel 0 write CAS commands | EventSel=64H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.CH1 | DRAM Channel 1 write CAS commands | EventSel=64H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_DRAM_WRITE_CAS.CH2 | DRAM Channel 2 write CAS commands | EventSel=64H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.PEER_PROBE_TRACKER | GQ peer probe tracker requests | EventSel=03H UMask=40H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.READ_TRACKER | GQ read tracker requests | EventSel=03H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.RT_LLC_MISS | GQ read tracker LLC misses | EventSel=03H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.RT_TO_LLC_RESP | GQ read tracker LLC requests | EventSel=03H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.RT_TO_RTID_ACQUIRED | GQ read tracker LLC miss to RTID acquired | EventSel=03H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.WRITE_TRACKER | GQ write tracker LLC misses | EventSel=03H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_ALLOC.WT_TO_RTID_ACQUIRED | GQ write tracker LLC miss to RTID acquired | EventSel=03H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_FULL.PEER_PROBE_TRACKER | Cycles GQ peer probe tracker is full. | EventSel=00H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_FULL.READ_TRACKER | Cycles GQ read tracker is full. | EventSel=00H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_FULL.WRITE_TRACKER | Cycles GQ write tracker is full. | EventSel=00H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER | Cycles GQ peer probe tracker is busy | EventSel=01H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_NOT_EMPTY.READ_TRACKER | Cycles GQ read tracker is busy | EventSel=01H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER | Cycles GQ write tracker is busy | EventSel=01H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.FROM_CORES_02 | Cycles GQ data is imported from Cores 0 and 2 | EventSel=04H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.FROM_CORES_13 | Cycles GQ data is imported from Cores 1 and 3 | EventSel=04H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.FROM_IMC | Cycles GQ data is imported from Integrated Memory Controller | EventSel=04H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.FROM_LLC | Cycles GQ data is imported from LLC | EventSel=04H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.FROM_QPI | Cycles GQ data is imported from Quickpath interface | EventSel=04H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.TO_CORES | Cycles GQ data sent to cores | EventSel=05H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.TO_LLC | Cycles GQ data sent to LLC | EventSel=05H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_DATA.TO_QPI_IMC | Cycles GQ data sent to the interconnect or IMC | EventSel=05H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.PEER_PROBE_TRACKER | GQ peer probe tracker LLC miss occupancy | EventSel=02H UMask=40H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.READ_TRACKER | GQ read tracker occupancy | EventSel=02H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.RT_LLC_MISS | GQ read tracker LLC miss occupancy | EventSel=02H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.RT_LLC_MISS_NOT_EMPTY | Cycles GQ read tracker LLC miss queued | EventSel=02H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.RT_TO_LLC_RESP | GQ read tracker LLC hit occupancy | EventSel=02H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.RT_TO_LLC_RESP_NOT_EMPTY | GQ read tracker LLC request queued | EventSel=02H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.RT_TO_RTID_ACQUIRED | GQ read tracker LLC miss to RTID acquired occupancy | EventSel=02H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.WRITE_TRACKER | GQ write tracker LLC miss occupancy | EventSel=02H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_OCCUPANCY.WT_TO_RTID_ACQUIRED | GQ write tracker LLC miss to RTID acquired occupancy | EventSel=02H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_SNOOP.GOTO_I | Remote snoop requests to change cache line to I state | EventSel=0CH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_SNOOP.GOTO_I_HIT_E | Remote snoop requests to change cache line from E to I state | EventSel=0CH UMask=08H Counter=1 |
| UNC_GQ_SNOOP.GOTO_I_HIT_F | Remote snoop requests to change cache line from F to I state | EventSel=0CH UMask=08H Counter=1 |
| UNC_GQ_SNOOP.GOTO_I_HIT_M | Remote snoop requests to change cache line from M to I state | EventSel=0CH UMask=08H Counter=1 |
| UNC_GQ_SNOOP.GOTO_I_HIT_S | Remote snoop requests to change cache line from S to I state | EventSel=0CH UMask=08H Counter=1 |
| UNC_GQ_SNOOP.GOTO_S | Remote snoop requests to change cache line to S state | EventSel=0CH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_GQ_SNOOP.GOTO_S_HIT_E | Remote snoop requests to change cache line from E to S state | EventSel=0CH UMask=04H Counter=1 |
| UNC_GQ_SNOOP.GOTO_S_HIT_F | Remote snoop requests to change cache line from F to S state | EventSel=0CH UMask=04H Counter=1 |
| UNC_GQ_SNOOP.GOTO_S_HIT_M | Remote snoop requests to change cache line from M to S state | EventSel=0CH UMask=04H Counter=1 |
| UNC_GQ_SNOOP.GOTO_S_HIT_S | Remote snoop requests to change cache line from S to S state | EventSel=0CH UMask=04H Counter=1 |
| UNC_IMC_BUSY.READ.CH0 | Cycles IMC channel 0 busy with a read request | EventSel=29H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_BUSY.READ.CH1 | Cycles IMC channel 1 busy with a read request | EventSel=29H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_BUSY.READ.CH2 | Cycles IMC channel 2 busy with a read request | EventSel=29H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_BUSY.WRITE.CH0 | Cycles IMC channel 0 busy with a write request | EventSel=29H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_BUSY.WRITE.CH1 | Cycles IMC channel 1 busy with a write request | EventSel=29H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_BUSY.WRITE.CH2 | Cycles IMC channel 2 busy with a write request | EventSel=29H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CANCEL.ANY | IMC cancels | EventSel=30H UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CANCEL.CH0 | IMC channel 0 cancels | EventSel=30H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CANCEL.CH1 | IMC channel 1 cancels | EventSel=30H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CANCEL.CH2 | IMC channel 2 cancels | EventSel=30H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CRITICAL_PRIORITY_READS.ANY | IMC critical priority read requests | EventSel=2EH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CRITICAL_PRIORITY_READS.CH0 | IMC channel 0 critical priority read requests | EventSel=2EH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CRITICAL_PRIORITY_READS.CH1 | IMC channel 1 critical priority read requests | EventSel=2EH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_CRITICAL_PRIORITY_READS.CH2 | IMC channel 2 critical priority read requests | EventSel=2EH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_HIGH_PRIORITY_READS.ANY | IMC high priority read requests | EventSel=2DH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_HIGH_PRIORITY_READS.CH0 | IMC channel 0 high priority read requests | EventSel=2DH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_HIGH_PRIORITY_READS.CH1 | IMC channel 1 high priority read requests | EventSel=2DH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_HIGH_PRIORITY_READS.CH2 | IMC channel 2 high priority read requests | EventSel=2DH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.READ.CH0 | Cycles DRAM channel 0 full with ISOC read requests | EventSel=28H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.READ.CH1 | Cycles DRAM channel 1 full with ISOC read requests | EventSel=28H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.READ.CH2 | Cycles DRAM channel 2 full with ISOC read requests | EventSel=28H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.WRITE.CH0 | Cycles DRAM channel 0 full with ISOC write requests | EventSel=28H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.WRITE.CH1 | Cycles DRAM channel 1 full with ISOC write requests | EventSel=28H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_FULL.WRITE.CH2 | Cycles DRAM channel 2 full with ISOC write requests | EventSel=28H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_OCCUPANCY.ANY | IMC ISOC read request occupancy | EventSel=2BH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_OCCUPANCY.CH0 | IMC channel 0 ISOC read request occupancy | EventSel=2BH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_OCCUPANCY.CH1 | IMC channel 1 ISOC read request occupancy | EventSel=2BH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_ISOC_OCCUPANCY.CH2 | IMC channel 2 ISOC read request occupancy | EventSel=2BH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_OCCUPANCY.ANY | IMC normal read request occupancy | EventSel=2AH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_OCCUPANCY.CH0 | IMC channel 0 normal read request occupancy | EventSel=2AH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_OCCUPANCY.CH1 | IMC channel 1 normal read request occupancy | EventSel=2AH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_OCCUPANCY.CH2 | IMC channel 2 normal read request occupancy | EventSel=2AH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_READS.ANY | IMC normal read requests | EventSel=2CH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_READS.CH0 | IMC channel 0 normal read requests | EventSel=2CH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_READS.CH1 | IMC channel 1 normal read requests | EventSel=2CH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_NORMAL_READS.CH2 | IMC channel 2 normal read requests | EventSel=2CH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_PRIORITY_UPDATES.ANY | IMC priority updates | EventSel=31H UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_PRIORITY_UPDATES.CH0 | IMC channel 0 priority updates | EventSel=31H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_PRIORITY_UPDATES.CH1 | IMC channel 1 priority updates | EventSel=31H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_PRIORITY_UPDATES.CH2 | IMC channel 2 priority updates | EventSel=31H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_RETRY.ANY | IMC retries | EventSel=32H UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_RETRY.CH0 | IMC Channel 0 retries | EventSel=32H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_RETRY.CH1 | IMC Channel 1 retries | EventSel=32H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_RETRY.CH2 | IMC Channel 2 retries | EventSel=32H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.FULL.ANY | IMC full cache line writes | EventSel=2FH UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.FULL.CH0 | IMC channel 0 full cache line writes | EventSel=2FH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.FULL.CH1 | IMC channel 1 full cache line writes | EventSel=2FH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.FULL.CH2 | IMC channel 2 full cache line writes | EventSel=2FH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.PARTIAL.ANY | IMC partial cache line writes | EventSel=2FH UMask=38H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.PARTIAL.CH0 | IMC channel 0 partial cache line writes | EventSel=2FH UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.PARTIAL.CH1 | IMC channel 1 partial cache line writes | EventSel=2FH UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_IMC_WRITES.PARTIAL.CH2 | IMC channel 2 partial cache line writes | EventSel=2FH UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_HITS.ANY | Number of LLC hits | EventSel=08H UMask=03H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_HITS.PROBE | Number of LLC peer probe hits | EventSel=08H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_HITS.READ | Number of LLC read hits | EventSel=08H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_HITS.WRITEBACKS | Number of LLC write hits | EventSel=08H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_IN.ANY | LLC lines allocated | EventSel=0AH UMask=0FH Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_IN.E_STATE | LLC lines allocated in E state | EventSel=0AH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_IN.F_STATE | LLC lines allocated in F state | EventSel=0AH UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_IN.M_STATE | LLC lines allocated in M state | EventSel=0AH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_IN.S_STATE | LLC lines allocated in S state | EventSel=0AH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.ANY | LLC lines victimized | EventSel=0BH UMask=1FH Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.E_STATE | LLC lines victimized in E state | EventSel=0BH UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.F_STATE | LLC lines victimized in F state | EventSel=0BH UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.I_STATE | LLC lines victimized in I state | EventSel=0BH UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.M_STATE | LLC lines victimized in M state | EventSel=0BH UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_LINES_OUT.S_STATE | LLC lines victimized in S state | EventSel=0BH UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_MISS.ANY | Number of LLC misses | EventSel=09H UMask=03H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_MISS.PROBE | Number of LLC peer probe misses | EventSel=09H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_MISS.READ | Number of LLC read misses | EventSel=09H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_LLC_MISS.WRITEBACKS | Number of LLC write misses | EventSel=09H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_PROCHOT_ASSERTION | PROCHOT system assertions | EventSel=82H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_ADDRESS_CONFLICTS.2WAY | QHL 2 way address conflicts | EventSel=24H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_ADDRESS_CONFLICTS.3WAY | QHL 3 way address conflicts | EventSel=24H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_ADDRESS_CONFLICTS.NONE | QHL no address conflicts | EventSel=24H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CONFLICT_CYCLES.IOH | QHL IOH Tracker conflict cycles | EventSel=25H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CONFLICT_CYCLES.LOCAL | QHL Local Tracker conflict cycles | EventSel=25H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CONFLICT_CYCLES.REMOTE | QHL Remote Tracker conflict cycles | EventSel=25H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_FULL.IOH | Cycles QHL IOH Tracker is full | EventSel=21H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_FULL.LOCAL | Cycles QHL Local Tracker is full | EventSel=21H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_FULL.REMOTE | Cycles QHL Remote Tracker is full | EventSel=21H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_NOT_EMPTY.IOH | Cycles QHL IOH tracker is busy | EventSel=22H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_NOT_EMPTY.LOCAL | Cycles QHL local tracker is busy | EventSel=22H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_CYCLES_NOT_EMPTY.REMOTE | Cycles QHL remote tracker is busy | EventSel=22H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_FRC_ACK_CNFLTS.ANY | QHL FrcAckCnflts sent | EventSel=33H UMask=07H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_FRC_ACK_CNFLTS.IOH | QHL FrcAckCnflts sent to IOH | EventSel=33H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_FRC_ACK_CNFLTS.LOCAL | QHL FrcAckCnflts sent to local home | EventSel=33H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_FRC_ACK_CNFLTS.REMOTE | QHL FrcAckCnflts sent to remote home | EventSel=33H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_OCCUPANCY.IOH | QHL IOH tracker allocate to deallocate occupancy | EventSel=23H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_OCCUPANCY.LOCAL | QHL local tracker allocate to deallocate occupancy | EventSel=23H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_OCCUPANCY.REMOTE | QHL remote tracker allocate to deallocate occupancy | EventSel=23H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.IOH_READS | Quickpath Home Logic IOH read requests | EventSel=20H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.IOH_WRITES | Quickpath Home Logic IOH write requests | EventSel=20H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.LOCAL_READS | Quickpath Home Logic local read requests | EventSel=20H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.LOCAL_WRITES | Quickpath Home Logic local write requests | EventSel=20H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.REMOTE_READS | Quickpath Home Logic remote read requests | EventSel=20H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_REQUESTS.REMOTE_WRITES | Quickpath Home Logic remote write requests | EventSel=20H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.IOH_CONFLICT | Sleeps due to IOH address conflicts | EventSel=34H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.IOH_ORDER | Sleeps due to IOH order conflicts | EventSel=34H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.LOCAL_CONFLICT | Sleeps due to local address conflicts | EventSel=34H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.LOCAL_ORDER | Sleeps due to local order conflicts | EventSel=34H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.REMOTE_CONFLICT | Sleeps due to remote address conflicts | EventSel=34H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_SLEEPS.REMOTE_ORDER | Sleeps due to remote order conflicts | EventSel=34H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QHL_TO_IMC_BYPASS | Number of requests to IMC that bypass QHL | EventSel=26H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.DRS_NDR.LINK_0 | Cycles QPI DRS/NDR Link 0 reserved for forward progress | EventSel=12H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.DRS_NDR.LINK_1 | Cycles QPI DRS/NDR Link 1 reserved for forward progress | EventSel=12H UMask=40H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.HOME.LINK_0 | Cycles QPI Home Link 0 reserved for forward progress | EventSel=12H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.HOME.LINK_1 | Cycles QPI Home Link 1 reserved for forward progress | EventSel=12H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.NCS_NCB.LINK_0 | Cycles QPI NCS/NCB Link 0 reserved for forward progress | EventSel=12H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.NCS_NCB.LINK_1 | Cycles QPI NCS/NCB Link 1 reserved for forward progress | EventSel=12H UMask=80H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.SNOOP.LINK_0 | Cycles QPI Snoop Link 0 reserved for forward progress | EventSel=12H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_QPI_RESERVED_CYCLES.SNOOP.LINK_1 | Cycles QPI Snoop Link 1 reserved for forward progress | EventSel=12H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.CONFLICT | Local home conflict snoop response | EventSel=06H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE | Local home snoop response - LLC has forwarded a modified cache line | EventSel=06H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE | Local home snoop response - LLC forwarding cache line in S state. | EventSel=06H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.HIT | Local home snoop response - LLC HIT | EventSel=06H UMask=1AH Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.HITM | Local home snoop response - LLC HITM | EventSel=06H UMask=24H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.I_STATE | Local home snoop response - LLC does not have cache line | EventSel=06H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.S_STATE | Local home snoop response - LLC has cache line in S state | EventSel=06H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_LOCAL_HOME.WB | Local home snoop response - LLC has cache line in the M state | EventSel=06H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.CONFLICT | Remote home conflict snoop response | EventSel=07H UMask=10H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE | Remote home snoop response - LLC has forwarded a modified cache line | EventSel=07H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE | Remote home snoop response - LLC forwarding cache line in S state. | EventSel=07H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.HIT | Remote home snoop response - LLC HIT | EventSel=07H UMask=1AH Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.HITM | Remote home snoop response - LLC HITM | EventSel=07H UMask=24H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.I_STATE | Remote home snoop response - LLC does not have cache line | EventSel=07H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.S_STATE | Remote home snoop response - LLC has cache line in S state | EventSel=07H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_SNP_RESP_TO_REMOTE_HOME.WB | Remote home snoop response - LLC has cache line in the M state | EventSel=07H UMask=20H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLED.CORE_0 | Cycles core 0 thermal throttled | EventSel=81H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLED.CORE_1 | Cycles core 1 thermal throttled | EventSel=81H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLED.CORE_2 | Cycles core 2 thermal throttled | EventSel=81H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLED.CORE_3 | Cycles core 3 thermal throttled | EventSel=81H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_PROCHOT.CORE_0 | Cycles core 0 PROCHOT throttled | EventSel=83H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_PROCHOT.CORE_1 | Cycles core 1 PROCHOT throttled | EventSel=83H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_PROCHOT.CORE_2 | Cycles core 2 PROCHOT throttled | EventSel=83H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_PROCHOT.CORE_3 | Cycles core 3 PROCHOT throttled | EventSel=83H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_TEMP.CORE_0 | Cycles core 0 above thermal throttling temperature | EventSel=80H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_TEMP.CORE_1 | Cycles core 1 above thermal throttling temperature | EventSel=80H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_TEMP.CORE_2 | Cycles core 2 above thermal throttling temperature | EventSel=80H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_THERMAL_THROTTLING_TEMP.CORE_3 | Cycles core 3 above thermal throttling temperature | EventSel=80H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| UNC_TURBO_MODE.CORE_0 | Cycles core 0 in turbo mode | EventSel=84H UMask=01H Counter=0,1,2,3,4,5,6,7 |
| UNC_TURBO_MODE.CORE_1 | Cycles core 1 in turbo mode | EventSel=84H UMask=02H Counter=0,1,2,3,4,5,6,7 |
| UNC_TURBO_MODE.CORE_2 | Cycles core 2 in turbo mode | EventSel=84H UMask=04H Counter=0,1,2,3,4,5,6,7 |
| UNC_TURBO_MODE.CORE_3 | Cycles core 3 in turbo mode | EventSel=84H UMask=08H Counter=0,1,2,3,4,5,6,7 |
| OFFCORE |