| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | Instructions retired (fixed counter) | IA32_FIXED_CTR0 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD | Cycles when thread is not halted (fixed counter) | IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.REF | Reference cycles when thread is not halted (fixed counter) | IA32_FIXED_CTR2 Architectural, Fixed |
| BR_INST_RETIRED.ALL_BRANCHES | Retired branch instructions (Precise Event) | EventSel=C4H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] Architectural |
| CPU_CLK_UNHALTED.REF_P | Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter) | EventSel=3CH UMask=01H Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.THREAD_P | Cycles when thread is not halted (programmable counter) | EventSel=3CH UMask=00H Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.TOTAL_CYCLES | Total CPU cycles | EventSel=3CH UMask=00H Invert=1 CMask=02H Counter=0,1,2,3 Architectural |
| LONGEST_LAT_CACHE.MISS | Longest latency cache miss | EventSel=2EH UMask=41H Counter=0,1,2,3 Architectural |
| LONGEST_LAT_CACHE.REFERENCE | Longest latency cache reference | EventSel=2EH UMask=4FH Counter=0,1,2,3 Architectural |
| ARITH.CYCLES_DIV_BUSY | Cycles the divider is busy | EventSel=14H UMask=01H Counter=0,1,2,3 |
| ARITH.DIV | Divide Operations executed | EventSel=14H UMask=01H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| ARITH.MUL | Multiply operations executed | EventSel=14H UMask=02H Counter=0,1,2,3 |
| BACLEAR.BAD_TARGET | BACLEAR asserted with bad target address | EventSel=E6H UMask=02H Counter=0,1,2,3 |
| BACLEAR.CLEAR | BACLEAR asserted, regardless of cause | EventSel=E6H UMask=01H Counter=0,1,2,3 |
| BACLEAR_FORCE_IQ | Instruction queue forced BACLEAR | EventSel=A7H UMask=01H Counter=0,1,2,3 |
| BPU_CLEARS.EARLY | Early Branch Prediction Unit clears | EventSel=E8H UMask=01H Counter=0,1,2,3 |
| BPU_CLEARS.LATE | Late Branch Prediction Unit clears | EventSel=E8H UMask=02H Counter=0,1,2,3 |
| BPU_MISSED_CALL_RET | Branch prediction unit missed call or return | EventSel=E5H UMask=01H Counter=0,1,2,3 |
| BR_INST_DECODED | Branch instructions decoded | EventSel=E0H UMask=01H Counter=0,1,2,3 |
| BR_INST_EXEC.ANY | Branch instructions executed | EventSel=88H UMask=7FH Counter=0,1,2,3 |
| BR_INST_EXEC.COND | Conditional branch instructions executed | EventSel=88H UMask=01H Counter=0,1,2,3 |
| BR_INST_EXEC.DIRECT | Unconditional branches executed | EventSel=88H UMask=02H Counter=0,1,2,3 |
| BR_INST_EXEC.DIRECT_NEAR_CALL | Unconditional call branches executed | EventSel=88H UMask=10H Counter=0,1,2,3 |
| BR_INST_EXEC.INDIRECT_NEAR_CALL | Indirect call branches executed | EventSel=88H UMask=20H Counter=0,1,2,3 |
| BR_INST_EXEC.INDIRECT_NON_CALL | Indirect non call branches executed | EventSel=88H UMask=04H Counter=0,1,2,3 |
| BR_INST_EXEC.NEAR_CALLS | Call branches executed | EventSel=88H UMask=30H Counter=0,1,2,3 |
| BR_INST_EXEC.NON_CALLS | All non call branches executed | EventSel=88H UMask=07H Counter=0,1,2,3 |
| BR_INST_EXEC.RETURN_NEAR | Indirect return branches executed | EventSel=88H UMask=08H Counter=0,1,2,3 |
| BR_INST_EXEC.TAKEN | Taken branches executed | EventSel=88H UMask=40H Counter=0,1,2,3 |
| BR_INST_RETIRED.ALL_BRANCHES_PS | Retired branch instructions (Precise Event) | EventSel=C4H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL | Retired conditional branch instructions (Precise Event) | EventSel=C4H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL_PS | Retired conditional branch instructions (Precise Event) | EventSel=C4H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL | Retired near call instructions (Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_PS | Retired near call instructions (Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3 | Retired near call instructions Ring 3 only(Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3_PS | Retired near call instructions Ring 3 only(Precise Event) | EventSel=C4H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_EXEC.ANY | Mispredicted branches executed | EventSel=89H UMask=7FH Counter=0,1,2,3 |
| BR_MISP_EXEC.COND | Mispredicted conditional branches executed | EventSel=89H UMask=01H Counter=0,1,2,3 |
| BR_MISP_EXEC.DIRECT | Mispredicted unconditional branches executed | EventSel=89H UMask=02H Counter=0,1,2,3 |
| BR_MISP_EXEC.DIRECT_NEAR_CALL | Mispredicted non call branches executed | EventSel=89H UMask=10H Counter=0,1,2,3 |
| BR_MISP_EXEC.INDIRECT_NEAR_CALL | Mispredicted indirect call branches executed | EventSel=89H UMask=20H Counter=0,1,2,3 |
| BR_MISP_EXEC.INDIRECT_NON_CALL | Mispredicted indirect non call branches executed | EventSel=89H UMask=04H Counter=0,1,2,3 |
| BR_MISP_EXEC.NEAR_CALLS | Mispredicted call branches executed | EventSel=89H UMask=30H Counter=0,1,2,3 |
| BR_MISP_EXEC.NON_CALLS | Mispredicted non call branches executed | EventSel=89H UMask=07H Counter=0,1,2,3 |
| BR_MISP_EXEC.RETURN_NEAR | Mispredicted return branches executed | EventSel=89H UMask=08H Counter=0,1,2,3 |
| BR_MISP_EXEC.TAKEN | Mispredicted taken branches executed | EventSel=89H UMask=40H Counter=0,1,2,3 |
| BR_MISP_RETIRED.NEAR_CALL | Mispredicted near retired calls (Precise Event) | EventSel=C5H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_CALL_PS | Mispredicted near retired calls (Precise Event) | EventSel=C5H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| CACHE_LOCK_CYCLES.L1D | Cycles L1D locked | EventSel=63H UMask=02H Counter=0,1 |
| CACHE_LOCK_CYCLES.L1D_L2 | Cycles L1D and L2 locked | EventSel=63H UMask=01H Counter=0,1 |
| DTLB_LOAD_MISSES.ANY | DTLB load misses | EventSel=08H UMask=01H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.PDE_MISS | DTLB load miss caused by low part of address | EventSel=08H UMask=20H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.STLB_HIT | DTLB second level hit | EventSel=08H UMask=10H Counter=0,1,2,3 |
| DTLB_LOAD_MISSES.WALK_COMPLETED | DTLB load miss page walks complete | EventSel=08H UMask=02H Counter=0,1,2,3 |
| DTLB_MISSES.ANY | DTLB misses | EventSel=49H UMask=01H Counter=0,1,2,3 |
| DTLB_MISSES.STLB_HIT | DTLB first level misses but second level hit | EventSel=49H UMask=10H Counter=0,1,2,3 |
| DTLB_MISSES.WALK_COMPLETED | DTLB miss page walks | EventSel=49H UMask=02H Counter=0,1,2,3 |
| ES_REG_RENAMES | ES segment renames | EventSel=D5H UMask=01H Counter=0,1,2,3 |
| FP_ASSIST.ALL | X87 Floating point assists (Precise Event) | EventSel=F7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.ALL_PS | X87 Floating point assists (Precise Event) | EventSel=F7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.INPUT | X87 Floating point assists for invalid input value (Precise Event) | EventSel=F7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.INPUT_PS | X87 Floating point assists for invalid input value (Precise Event) | EventSel=F7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.OUTPUT | X87 Floating point assists for invalid output value (Precise Event) | EventSel=F7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.OUTPUT_PS | X87 Floating point assists for invalid output value (Precise Event) | EventSel=F7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_COMP_OPS_EXE.MMX | MMX Uops | EventSel=10H UMask=02H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION | SSE* FP double precision Uops | EventSel=10H UMask=80H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP | SSE and SSE2 FP Uops | EventSel=10H UMask=04H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP_PACKED | SSE FP packed Uops | EventSel=10H UMask=10H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_FP_SCALAR | SSE FP scalar Uops | EventSel=10H UMask=20H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION | SSE* FP single precision Uops | EventSel=10H UMask=40H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.SSE2_INTEGER | SSE2 integer Uops | EventSel=10H UMask=08H Counter=0,1,2,3 |
| FP_COMP_OPS_EXE.X87 | Computational floating-point operations executed | EventSel=10H UMask=01H Counter=0,1,2,3 |
| FP_MMX_TRANS.ANY | All Floating Point to and from MMX transitions | EventSel=CCH UMask=03H Counter=0,1,2,3 |
| FP_MMX_TRANS.TO_FP | Transitions from MMX to Floating Point instructions | EventSel=CCH UMask=01H Counter=0,1,2,3 |
| FP_MMX_TRANS.TO_MMX | Transitions from Floating Point to MMX instructions | EventSel=CCH UMask=02H Counter=0,1,2,3 |
| ILD_STALL.ANY | Any Instruction Length Decoder stall cycles | EventSel=87H UMask=0FH Counter=0,1,2,3 |
| ILD_STALL.IQ_FULL | Instruction Queue full stall cycles | EventSel=87H UMask=04H Counter=0,1,2,3 |
| ILD_STALL.LCP | Length Change Prefix stall cycles | EventSel=87H UMask=01H Counter=0,1,2,3 |
| ILD_STALL.MRU | Stall cycles due to BPU MRU bypass | EventSel=87H UMask=02H Counter=0,1,2,3 |
| ILD_STALL.REGEN | Regen stall cycles | EventSel=87H UMask=08H Counter=0,1,2,3 |
| INST_DECODED.DEC0 | Instructions that must be decoded by decoder 0 | EventSel=18H UMask=01H Counter=0,1,2,3 |
| INST_QUEUE_WRITE_CYCLES | Cycles instructions are written to the instruction queue | EventSel=1EH UMask=01H Counter=0,1,2,3 |
| INST_QUEUE_WRITES | Instructions written to instruction queue. | EventSel=17H UMask=01H Counter=0,1,2,3 |
| INST_RETIRED.ANY_P | Instructions retired (Programmable counter and Precise Event) | EventSel=C0H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.ANY_P_PS | Instructions retired (Programmable counter and Precise Event) | EventSel=C0H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.MMX | Retired MMX instructions (Precise Event) | EventSel=C0H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.MMX_PS | Retired MMX instructions (Precise Event) | EventSel=C0H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.TOTAL_CYCLES | Total cycles (Precise Event) | EventSel=C0H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.TOTAL_CYCLES_PS | Total cycles (Precise Event) | EventSel=C0H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.X87 | Retired floating-point operations (Precise Event) | EventSel=C0H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| INST_RETIRED.X87_PS | Retired floating-point operations (Precise Event) | EventSel=C0H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| IO_TRANSACTIONS | I/O transactions | EventSel=6CH UMask=01H Counter=0,1,2,3 |
| ITLB_FLUSH | ITLB flushes | EventSel=AEH UMask=01H Counter=0,1,2,3 |
| ITLB_MISS_RETIRED | Retired instructions that missed the ITLB (Precise Event) | EventSel=C8H UMask=20H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| ITLB_MISS_RETIRED_PS | Retired instructions that missed the ITLB (Precise Event) | EventSel=C8H UMask=20H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| ITLB_MISSES.ANY | ITLB miss | EventSel=85H UMask=01H Counter=0,1,2,3 |
| ITLB_MISSES.WALK_COMPLETED | ITLB miss page walks | EventSel=85H UMask=02H Counter=0,1,2,3 |
| L1D.M_EVICT | L1D cache lines replaced in M state | EventSel=51H UMask=04H Counter=0,1 |
| L1D.M_REPL | L1D cache lines allocated in the M state | EventSel=51H UMask=02H Counter=0,1 |
| L1D.M_SNOOP_EVICT | L1D snoop eviction of cache lines in M state | EventSel=51H UMask=08H Counter=0,1 |
| L1D.REPL | L1 data cache lines allocated | EventSel=51H UMask=01H Counter=0,1 |
| L1D_ALL_REF.ANY | All references to the L1 data cache | EventSel=43H UMask=01H Counter=0,1 |
| L1D_ALL_REF.CACHEABLE | L1 data cacheable reads and writes | EventSel=43H UMask=02H Counter=0,1 |
| L1D_CACHE_LD.E_STATE | L1 data cache read in E state | EventSel=40H UMask=04H Counter=0,1 |
| L1D_CACHE_LD.I_STATE | L1 data cache read in I state (misses) | EventSel=40H UMask=01H Counter=0,1 |
| L1D_CACHE_LD.M_STATE | L1 data cache read in M state | EventSel=40H UMask=08H Counter=0,1 |
| L1D_CACHE_LD.MESI | L1 data cache reads | EventSel=40H UMask=0FH Counter=0,1 |
| L1D_CACHE_LD.S_STATE | L1 data cache read in S state | EventSel=40H UMask=02H Counter=0,1 |
| L1D_CACHE_LOCK.E_STATE | L1 data cache load locks in E state | EventSel=42H UMask=04H Counter=0,1 |
| L1D_CACHE_LOCK.HIT | L1 data cache load lock hits | EventSel=42H UMask=01H Counter=0,1 |
| L1D_CACHE_LOCK.M_STATE | L1 data cache load locks in M state | EventSel=42H UMask=08H Counter=0,1 |
| L1D_CACHE_LOCK.S_STATE | L1 data cache load locks in S state | EventSel=42H UMask=02H Counter=0,1 |
| L1D_CACHE_LOCK_FB_HIT | L1D load lock accepted in fill buffer | EventSel=53H UMask=01H Counter=0,1 |
| L1D_CACHE_PREFETCH_LOCK_FB_HIT | L1D prefetch load lock accepted in fill buffer | EventSel=52H UMask=01H Counter=0,1 |
| L1D_CACHE_ST.E_STATE | L1 data cache stores in E state | EventSel=41H UMask=04H Counter=0,1 |
| L1D_CACHE_ST.M_STATE | L1 data cache stores in M state | EventSel=41H UMask=08H Counter=0,1 |
| L1D_CACHE_ST.S_STATE | L1 data cache stores in S state | EventSel=41H UMask=02H Counter=0,1 |
| L1D_PREFETCH.MISS | L1D hardware prefetch misses | EventSel=4EH UMask=02H Counter=0,1 |
| L1D_PREFETCH.REQUESTS | L1D hardware prefetch requests | EventSel=4EH UMask=01H Counter=0,1 |
| L1D_PREFETCH.TRIGGERS | L1D hardware prefetch requests triggered | EventSel=4EH UMask=04H Counter=0,1 |
| L1D_WB_L2.E_STATE | L1 writebacks to L2 in E state | EventSel=28H UMask=04H Counter=0,1,2,3 |
| L1D_WB_L2.I_STATE | L1 writebacks to L2 in I state (misses) | EventSel=28H UMask=01H Counter=0,1,2,3 |
| L1D_WB_L2.M_STATE | L1 writebacks to L2 in M state | EventSel=28H UMask=08H Counter=0,1,2,3 |
| L1D_WB_L2.MESI | All L1 writebacks to L2 | EventSel=28H UMask=0FH Counter=0,1,2,3 |
| L1D_WB_L2.S_STATE | L1 writebacks to L2 in S state | EventSel=28H UMask=02H Counter=0,1,2,3 |
| L1I.CYCLES_STALLED | L1I instruction fetch stall cycles | EventSel=80H UMask=04H Counter=0,1,2,3 |
| L1I.HITS | L1I instruction fetch hits | EventSel=80H UMask=01H Counter=0,1,2,3 |
| L1I.MISSES | L1I instruction fetch misses | EventSel=80H UMask=02H Counter=0,1,2,3 |
| L1I.READS | L1I Instruction fetches | EventSel=80H UMask=03H Counter=0,1,2,3 |
| L2_DATA_RQSTS.ANY | All L2 data requests | EventSel=26H UMask=FFH Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.E_STATE | L2 data demand loads in E state | EventSel=26H UMask=04H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.I_STATE | L2 data demand loads in I state (misses) | EventSel=26H UMask=01H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.M_STATE | L2 data demand loads in M state | EventSel=26H UMask=08H Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.MESI | L2 data demand requests | EventSel=26H UMask=0FH Counter=0,1,2,3 |
| L2_DATA_RQSTS.DEMAND.S_STATE | L2 data demand loads in S state | EventSel=26H UMask=02H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.E_STATE | L2 data prefetches in E state | EventSel=26H UMask=40H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.I_STATE | L2 data prefetches in the I state (misses) | EventSel=26H UMask=10H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.M_STATE | L2 data prefetches in M state | EventSel=26H UMask=80H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.MESI | All L2 data prefetches | EventSel=26H UMask=F0H Counter=0,1,2,3 |
| L2_DATA_RQSTS.PREFETCH.S_STATE | L2 data prefetches in the S state | EventSel=26H UMask=20H Counter=0,1,2,3 |
| L2_LINES_IN.ANY | L2 lines allocated | EventSel=F1H UMask=07H Counter=0,1,2,3 |
| L2_LINES_IN.E_STATE | L2 lines allocated in the E state | EventSel=F1H UMask=04H Counter=0,1,2,3 |
| L2_LINES_IN.S_STATE | L2 lines allocated in the S state | EventSel=F1H UMask=02H Counter=0,1,2,3 |
| L2_LINES_OUT.ANY | L2 lines evicted | EventSel=F2H UMask=0FH Counter=0,1,2,3 |
| L2_LINES_OUT.DEMAND_CLEAN | L2 lines evicted by a demand request | EventSel=F2H UMask=01H Counter=0,1,2,3 |
| L2_LINES_OUT.DEMAND_DIRTY | L2 modified lines evicted by a demand request | EventSel=F2H UMask=02H Counter=0,1,2,3 |
| L2_LINES_OUT.PREFETCH_CLEAN | L2 lines evicted by a prefetch request | EventSel=F2H UMask=04H Counter=0,1,2,3 |
| L2_LINES_OUT.PREFETCH_DIRTY | L2 modified lines evicted by a prefetch request | EventSel=F2H UMask=08H Counter=0,1,2,3 |
| L2_RQSTS.IFETCH_HIT | L2 instruction fetch hits | EventSel=24H UMask=10H Counter=0,1,2,3 |
| L2_RQSTS.IFETCH_MISS | L2 instruction fetch misses | EventSel=24H UMask=20H Counter=0,1,2,3 |
| L2_RQSTS.IFETCHES | L2 instruction fetches | EventSel=24H UMask=30H Counter=0,1,2,3 |
| L2_RQSTS.LD_HIT | L2 load hits | EventSel=24H UMask=01H Counter=0,1,2,3 |
| L2_RQSTS.LD_MISS | L2 load misses | EventSel=24H UMask=02H Counter=0,1,2,3 |
| L2_RQSTS.LOADS | L2 requests | EventSel=24H UMask=03H Counter=0,1,2,3 |
| L2_RQSTS.MISS | All L2 misses | EventSel=24H UMask=AAH Counter=0,1,2,3 |
| L2_RQSTS.PREFETCH_HIT | L2 prefetch hits | EventSel=24H UMask=40H Counter=0,1,2,3 |
| L2_RQSTS.PREFETCH_MISS | L2 prefetch misses | EventSel=24H UMask=80H Counter=0,1,2,3 |
| L2_RQSTS.PREFETCHES | All L2 prefetches | EventSel=24H UMask=C0H Counter=0,1,2,3 |
| L2_RQSTS.REFERENCES | All L2 requests | EventSel=24H UMask=FFH Counter=0,1,2,3 |
| L2_RQSTS.RFO_HIT | L2 RFO hits | EventSel=24H UMask=04H Counter=0,1,2,3 |
| L2_RQSTS.RFO_MISS | L2 RFO misses | EventSel=24H UMask=08H Counter=0,1,2,3 |
| L2_RQSTS.RFOS | L2 RFO requests | EventSel=24H UMask=0CH Counter=0,1,2,3 |
| L2_TRANSACTIONS.ANY | All L2 transactions | EventSel=F0H UMask=80H Counter=0,1,2,3 |
| L2_TRANSACTIONS.FILL | L2 fill transactions | EventSel=F0H UMask=20H Counter=0,1,2,3 |
| L2_TRANSACTIONS.IFETCH | L2 instruction fetch transactions | EventSel=F0H UMask=04H Counter=0,1,2,3 |
| L2_TRANSACTIONS.L1D_WB | L1D writeback to L2 transactions | EventSel=F0H UMask=10H Counter=0,1,2,3 |
| L2_TRANSACTIONS.LOAD | L2 Load transactions | EventSel=F0H UMask=01H Counter=0,1,2,3 |
| L2_TRANSACTIONS.PREFETCH | L2 prefetch transactions | EventSel=F0H UMask=08H Counter=0,1,2,3 |
| L2_TRANSACTIONS.RFO | L2 RFO transactions | EventSel=F0H UMask=02H Counter=0,1,2,3 |
| L2_TRANSACTIONS.WB | L2 writeback to LLC transactions | EventSel=F0H UMask=40H Counter=0,1,2,3 |
| L2_WRITE.LOCK.E_STATE | L2 demand lock RFOs in E state | EventSel=27H UMask=40H Counter=0,1,2,3 |
| L2_WRITE.LOCK.HIT | All demand L2 lock RFOs that hit the cache | EventSel=27H UMask=E0H Counter=0,1,2,3 |
| L2_WRITE.LOCK.I_STATE | L2 demand lock RFOs in I state (misses) | EventSel=27H UMask=10H Counter=0,1,2,3 |
| L2_WRITE.LOCK.M_STATE | L2 demand lock RFOs in M state | EventSel=27H UMask=80H Counter=0,1,2,3 |
| L2_WRITE.LOCK.MESI | All demand L2 lock RFOs | EventSel=27H UMask=F0H Counter=0,1,2,3 |
| L2_WRITE.LOCK.S_STATE | L2 demand lock RFOs in S state | EventSel=27H UMask=20H Counter=0,1,2,3 |
| L2_WRITE.RFO.HIT | All L2 demand store RFOs that hit the cache | EventSel=27H UMask=0EH Counter=0,1,2,3 |
| L2_WRITE.RFO.I_STATE | L2 demand store RFOs in I state (misses) | EventSel=27H UMask=01H Counter=0,1,2,3 |
| L2_WRITE.RFO.M_STATE | L2 demand store RFOs in M state | EventSel=27H UMask=08H Counter=0,1,2,3 |
| L2_WRITE.RFO.MESI | All L2 demand store RFOs | EventSel=27H UMask=0FH Counter=0,1,2,3 |
| L2_WRITE.RFO.S_STATE | L2 demand store RFOs in S state | EventSel=27H UMask=02H Counter=0,1,2,3 |
| LARGE_ITLB.HIT | Large ITLB hit | EventSel=82H UMask=01H Counter=0,1,2,3 |
| LOAD_DISPATCH.ANY | All loads dispatched | EventSel=13H UMask=07H Counter=0,1,2,3 |
| LOAD_DISPATCH.MOB | Loads dispatched from the MOB | EventSel=13H UMask=04H Counter=0,1,2,3 |
| LOAD_DISPATCH.RS | Loads dispatched that bypass the MOB | EventSel=13H UMask=01H Counter=0,1,2,3 |
| LOAD_DISPATCH.RS_DELAYED | Loads dispatched from stage 305 | EventSel=13H UMask=02H Counter=0,1,2,3 |
| LOAD_HIT_PRE | Load operations conflicting with software prefetches | EventSel=4CH UMask=01H Counter=0,1 |
| LSD.ACTIVE | Cycles when uops were delivered by the LSD | EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3 |
| LSD.INACTIVE | Cycles no uops were delivered by the LSD | EventSel=A8H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| LSD_OVERFLOW | Loops that can't stream from the instruction queue | EventSel=20H UMask=01H Counter=0,1,2,3 |
| MACHINE_CLEARS.CYCLES | Cycles machine clear asserted | EventSel=C3H UMask=01H Counter=0,1,2,3 |
| MACHINE_CLEARS.MEM_ORDER | Execution pipeline restart due to Memory ordering conflicts | EventSel=C3H UMask=02H Counter=0,1,2,3 |
| MACHINE_CLEARS.SMC | Self-Modifying Code detected | EventSel=C3H UMask=04H Counter=0,1,2,3 |
| MACRO_INSTS.DECODED | Instructions decoded | EventSel=D0H UMask=01H Counter=0,1,2,3 |
| MACRO_INSTS.FUSIONS_DECODED | Macro-fused instructions decoded | EventSel=A6H UMask=01H Counter=0,1,2,3 |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0 | Memory instructions retired above 0 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=00H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024 | Memory instructions retired above 1024 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=400H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128 | Memory instructions retired above 128 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16 | Memory instructions retired above 16 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384 | Memory instructions retired above 16384 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=4000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048 | Memory instructions retired above 2048 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=800H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256 | Memory instructions retired above 256 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32 | Memory instructions retired above 32 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768 | Memory instructions retired above 32768 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=8000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4 | Memory instructions retired above 4 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096 | Memory instructions retired above 4096 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=1000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512 | Memory instructions retired above 512 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64 | Memory instructions retired above 64 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8 | Memory instructions retired above 8 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192 | Memory instructions retired above 8192 clocks (Precise Event) | EventSel=0BH UMask=10H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=2000H Counter=3 PEBS:[Precise, Latency] |
| MEM_INST_RETIRED.LOADS | Instructions retired which contains a load (Precise Event) | EventSel=0BH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.LOADS_PS | Instructions retired which contains a load (Precise Event) | EventSel=0BH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.STORES | Instructions retired which contains a store (Precise Event) | EventSel=0BH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_INST_RETIRED.STORES_PS | Instructions retired which contains a store (Precise Event) | EventSel=0BH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.DTLB_MISS | Retired loads that miss the DTLB (Precise Event) | EventSel=CBH UMask=80H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.DTLB_MISS_PS | Retired loads that miss the DTLB (Precise Event) | EventSel=CBH UMask=80H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.HIT_LFB | Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) | EventSel=CBH UMask=40H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.HIT_LFB_PS | Retired loads that miss L1D and hit an previously allocated LFB (Precise Event) | EventSel=CBH UMask=40H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L1D_HIT | Retired loads that hit the L1 data cache (Precise Event) | EventSel=CBH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L1D_HIT_PS | Retired loads that hit the L1 data cache (Precise Event) | EventSel=CBH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L2_HIT | Retired loads that hit the L2 cache (Precise Event) | EventSel=CBH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.L2_HIT_PS | Retired loads that hit the L2 cache (Precise Event) | EventSel=CBH UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_MISS | Retired loads that miss the LLC cache (Precise Event) | EventSel=CBH UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_MISS_PS | Retired loads that miss the LLC cache (Precise Event) | EventSel=CBH UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_UNSHARED_HIT | Retired loads that hit valid versions in the LLC cache (Precise Event) | EventSel=CBH UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.LLC_UNSHARED_HIT_PS | Retired loads that hit valid versions in the LLC cache (Precise Event) | EventSel=CBH UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM | Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) | EventSel=CBH UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM_PS | Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event) | EventSel=CBH UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_STORE_RETIRED.DTLB_MISS | Retired stores that miss the DTLB (Precise Event) | EventSel=0CH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_STORE_RETIRED.DTLB_MISS_PS | Retired stores that miss the DTLB (Precise Event) | EventSel=0CH UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| OFFCORE_REQUESTS.L1D_WRITEBACK | Offcore L1 data cache writebacks | EventSel=B0H UMask=40H Counter=0,1,2,3 |
| OFFCORE_REQUESTS_SQ_FULL | Offcore requests blocked due to Super Queue full | EventSel=B2H UMask=01H Counter=0,1,2,3 |
| PARTIAL_ADDRESS_ALIAS | False dependencies due to partial address aliasing | EventSel=07H UMask=01H Counter=0,1,2,3 |
| RAT_STALLS.ANY | All RAT stall cycles | EventSel=D2H UMask=0FH Counter=0,1,2,3 |
| RAT_STALLS.FLAGS | Flag stall cycles | EventSel=D2H UMask=01H Counter=0,1,2,3 |
| RAT_STALLS.REGISTERS | Partial register stall cycles | EventSel=D2H UMask=02H Counter=0,1,2,3 |
| RAT_STALLS.ROB_READ_PORT | ROB read port stalls cycles | EventSel=D2H UMask=04H Counter=0,1,2,3 |
| RAT_STALLS.SCOREBOARD | Scoreboard stall cycles | EventSel=D2H UMask=08H Counter=0,1,2,3 |
| RESOURCE_STALLS.ANY | Resource related stall cycles | EventSel=A2H UMask=01H Counter=0,1,2,3 |
| RESOURCE_STALLS.FPCW | FPU control word write stall cycles | EventSel=A2H UMask=20H Counter=0,1,2,3 |
| RESOURCE_STALLS.LOAD | Load buffer stall cycles | EventSel=A2H UMask=02H Counter=0,1,2,3 |
| RESOURCE_STALLS.MXCSR | MXCSR rename stall cycles | EventSel=A2H UMask=40H Counter=0,1,2,3 |
| RESOURCE_STALLS.OTHER | Other Resource related stall cycles | EventSel=A2H UMask=80H Counter=0,1,2,3 |
| RESOURCE_STALLS.ROB_FULL | ROB full stall cycles | EventSel=A2H UMask=10H Counter=0,1,2,3 |
| RESOURCE_STALLS.RS_FULL | Reservation Station full stall cycles | EventSel=A2H UMask=04H Counter=0,1,2,3 |
| RESOURCE_STALLS.STORE | Store buffer stall cycles | EventSel=A2H UMask=08H Counter=0,1,2,3 |
| SB_DRAIN.ANY | All Store buffer stall cycles | EventSel=04H UMask=07H Counter=0,1,2,3 |
| SEG_RENAME_STALLS | Segment rename stall cycles | EventSel=D4H UMask=01H Counter=0,1,2,3 |
| SIMD_INT_128.PACK | 128 bit SIMD integer pack operations | EventSel=12H UMask=04H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_ARITH | 128 bit SIMD integer arithmetic operations | EventSel=12H UMask=20H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_LOGICAL | 128 bit SIMD integer logical operations | EventSel=12H UMask=10H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_MPY | 128 bit SIMD integer multiply operations | EventSel=12H UMask=01H Counter=0,1,2,3 |
| SIMD_INT_128.PACKED_SHIFT | 128 bit SIMD integer shift operations | EventSel=12H UMask=02H Counter=0,1,2,3 |
| SIMD_INT_128.SHUFFLE_MOVE | 128 bit SIMD integer shuffle/move operations | EventSel=12H UMask=40H Counter=0,1,2,3 |
| SIMD_INT_128.UNPACK | 128 bit SIMD integer unpack operations | EventSel=12H UMask=08H Counter=0,1,2,3 |
| SIMD_INT_64.PACK | SIMD integer 64 bit pack operations | EventSel=FDH UMask=04H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_ARITH | SIMD integer 64 bit arithmetic operations | EventSel=FDH UMask=20H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_LOGICAL | SIMD integer 64 bit logical operations | EventSel=FDH UMask=10H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_MPY | SIMD integer 64 bit packed multiply operations | EventSel=FDH UMask=01H Counter=0,1,2,3 |
| SIMD_INT_64.PACKED_SHIFT | SIMD integer 64 bit shift operations | EventSel=FDH UMask=02H Counter=0,1,2,3 |
| SIMD_INT_64.SHUFFLE_MOVE | SIMD integer 64 bit shuffle/move operations | EventSel=FDH UMask=40H Counter=0,1,2,3 |
| SIMD_INT_64.UNPACK | SIMD integer 64 bit unpack operations | EventSel=FDH UMask=08H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HIT | Thread responded HIT to snoop | EventSel=B8H UMask=01H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HITE | Thread responded HITE to snoop | EventSel=B8H UMask=02H Counter=0,1,2,3 |
| SNOOP_RESPONSE.HITM | Thread responded HITM to snoop | EventSel=B8H UMask=04H Counter=0,1,2,3 |
| SQ_FULL_STALL_CYCLES | Super Queue full stall cycles | EventSel=F6H UMask=01H Counter=0,1,2,3 |
| SQ_MISC.SPLIT_LOCK | Super Queue lock splits across a cache line | EventSel=F4H UMask=10H Counter=0,1,2,3 |
| SSEX_UOPS_RETIRED.PACKED_DOUBLE | SIMD Packed-Double Uops retired (Precise Event) | EventSel=C7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_DOUBLE_PS | SIMD Packed-Double Uops retired (Precise Event) | EventSel=C7H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_SINGLE | SIMD Packed-Single Uops retired (Precise Event) | EventSel=C7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.PACKED_SINGLE_PS | SIMD Packed-Single Uops retired (Precise Event) | EventSel=C7H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_DOUBLE | SIMD Scalar-Double Uops retired (Precise Event) | EventSel=C7H UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_DOUBLE_PS | SIMD Scalar-Double Uops retired (Precise Event) | EventSel=C7H UMask=08H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_SINGLE | SIMD Scalar-Single Uops retired (Precise Event) | EventSel=C7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.SCALAR_SINGLE_PS | SIMD Scalar-Single Uops retired (Precise Event) | EventSel=C7H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.VECTOR_INTEGER | SIMD Vector Integer Uops retired (Precise Event) | EventSel=C7H UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| SSEX_UOPS_RETIRED.VECTOR_INTEGER_PS | SIMD Vector Integer Uops retired (Precise Event) | EventSel=C7H UMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| STORE_BLOCKS.AT_RET | Loads delayed with at-Retirement block code | EventSel=06H UMask=04H Counter=0,1,2,3 |
| STORE_BLOCKS.L1D_BLOCK | Cacheable loads delayed with L1D block code | EventSel=06H UMask=08H Counter=0,1,2,3 |
| TWO_UOP_INSTS_DECODED | Two Uop instructions decoded | EventSel=19H UMask=01H Counter=0,1,2,3 |
| UOP_UNFUSION | Uop unfusions due to FP exceptions | EventSel=DBH UMask=01H Counter=0,1,2,3 |
| UOPS_DECODED.ESP_FOLDING | Stack pointer instructions decoded | EventSel=D1H UMask=04H Counter=0,1,2,3 |
| UOPS_DECODED.ESP_SYNC | Stack pointer sync operations | EventSel=D1H UMask=08H Counter=0,1,2,3 |
| UOPS_DECODED.MS_CYCLES_ACTIVE | Uops decoded by Microcode Sequencer | EventSel=D1H UMask=02H CMask=01H Counter=0,1,2,3 |
| UOPS_DECODED.STALL_CYCLES | Cycles no Uops are decoded | EventSel=D1H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_ACTIVE_CYCLES | Cycles Uops executed on any port (core count) | EventSel=B1H UMask=3FH AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5 | Cycles Uops executed on ports 0-4 (core count) | EventSel=B1H UMask=1FH AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_COUNT | Uops executed on any port (core count) | EventSel=B1H UMask=3FH EdgeDetect=1 AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_COUNT_NO_PORT5 | Uops executed on ports 0-4 (core count) | EventSel=B1H UMask=1FH EdgeDetect=1 AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_CYCLES | Cycles no Uops issued on any port (core count) | EventSel=B1H UMask=3FH AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5 | Cycles no Uops issued on ports 0-4 (core count) | EventSel=B1H UMask=1FH AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT0 | Uops executed on port 0 | EventSel=B1H UMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT015 | Uops issued on ports 0, 1 or 5 | EventSel=B1H UMask=40H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT015_STALL_CYCLES | Cycles no Uops issued on ports 0, 1 or 5 | EventSel=B1H UMask=40H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT1 | Uops executed on port 1 | EventSel=B1H UMask=02H Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT2_CORE | Uops executed on port 2 (core count) | EventSel=B1H UMask=04H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT234_CORE | Uops issued on ports 2, 3 or 4 | EventSel=B1H UMask=80H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT3_CORE | Uops executed on port 3 (core count) | EventSel=B1H UMask=08H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT4_CORE | Uops executed on port 4 (core count) | EventSel=B1H UMask=10H AnyThread=1 Counter=0,1,2,3 |
| UOPS_EXECUTED.PORT5 | Uops executed on port 5 | EventSel=B1H UMask=20H Counter=0,1,2,3 |
| UOPS_ISSUED.ANY | Uops issued | EventSel=0EH UMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.CORE_STALL_CYCLES | Cycles no Uops were issued on any thread | EventSel=0EH UMask=01H AnyThread=1 Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.CYCLES_ALL_THREADS | Cycles Uops were issued on either thread | EventSel=0EH UMask=01H AnyThread=1 CMask=01H Counter=0,1,2,3 |
| UOPS_ISSUED.FUSED | Fused Uops issued | EventSel=0EH UMask=02H Counter=0,1,2,3 |
| UOPS_ISSUED.STALL_CYCLES | Cycles no Uops were issued | EventSel=0EH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 |
| UOPS_RETIRED.ACTIVE_CYCLES | Cycles Uops are being retired | EventSel=C2H UMask=01H CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ACTIVE_CYCLES_PS | Cycles Uops are being retired | EventSel=C2H UMask=01H CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ANY | Uops retired (Precise Event) | EventSel=C2H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ANY_PS | Uops retired (Precise Event) | EventSel=C2H UMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.MACRO_FUSED | Macro-fused Uops retired (Precise Event) | EventSel=C2H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.MACRO_FUSED_PS | Macro-fused Uops retired (Precise Event) | EventSel=C2H UMask=04H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS | Retirement slots used (Precise Event) | EventSel=C2H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS_PS | Retirement slots used (Precise Event) | EventSel=C2H UMask=02H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES | Cycles Uops are not retiring (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES_PS | Cycles Uops are not retiring (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES | Total cycles using precise uop retired event (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES_PS | Total cycles using precise uop retired event (Precise Event) | EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 PEBS:[PreciseEventingIP] |
| UNCORE | ||
| UNC_M_ADDR_MATCH0 | UNC_M_ADDR_MATCH0 | EventSel=01H UMask=3CH Counter=0,1,2,3,4,5 |
| UNC_M_AUTO_CLS | UNC_M_AUTO_CLS | EventSel=01H UMask=2AH Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.F2B_BCMD | UNC_M_B_CMD.F2B_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.F2V_BCMD | UNC_M_B_CMD.F2V_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.MRG_BCMD | UNC_M_B_CMD.MRG_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.RD_BCMD | UNC_M_B_CMD.RD_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.SPRWR_BCMD | UNC_M_B_CMD.SPRWR_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.V2F_BCMD | UNC_M_B_CMD.V2F_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.V2V_BCMD | UNC_M_B_CMD.V2V_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_B_CMD.WR_BCMD | UNC_M_B_CMD.WR_BCMD | EventSel=01H UMask=34H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_RD_SCMD | UNC_M_DRAM_CMD.CAS_RD_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_RD_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CAS_RD_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_RD_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CAS_RD_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_RD_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CAS_RD_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_RD_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CAS_RD_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_WR_SCMD | UNC_M_DRAM_CMD.CAS_WR_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_WR_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CAS_WR_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_WR_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CAS_WR_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_WR_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CAS_WR_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CAS_WR_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CAS_WR_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_RD_SCMD | UNC_M_DRAM_CMD.CASPRE_RD_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_RD_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CASPRE_RD_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_RD_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CASPRE_RD_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_RD_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CASPRE_RD_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_RD_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CASPRE_RD_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_WR_SCMD | UNC_M_DRAM_CMD.CASPRE_WR_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_WR_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CASPRE_WR_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_WR_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CASPRE_WR_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_WR_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CASPRE_WR_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CASPRE_WR_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CASPRE_WR_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEH_SCMD | UNC_M_DRAM_CMD.CKEH_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEH_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CKEH_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEH_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CKEH_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEH_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CKEH_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEH_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CKEH_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEL_SCMD | UNC_M_DRAM_CMD.CKEL_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEL_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.CKEL_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEL_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.CKEL_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEL_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.CKEL_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.CKEL_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.CKEL_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS_SCMD | UNC_M_DRAM_CMD.EMRS_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.EMRS_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.EMRS_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.EMRS_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.EMRS_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS2_SCMD | UNC_M_DRAM_CMD.EMRS2_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS2_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.EMRS2_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS2_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.EMRS2_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS2_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.EMRS2_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS2_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.EMRS2_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS3_SCMD | UNC_M_DRAM_CMD.EMRS3_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS3_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.EMRS3_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS3_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.EMRS3_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS3_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.EMRS3_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EMRS3_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.EMRS3_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.ENSR_SCMD | UNC_M_DRAM_CMD.ENSR_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.ENSR_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.ENSR_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.ENSR_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.ENSR_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.ENSR_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.ENSR_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.ENSR_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.ENSR_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EXSR_SCMD | UNC_M_DRAM_CMD.EXSR_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EXSR_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.EXSR_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EXSR_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.EXSR_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EXSR_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.EXSR_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.EXSR_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.EXSR_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.GENDRM_SCMD | UNC_M_DRAM_CMD.GENDRM_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.GENDRM_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.GENDRM_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.GENDRM_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.GENDRM_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.GENDRM_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.GENDRM_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.GENDRM_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.GENDRM_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.IBD_SCMD | UNC_M_DRAM_CMD.IBD_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.IBD_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.IBD_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.IBD_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.IBD_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.IBD_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.IBD_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.IBD_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.IBD_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.MRS_SCMD | UNC_M_DRAM_CMD.MRS_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.MRS_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.MRS_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.MRS_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.MRS_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.MRS_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.MRS_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.MRS_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.MRS_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOP_SCMD | UNC_M_DRAM_CMD.NOP_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOP_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.NOP_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOP_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.NOP_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOP_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.NOP_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOP_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.NOP_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOWPE_SCMD | UNC_M_DRAM_CMD.NOWPE_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOWPE_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.NOWPE_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOWPE_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.NOWPE_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOWPE_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.NOWPE_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.NOWPE_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.NOWPE_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.POLL_SCMD | UNC_M_DRAM_CMD.POLL_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.POLL_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.POLL_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.POLL_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.POLL_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.POLL_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.POLL_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.POLL_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.POLL_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PRE_SCMD | UNC_M_DRAM_CMD.PRE_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PRE_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.PRE_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PRE_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.PRE_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PRE_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.PRE_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PRE_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.PRE_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PREALL_SCMD | UNC_M_DRAM_CMD.PREALL_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PREALL_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.PREALL_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PREALL_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.PREALL_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PREALL_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.PREALL_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.PREALL_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.PREALL_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RAS_SCMD | UNC_M_DRAM_CMD.RAS_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RAS_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.RAS_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RAS_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.RAS_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RAS_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.RAS_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RAS_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.RAS_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RFR_SCMD | UNC_M_DRAM_CMD.RFR_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RFR_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.RFR_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RFR_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.RFR_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RFR_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.RFR_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.RFR_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.RFR_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SFT_RST_SCMD | UNC_M_DRAM_CMD.SFT_RST_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SFT_RST_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.SFT_RST_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SFT_RST_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.SFT_RST_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SFT_RST_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.SFT_RST_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SFT_RST_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.SFT_RST_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SYNC_SCMD | UNC_M_DRAM_CMD.SYNC_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SYNC_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.SYNC_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SYNC_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.SYNC_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SYNC_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.SYNC_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.SYNC_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.SYNC_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.TRKL_SCMD | UNC_M_DRAM_CMD.TRKL_SCMD | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.TRKL_SCMD.ADAPTIVEMODE | UNC_M_DRAM_CMD.TRKL_SCMD.ADAPTIVEMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.TRKL_SCMD.READMAJORMODE | UNC_M_DRAM_CMD.TRKL_SCMD.READMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.TRKL_SCMD.TRADEOFFMODE | UNC_M_DRAM_CMD.TRKL_SCMD.TRADEOFFMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DRAM_CMD.TRKL_SCMD.WRITEMAJORMODE | UNC_M_DRAM_CMD.TRKL_SCMD.WRITEMAJORMODE | EventSel=01H UMask=14H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FILL.RDQ_EMPTY | UNC_M_DSP_FILL.RDQ_EMPTY | EventSel=01H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FILL.RDQ_FULL | UNC_M_DSP_FILL.RDQ_FULL | EventSel=01H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FILL.WRQ_EMPTY | UNC_M_DSP_FILL.WRQ_EMPTY | EventSel=01H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FILL.WRQ_FULL | UNC_M_DSP_FILL.WRQ_FULL | EventSel=01H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FULL_CNT_EN.RDQ_EMPTY | UNC_M_DSP_FULL_CNT_EN.RDQ_EMPTY | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FULL_CNT_EN.RDQ_FULL | UNC_M_DSP_FULL_CNT_EN.RDQ_FULL | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FULL_CNT_EN.WRQ_EMPTY | UNC_M_DSP_FULL_CNT_EN.WRQ_EMPTY | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_DSP_FULL_CNT_EN.WRQ_FULL | UNC_M_DSP_FULL_CNT_EN.WRQ_FULL | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.1CMD | UNC_M_FRM_TYPE.1CMD | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.3CMD | UNC_M_FRM_TYPE.3CMD | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.CHNL | UNC_M_FRM_TYPE.CHNL | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.NOP | UNC_M_FRM_TYPE.NOP | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.SYNC | UNC_M_FRM_TYPE.SYNC | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FRM_TYPE.WDAT | UNC_M_FRM_TYPE.WDAT | EventSel=01H UMask=12H Counter=0,1,2,3,4,5 |
| UNC_M_FVC_EVNT1 | UNC_M_FVC_EVNT1 | EventSel=01H UMask=1AH Counter=0,1,2,3,4,5 |
| UNC_M_FVC_EVNT2 | UNC_M_FVC_EVNT2 | EventSel=01H UMask=1CH Counter=0,1,2,3,4,5 |
| UNC_M_FVC_EVNT3 | UNC_M_FVC_EVNT3 | EventSel=01H UMask=1EH Counter=0,1,2,3,4,5 |
| UNC_M_FVC_EVNT4 | UNC_M_FVC_EVNT4 | EventSel=01H UMask=20H Counter=0,1,2,3,4,5 |
| UNC_M_FVID_RACE | UNC_M_FVID_RACE | EventSel=01H UMask=30H Counter=0,1,2,3,4,5 |
| UNC_M_ISS_SCHED | UNC_M_ISS_SCHED | EventSel=01H UMask=10H Counter=0,1,2,3,4,5 |
| UNC_M_LATENCY_CNT_EN | UNC_M_LATENCY_CNT_EN | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_MA_PAR_ERR | UNC_M_MA_PAR_ERR | EventSel=01H UMask=18H Counter=0,1,2,3,4,5 |
| UNC_M_MULTICAS | UNC_M_MULTICAS | EventSel=01H UMask=2EH Counter=0,1,2,3,4,5 |
| UNC_M_OPN2CLS.CLS2OPN | UNC_M_OPN2CLS.CLS2OPN | EventSel=01H UMask=2CH Counter=0,1,2,3,4,5 |
| UNC_M_OPN2CLS.OPN2CLS | UNC_M_OPN2CLS.OPN2CLS | EventSel=01H UMask=2CH Counter=0,1,2,3,4,5 |
| UNC_M_OPNCLS_CNT_EN.CLOSED | UNC_M_OPNCLS_CNT_EN.CLOSED | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_OPNCLS_CNT_EN.OPEN | UNC_M_OPNCLS_CNT_EN.OPEN | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_PAGE_EMPTY | UNC_M_PAGE_EMPTY | EventSel=01H UMask=2AH Counter=0,1,2,3,4,5 |
| UNC_M_PAGE_HIT | UNC_M_PAGE_HIT | EventSel=01H UMask=28H Counter=0,1,2,3,4,5 |
| UNC_M_PAGE_MISS | UNC_M_PAGE_MISS | EventSel=01H UMask=26H Counter=0,1,2,3,4,5 |
| UNC_M_PATROL_TXNS | UNC_M_PATROL_TXNS | EventSel=01H UMask=22H Counter=0,1,2,3,4,5 |
| UNC_M_REFRESH | UNC_M_REFRESH | EventSel=01H UMask=0CH Counter=0,1,2,3,4,5 |
| UNC_M_REFRESH_CONFLICT | UNC_M_REFRESH_CONFLICT | EventSel=01H UMask=0EH Counter=0,1,2,3,4,5 |
| UNC_M_RETRY | UNC_M_RETRY | EventSel=01H UMask=16H Counter=0,1,2,3,4,5 |
| UNC_M_RETRY.FVID | UNC_M_RETRY.FVID | EventSel=01H UMask=16H Counter=0,1,2,3,4,5 |
| UNC_M_SCHED_INFLIGHT_CMD | UNC_M_SCHED_INFLIGHT_CMD | EventSel=01H UMask=38H Counter=0,1,2,3,4,5 |
| UNC_M_SCHED_MODE_CNT_EN.ADAPTIVE | UNC_M_SCHED_MODE_CNT_EN.ADAPTIVE | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_SCHED_MODE_CNT_EN.READ_MAJOR | UNC_M_SCHED_MODE_CNT_EN.READ_MAJOR | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_SCHED_MODE_CNT_EN.TRADEOFF | UNC_M_SCHED_MODE_CNT_EN.TRADEOFF | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_SCHED_MODE_CNT_EN.WRITE_MAJOR | UNC_M_SCHED_MODE_CNT_EN.WRITE_MAJOR | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_STARVED_CNT_EN | UNC_M_STARVED_CNT_EN | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_STARVED_RETRY | UNC_M_STARVED_RETRY | EventSel=01H UMask=06H Counter=0,1,2,3,4,5 |
| UNC_M_TIME_STAMP_TICK | UNC_M_TIME_STAMP_TICK | EventSel=01H UMask=36H Counter=0,1,2,3,4,5 |
| UNC_M_TRANS_CMD | UNC_M_TRANS_CMD | EventSel=01H UMask=24H Counter=0,1,2,3,4,5 |
| UNC_M_TT_CMD | UNC_M_TT_CMD | EventSel=01H UMask=32H Counter=0,1,2,3,4,5 |
| UNC_M_TT_CNT_EN | UNC_M_TT_CNT_EN | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_TT_TRP_DN | UNC_M_TT_TRP_DN | EventSel=01H UMask=0AH Counter=0,1,2,3,4,5 |
| UNC_M_TT_TRP_UP | UNC_M_TT_TRP_UP | EventSel=01H UMask=08H Counter=0,1,2,3,4,5 |
| UNC_M_Z_INFLIGHT_CMD | UNC_M_Z_INFLIGHT_CMD | EventSel=01H UMask=3AH Counter=0,1,2,3,4,5 |
| UNC_M_ZERO | UNC_M_ZERO | EventSel=01H UMask=3EH Counter=0,1,2,3,4,5 |
| UNC_M_ZFULL | UNC_M_ZFULL | EventSel=01H UMask=02H Counter=0,1,2,3,4,5 |
| UNC_M_ZFULL_CNT_EN | UNC_M_ZFULL_CNT_EN | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZFULL_RETRY | UNC_M_ZFULL_RETRY | EventSel=01H UMask=04H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.ALL | UNC_M_ZLATENCY_CNT_EN.ALL | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.F2B_BCMD | UNC_M_ZLATENCY_CNT_EN.F2B_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.F2V_BCMD | UNC_M_ZLATENCY_CNT_EN.F2V_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.MRG_BCMD | UNC_M_ZLATENCY_CNT_EN.MRG_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.RD_BCMD | UNC_M_ZLATENCY_CNT_EN.RD_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.SPRWR_BCMD | UNC_M_ZLATENCY_CNT_EN.SPRWR_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.V2F_BCMD | UNC_M_ZLATENCY_CNT_EN.V2F_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.V2V_BCMD | UNC_M_ZLATENCY_CNT_EN.V2V_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_M_ZLATENCY_CNT_EN.WR_BCMD | UNC_M_ZLATENCY_CNT_EN.WR_BCMD | EventSel=81H UMask=00H Counter=0,1,2,3,4,5 |
| UNC_R_FLT_SENT_EN | Counts Output port sends NULL flit | EventSel=01H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| UNC_R_INP_RCVD_VN_MSGC_SEL.ANY.DRS | ANY Data Response Messages | EventSel=01H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| UNC_R_OUT_NULL_IDLE_EN | Counts Output port sends NULL flit | EventSel=01H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| UNC_R_TARGET_AVAILABLE | Times target available at output port | EventSel=01H UMask=00H Counter=0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 |
| UNC_W_CLOCKTICKS | uncore clock frequency | EventSel=00H UMask=00H Counter=0,1,2,3 |
| OFFCORE |