| Event Name | Description | Additional Info |
|---|---|---|
| CORE | ||
| INST_RETIRED.ANY | This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions. | IA32_FIXED_CTR0 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD | This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. | IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.THREAD_ANY | Core cycles when at least one thread on the physical core is not in halt state. | IA32_FIXED_CTR1 Architectural, Fixed |
| CPU_CLK_UNHALTED.REF_TSC | This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case. | IA32_FIXED_CTR2 Architectural, Fixed |
| BR_INST_RETIRED.ALL_BRANCHES | This event counts all (macro) branch instructions retired. | EventSel=C4H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| BR_MISP_RETIRED.ALL_BRANCHES | This event counts all mispredicted macro branch instructions retired. | EventSel=C5H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_THREAD_UNHALTED.REF_XCLK | This is a fixed-frequency event programmed to general counters. It counts when the core is unhalted at 100 Mhz. | EventSel=3CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY | Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate). | EventSel=3CH UMask=01H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_UNHALTED.REF_XCLK | Reference cycles when the thread is unhalted (counts at 100 MHz rate). | EventSel=3CH UMask=01H CMask=0 Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.REF_XCLK_ANY | Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate). | EventSel=3CH UMask=01H AnyThread=1 CMask=0 Counter=0,1,2,3 Architectural |
| CPU_CLK_UNHALTED.THREAD_P | This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. | EventSel=3CH UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| CPU_CLK_UNHALTED.THREAD_P_ANY | Core cycles when at least one thread on the physical core is not in halt state. | EventSel=3CH UMask=00H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| INST_RETIRED.ANY_P | This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two). Errata: BDM61 |
EventSel=C0H UMask=00H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| LONGEST_LAT_CACHE.MISS | This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU. | EventSel=2EH UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| LONGEST_LAT_CACHE.REFERENCE | This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU. | EventSel=2EH UMask=4FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 Architectural |
| ARITH.FPU_DIV_ACTIVE | This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed. | EventSel=14H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BACLEARS.ANY | Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end. | EventSel=E6H UMask=1FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_BRANCHES | This event counts both taken and not taken speculative and retired branch instructions. | EventSel=88H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_CONDITIONAL | This event counts both taken and not taken speculative and retired macro-conditional branch instructions. | EventSel=88H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_DIRECT_JMP | This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects. | EventSel=88H UMask=C2H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_DIRECT_NEAR_CALL | This event counts both taken and not taken speculative and retired direct near calls. | EventSel=88H UMask=D0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET | This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches. | EventSel=88H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN | This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic. | EventSel=88H UMask=C8H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.NONTAKEN_CONDITIONAL | This event counts not taken macro-conditional branch instructions. | EventSel=88H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_CONDITIONAL | This event counts taken speculative and retired macro-conditional branch instructions. | EventSel=88H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_DIRECT_JUMP | This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches. | EventSel=88H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL | This event counts taken speculative and retired direct near calls. | EventSel=88H UMask=90H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET | This event counts taken speculative and retired indirect branches excluding calls and return branches. | EventSel=88H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL | This event counts taken speculative and retired indirect calls including both register and memory indirect. | EventSel=88H UMask=A0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN | This event counts taken speculative and retired indirect branches that have a return mnemonic. | EventSel=88H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_INST_RETIRED.ALL_BRANCHES_PS | This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired. Errata: BDW98 |
EventSel=C4H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL | This event counts conditional branch instructions retired. | EventSel=C4H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.CONDITIONAL_PS | This is a precise version (that is, uses PEBS) of the event that counts conditional branch instructions retired. | EventSel=C4H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.FAR_BRANCH | This event counts far branch instructions retired. Errata: BDW98 |
EventSel=C4H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL | This event counts both direct and indirect near call instructions retired. | EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_PS | This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect near call instructions retired. | EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3 | This event counts both direct and indirect macro near call instructions retired (captured in ring 3). | EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_CALL_R3_PS | This is a precise version (that is, uses PEBS) of the event that counts both direct and indirect macro near call instructions retired (captured in ring 3). | EventSel=C4H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_RETURN | This event counts return instructions retired. | EventSel=C4H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_RETURN_PS | This is a precise version (that is, uses PEBS) of the event that counts return instructions retired. | EventSel=C4H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_TAKEN | This event counts taken branch instructions retired. | EventSel=C4H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NEAR_TAKEN_PS | This is a precise version (that is, uses PEBS) of the event that counts taken branch instructions retired. | EventSel=C4H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_INST_RETIRED.NOT_TAKEN | This event counts not taken branch instructions retired. | EventSel=C4H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_EXEC.ALL_BRANCHES | This event counts both taken and not taken speculative and retired mispredicted branch instructions. | EventSel=89H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.ALL_CONDITIONAL | This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions. | EventSel=89H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET | This event counts both taken and not taken mispredicted indirect branches excluding calls and returns. | EventSel=89H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.INDIRECT | Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded). | EventSel=89H UMask=E4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.NONTAKEN_CONDITIONAL | This event counts not taken speculative and retired mispredicted macro conditional branch instructions. | EventSel=89H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_CONDITIONAL | This event counts taken speculative and retired mispredicted macro conditional branch instructions. | EventSel=89H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET | This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns. | EventSel=89H UMask=84H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL | Taken speculative and retired mispredicted indirect calls. | EventSel=89H UMask=A0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_EXEC.TAKEN_RETURN_NEAR | This event counts taken speculative and retired mispredicted indirect branches that have a return mnemonic. | EventSel=89H UMask=88H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| BR_MISP_RETIRED.ALL_BRANCHES_PS | This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired. | EventSel=C5H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL | This event counts mispredicted conditional branch instructions retired. | EventSel=C5H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.CONDITIONAL_PS | This is a precise version (that is, uses PEBS) of the event that counts mispredicted conditional branch instructions retired. | EventSel=C5H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_TAKEN | Number of near branch instructions retired that were mispredicted and taken. | EventSel=C5H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.NEAR_TAKEN_PS | Number of near branch instructions retired that were mispredicted and taken. (Precise Event - PEBS). | EventSel=C5H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.RET | This event counts mispredicted return instructions retired. | EventSel=C5H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| BR_MISP_RETIRED.RET_PS | This is a precise version (that is, uses PEBS) of the event that counts mispredicted return instructions retired. | EventSel=C5H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| CPL_CYCLES.RING0 | This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode. | EventSel=5CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPL_CYCLES.RING0_TRANS | This event counts when there is a transition from ring 1,2 or 3 to ring0. | EventSel=5CH UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPL_CYCLES.RING123 | This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3. | EventSel=5CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE | Count XClk pulses when this thread is unhalted and the other thread is halted. | EventSel=3CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE | Count XClk pulses when this thread is unhalted and the other thread is halted. | EventSel=3CH UMask=02H CMask=0 Counter=0,1,2,3 |
| CYCLE_ACTIVITY.CYCLES_L1D_MISS | Cycles while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=08H CMask=08H Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.CYCLES_L1D_PENDING | Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache. | EventSel=A3H UMask=08H CMask=08H Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.CYCLES_L2_MISS | Cycles while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.CYCLES_L2_PENDING | Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache. | EventSel=A3H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.CYCLES_LDM_PENDING | Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem). | EventSel=A3H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.CYCLES_MEM_ANY | Cycles while memory subsystem has an outstanding load. | EventSel=A3H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.CYCLES_NO_EXECUTE | Counts number of cycles nothing is executed on any execution port. | EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_L1D_MISS | Execution stalls while L1 cache miss demand load is outstanding. | EventSel=A3H UMask=0CH CMask=0CH Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.STALLS_L1D_PENDING | Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache. | EventSel=A3H UMask=0CH CMask=0CH Counter=2 CounterHTOff=2 |
| CYCLE_ACTIVITY.STALLS_L2_MISS | Execution stalls while L2 cache miss demand load is outstanding. | EventSel=A3H UMask=05H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.STALLS_L2_PENDING | Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands. | EventSel=A3H UMask=05H CMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_LDM_PENDING | Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request. | EventSel=A3H UMask=06H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| CYCLE_ACTIVITY.STALLS_MEM_ANY | Execution stalls while memory subsystem has an outstanding load. | EventSel=A3H UMask=06H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| CYCLE_ACTIVITY.STALLS_TOTAL | Total execution stalls. | EventSel=A3H UMask=04H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DSB2MITE_SWITCHES.PENALTY_CYCLES | This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs. Penalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 0–2 cycles. | EventSel=ABH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK | This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). Errata: BDM69 |
EventSel=08H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.STLB_HIT | Load operations that miss the first DTLB level but hit the second and do not cause page walks. | EventSel=08H UMask=60H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.STLB_HIT_2M | Load misses that miss the DTLB and hit the STLB (2M). | EventSel=08H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.STLB_HIT_4K | Load misses that miss the DTLB and hit the STLB (4K). | EventSel=08H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_COMPLETED | Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size. Errata: BDM69 |
EventSel=08H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_COMPLETED_1G | This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=08H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M | This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=08H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_COMPLETED_4K | This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=08H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_LOAD_MISSES.WALK_DURATION | This event counts the number of cycles while PMH is busy with the page walk. Errata: BDM69 |
EventSel=08H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.MISS_CAUSES_A_WALK | This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). Errata: BDM69 |
EventSel=49H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.STLB_HIT | Store operations that miss the first TLB level but hit the second and do not cause page walks. | EventSel=49H UMask=60H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.STLB_HIT_2M | Store misses that miss the DTLB and hit the STLB (2M). | EventSel=49H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.STLB_HIT_4K | Store misses that miss the DTLB and hit the STLB (4K). | EventSel=49H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_COMPLETED | Store misses in all DTLB levels that cause completed page walks. Errata: BDM69 |
EventSel=49H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_COMPLETED_1G | This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=49H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M | This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=49H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_COMPLETED_4K | This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=49H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| DTLB_STORE_MISSES.WALK_DURATION | This event counts the number of cycles while PMH is busy with the page walk. Errata: BDM69 |
EventSel=49H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| EPT.WALK_CYCLES | This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches. | EventSel=4FH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE | Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE | Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE | Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE | Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.4_FLOPS | Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=18H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ARITH_INST_RETIRED.DOUBLE | Number of SSE/AVX computational double precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. | EventSel=C7H UMask=15H CMask=0 Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ARITH_INST_RETIRED.PACKED | Number of SSE/AVX computational packed floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* packed double and single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. | EventSel=C7H UMask=3CH CMask=0 Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ARITH_INST_RETIRED.SCALAR | Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=03H CMask=0 Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ARITH_INST_RETIRED.SCALAR_DOUBLE | Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.SCALAR_SINGLE | Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events. | EventSel=C7H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ARITH_INST_RETIRED.SINGLE | Number of SSE/AVX computational single precision floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar and packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. | EventSel=C7H UMask=2AH CMask=0 Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ARITH_INST_RETIRED.VECTOR | Number of any Vector retired FP arithmetic instructions | EventSel=C7H UMask=FCH Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| FP_ASSIST.ANY | This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. | EventSel=CAH UMask=1EH CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| FP_ASSIST.SIMD_INPUT | This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention. | EventSel=CAH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.SIMD_OUTPUT | This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention. | EventSel=CAH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.X87_INPUT | This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid. | EventSel=CAH UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| FP_ASSIST.X87_OUTPUT | This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid. | EventSel=CAH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| HLE_RETIRED.ABORTED | Number of times HLE abort was triggered. | EventSel=C8H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| HLE_RETIRED.ABORTED_MISC1 | Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details). | EventSel=C8H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.ABORTED_MISC2 | Number of times the TSX watchdog signaled an HLE abort. | EventSel=C8H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.ABORTED_MISC3 | Number of times a disallowed operation caused an HLE abort. | EventSel=C8H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.ABORTED_MISC4 | Number of times HLE caused a fault. | EventSel=C8H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.ABORTED_MISC5 | Number of times HLE aborted and was not due to the abort conditions in subevents 3-6. | EventSel=C8H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.ABORTED_PS | Number of times HLE abort was triggered (PEBS). | EventSel=C8H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| HLE_RETIRED.COMMIT | Number of times HLE commit succeeded. | EventSel=C8H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| HLE_RETIRED.START | Number of times we entered an HLE region does not count nested transactions. | EventSel=C8H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.HIT | This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches. | EventSel=80H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.IFDATA_STALL | This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit). | EventSel=80H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ICACHE.MISSES | This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses. | EventSel=80H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_DSB_CYCLES_4_UOPS | This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=18H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_DSB_CYCLES_ANY_UOPS | This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=18H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_MITE_CYCLES_4_UOPS | This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=24H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.ALL_MITE_CYCLES_ANY_UOPS | This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=24H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.DSB_CYCLES | This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.DSB_UOPS | This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.EMPTY | This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty. | EventSel=79H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ.MITE_ALL_UOPS | This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=3CH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MITE_CYCLES | This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MITE_UOPS | This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). | EventSel=79H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_CYCLES | This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. | EventSel=79H UMask=30H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_CYCLES | This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=10H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_OCCUR | This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=10H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_DSB_UOPS | This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_MITE_UOPS | This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. | EventSel=79H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_SWITCHES | Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer. | EventSel=79H UMask=30H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ.MS_UOPS | This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. | EventSel=79H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| IDQ_UOPS_NOT_DELIVERED.CORE | This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding “4 – x” when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops. | EventSel=9CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE | This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4. | EventSel=9CH UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK | Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE. | EventSel=9CH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE | This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3. | EventSel=9CH UMask=01H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE | Cycles with less than 2 uops delivered by the front end. | EventSel=9CH UMask=01H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE | Cycles with less than 3 uops delivered by the front end. | EventSel=9CH UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| ILD_STALL.LCP | This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk. | EventSel=87H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INST_RETIRED.PREC_DIST | This is a precise version (that is, uses PEBS) of the event that counts instructions retired. Errata: BDM11, BDM55 |
EventSel=C0H UMask=01H Counter=1 CounterHTOff=1 PEBS:[Precise] |
| INST_RETIRED.X87 | This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling. | EventSel=C0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| INT_MISC.RAT_STALL_CYCLES | This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread. | EventSel=0DH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INT_MISC.RECOVERY_CYCLES | Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear. | EventSel=0DH UMask=03H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| INT_MISC.RECOVERY_CYCLES_ANY | Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke). | EventSel=0DH UMask=03H AnyThread=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB.ITLB_FLUSH | This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific). | EventSel=AEH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.MISS_CAUSES_A_WALK | This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). Errata: BDM69 |
EventSel=85H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.STLB_HIT | Operations that miss the first ITLB level but hit the second and do not cause any page walks. | EventSel=85H UMask=60H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.STLB_HIT_2M | Code misses that miss the DTLB and hit the STLB (2M). | EventSel=85H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.STLB_HIT_4K | Core misses that miss the DTLB and hit the STLB (4K). | EventSel=85H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_COMPLETED | Misses in all ITLB levels that cause completed page walks. Errata: BDM69 |
EventSel=85H UMask=0EH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_COMPLETED_1G | This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=85H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_COMPLETED_2M_4M | This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=85H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_COMPLETED_4K | This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. Errata: BDM69 |
EventSel=85H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ITLB_MISSES.WALK_DURATION | This event counts the number of cycles while PMH is busy with the page walk. Errata: BDM69 |
EventSel=85H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D.REPLACEMENT | This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace. | EventSel=51H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D_PEND_MISS.FB_FULL | Cycles a demand request was blocked due to Fill Buffers unavailability. | EventSel=48H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L1D_PEND_MISS.PENDING | This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. | EventSel=48H UMask=01H Counter=2 CounterHTOff=2 |
| L1D_PEND_MISS.PENDING_CYCLES | This event counts duration of L1D miss outstanding in cycles. | EventSel=48H UMask=01H CMask=01H Counter=2 CounterHTOff=2 |
| L1D_PEND_MISS.PENDING_CYCLES_ANY | Cycles with L1D load Misses outstanding from any thread on physical core. | EventSel=48H UMask=01H AnyThread=1 CMask=01H Counter=2 CounterHTOff=2 |
| L2_DEMAND_RQSTS.WB_HIT | This event counts the number of WB requests that hit L2 cache. | EventSel=27H UMask=50H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.ALL | This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects. | EventSel=F1H UMask=07H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.E | This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects. | EventSel=F1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.I | This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects. | EventSel=F1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_IN.S | This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects. | EventSel=F1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_LINES_OUT.DEMAND_CLEAN | Clean L2 cache lines evicted by demand. | EventSel=F2H UMask=05H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_CODE_RD | This event counts the total number of L2 code requests. | EventSel=24H UMask=E4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_DEMAND_DATA_RD | This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted. | EventSel=24H UMask=E1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_DEMAND_MISS | Demand requests that miss L2 cache. | EventSel=24H UMask=27H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_DEMAND_REFERENCES | Demand requests to L2 cache. | EventSel=24H UMask=E7H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_PF | This event counts the total number of requests from the L2 hardware prefetchers. | EventSel=24H UMask=F8H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.ALL_RFO | This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. | EventSel=24H UMask=E2H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.CODE_RD_HIT | L2 cache hits when fetching instructions, code reads. | EventSel=24H UMask=C4H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.CODE_RD_MISS | L2 cache misses when fetching instructions. | EventSel=24H UMask=24H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.DEMAND_DATA_RD_HIT | Counts the number of demand Data Read requests, initiated by load instructions, that hit L2 cache. | EventSel=24H UMask=C1H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.DEMAND_DATA_RD_MISS | This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted. | EventSel=24H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.L2_PF_HIT | This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types. | EventSel=24H UMask=D0H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.L2_PF_MISS | This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache. | EventSel=24H UMask=30H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.MISS | All requests that miss L2 cache. | EventSel=24H UMask=3FH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.REFERENCES | All L2 requests. | EventSel=24H UMask=FFH Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.RFO_HIT | RFO requests that hit L2 cache. | EventSel=24H UMask=C2H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_RQSTS.RFO_MISS | RFO requests that miss L2 cache. | EventSel=24H UMask=22H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.ALL_PF | This event counts L2 or L3 HW prefetches that access L2 cache including rejects. | EventSel=F0H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.ALL_REQUESTS | This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on. | EventSel=F0H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.CODE_RD | This event counts the number of L2 cache accesses when fetching instructions. | EventSel=F0H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.DEMAND_DATA_RD | This event counts Demand Data Read requests that access L2 cache, including rejects. | EventSel=F0H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L1D_WB | This event counts L1D writebacks that access L2 cache. | EventSel=F0H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L2_FILL | This event counts L2 fill requests that access L2 cache. | EventSel=F0H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.L2_WB | This event counts L2 writebacks that access L2 cache. | EventSel=F0H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| L2_TRANS.RFO | This event counts Read for Ownership (RFO) requests that access L2 cache. | EventSel=F0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS.NO_SR | This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use. | EventSel=03H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS.STORE_FORWARD | This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide. | EventSel=03H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LD_BLOCKS_PARTIAL.ADDRESS_ALIAS | This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased. | EventSel=07H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOAD_HIT_PRE.HW_PF | This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch. | EventSel=4CH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOAD_HIT_PRE.SW_PF | This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions. | EventSel=4CH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOCK_CYCLES.CACHE_LOCK_DURATION | This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION). | EventSel=63H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION | This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access. | EventSel=63H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.CYCLES_4_UOPS | Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. | EventSel=A8H UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.CYCLES_ACTIVE | Cycles Uops delivered by the LSD, but didn't come from the decoder. | EventSel=A8H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| LSD.UOPS | Number of Uops delivered by the LSD. | EventSel=A8H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.COUNT | Number of machine clears (nukes) of any type. | EventSel=C3H UMask=01H EdgeDetect=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.CYCLES | This event counts both thread-specific (TS) and all-thread (AT) nukes. | EventSel=C3H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.MASKMOV | Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault. | EventSel=C3H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.MEMORY_ORDERING | This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer. | EventSel=C3H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MACHINE_CLEARS.SMC | This event counts self-modifying code (SMC) detected, which causes a machine clear. | EventSel=C3H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT | This event counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache. Errata: BDM100 |
EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache. Errata: BDM100 |
EventSel=D2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM | This event counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). Errata: BDM100 |
EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). Errata: BDM100 |
EventSel=D2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS | This event counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache. Errata: BDM100 |
EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache. Errata: BDM100 |
EventSel=D2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE | This event counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required. Errata: BDM100 |
EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required. Errata: BDM100 |
EventSel=D2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM | Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI). Errata: BDE70, BDM100 |
EventSel=D3H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM_PS | This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event. Errata: BDE70, BDM100 |
EventSel=D3H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.HIT_LFB | This event counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. | EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.HIT_LFB_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. | EventSel=D1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L1_HIT | This event counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source. | EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_HIT_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source. | EventSel=D1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L1_MISS | This event counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source. | EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L1_MISS_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source. | EventSel=D1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L2_HIT | This event counts retired load uops which data sources were hits in the mid-level (L2) cache. Errata: BDM35 |
EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_HIT_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache. Errata: BDM35 |
EventSel=D1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L2_MISS | This event counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source. | EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L2_MISS_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source. | EventSel=D1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L3_HIT | This event counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required. Errata: BDM100 |
EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L3_HIT_PS | This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required. Errata: BDM100 |
EventSel=D1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_LOAD_UOPS_RETIRED.L3_MISS | Miss in last-level (L3) cache. Excludes Unknown data-source. Errata: BDM100, BDE70 |
EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_LOAD_UOPS_RETIRED.L3_MISS_PS | Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS). Errata: BDM100 |
EventSel=D1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128 | Counts randomly selected loads with latency value being above 128. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=80H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16 | Counts randomly selected loads with latency value being above 16. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=10H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256 | Counts randomly selected loads with latency value being above 256. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=100H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32 | Counts randomly selected loads with latency value being above 32. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=20H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4 | Counts randomly selected loads with latency value being above four. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=04H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512 | Counts randomly selected loads with latency value being above 512. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=200H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64 | Counts randomly selected loads with latency value being above 64. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=40H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8 | Counts randomly selected loads with latency value being above eight. Errata: BDM100, BDM35 |
EventSel=CDH UMask=01H MSR_PEBS_LD_LAT_THRESHOLD(3F6H)=08H Counter=3 CounterHTOff=3 PEBS:[Precise, DataLinearAddress, Latency] |
| MEM_UOPS_RETIRED.ALL_LOADS | Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. | EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.ALL_LOADS_PS | Counts all retired load uops. This event accounts for SW prefetch uops of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW. (Precise Event - PEBS) | EventSel=D0H UMask=81H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.ALL_STORES | Counts all retired store uops. | EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.ALL_STORES_PS | Counts all retired store uops. (Precise Event - PEBS) | EventSel=D0H UMask=82H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.LOCK_LOADS | This event counts load uops with locked access retired to the architected path. Errata: BDM35 |
EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.LOCK_LOADS_PS | This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path. Errata: BDM35 |
EventSel=D0H UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.SPLIT_LOADS | This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). | EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_LOADS_PS | This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). | EventSel=D0H UMask=41H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.SPLIT_STORES | This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). | EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.SPLIT_STORES_PS | This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). | EventSel=D0H UMask=42H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS | This event counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. | EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS | This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. | EventSel=D0H UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MEM_UOPS_RETIRED.STLB_MISS_STORES | This event counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. | EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| MEM_UOPS_RETIRED.STLB_MISS_STORES_PS | This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. | EventSel=D0H UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, DataLinearAddress] |
| MISALIGN_MEM_REF.LOADS | This event counts speculative cache-line split load uops dispatched to the L1 cache. | EventSel=05H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MISALIGN_MEM_REF.STORES | This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache. | EventSel=05H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.INT_ELIMINATED | Number of integer Move Elimination candidate uops that were eliminated. | EventSel=58H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.INT_NOT_ELIMINATED | Number of integer Move Elimination candidate uops that were not eliminated. | EventSel=58H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.SIMD_ELIMINATED | Number of SIMD Move Elimination candidate uops that were eliminated. | EventSel=58H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| MOVE_ELIMINATION.SIMD_NOT_ELIMINATED | Number of SIMD Move Elimination candidate uops that were not eliminated. | EventSel=58H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.ALL_DATA_RD | This event counts the demand and prefetch data reads. All Core Data Reads include cacheable "Demands" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type. | EventSel=B0H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.ALL_REQUESTS | This event counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, and so on. | EventSel=B0H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_CODE_RD | This event counts both cacheable and non-cacheable code read requests. | EventSel=B0H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_DATA_RD | This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. | EventSel=B0H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS.DEMAND_RFO | This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. | EventSel=B0H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_BUFFER.SQ_FULL | This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full. Note: Writeback pending FIFO has six entries. | EventSel=B2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD | This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. Errata: BDM76 |
EventSel=60H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD | This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. Errata: BDM76 |
EventSel=60H UMask=08H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD | This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). Errata: BDM76 |
EventSel=60H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO | This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Errata: BDM76 |
EventSel=60H UMask=04H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD | This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. Errata: BDM76 |
EventSel=60H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD | This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.
Note: A prefetch promoted to Demand is counted from the promotion point. Errata: BDM76 |
EventSel=60H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6 | Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue. Errata: BDM76 |
EventSel=60H UMask=01H CMask=06H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO | This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. Errata: BDM76 |
EventSel=60H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| OTHER_ASSISTS.ANY_WB_ASSIST | Number of times any microcode assist is invoked by HW upon uop writeback. | EventSel=C1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| OTHER_ASSISTS.AVX_TO_SSE | This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable. Errata: BDM30 |
EventSel=C1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| OTHER_ASSISTS.SSE_TO_AVX | This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable. Errata: BDM30 |
EventSel=C1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| PAGE_WALKER_LOADS.DTLB_L1 | Number of DTLB page walker hits in the L1+FB. Errata: BDM69, BDM98 |
EventSel=BCH UMask=11H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.DTLB_L2 | Number of DTLB page walker hits in the L2. Errata: BDM69, BDM98 |
EventSel=BCH UMask=12H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.DTLB_L3 | Number of DTLB page walker hits in the L3 + XSNP. Errata: BDM69, BDM98 |
EventSel=BCH UMask=14H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.DTLB_MEMORY | Number of DTLB page walker hits in Memory. Errata: BDM69, BDM98 |
EventSel=BCH UMask=18H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.ITLB_L1 | Number of ITLB page walker hits in the L1+FB. Errata: BDM69, BDM98 |
EventSel=BCH UMask=21H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.ITLB_L2 | Number of ITLB page walker hits in the L2. Errata: BDM69, BDM98 |
EventSel=BCH UMask=22H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| PAGE_WALKER_LOADS.ITLB_L3 | Number of ITLB page walker hits in the L3 + XSNP. Errata: BDM69, BDM98 |
EventSel=BCH UMask=24H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RESOURCE_STALLS.ANY | This event counts resource-related stall cycles. | EventSel=A2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.ROB | This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end. | EventSel=A2H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.RS | This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end. | EventSel=A2H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RESOURCE_STALLS.SB | This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end. | EventSel=A2H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| ROB_MISC_EVENTS.LBR_INSERTS | This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register. | EventSel=CCH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RS_EVENTS.EMPTY_CYCLES | This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues. | EventSel=5EH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RS_EVENTS.EMPTY_END | Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues. | EventSel=5EH UMask=01H EdgeDetect=1 Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| RTM_RETIRED.ABORTED | Number of times RTM abort was triggered . | EventSel=C9H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP, Counter=0,1,2,3] |
| RTM_RETIRED.ABORTED_MISC1 | Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details). | EventSel=C9H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.ABORTED_MISC2 | Number of times the TSX watchdog signaled an RTM abort. | EventSel=C9H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.ABORTED_MISC3 | Number of times a disallowed operation caused an RTM abort. | EventSel=C9H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.ABORTED_MISC4 | Number of times a RTM caused a fault. | EventSel=C9H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.ABORTED_MISC5 | Number of times RTM aborted and was not due to the abort conditions in subevents 3-6. | EventSel=C9H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.ABORTED_PS | Number of times RTM abort was triggered (PEBS). | EventSel=C9H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| RTM_RETIRED.COMMIT | Number of times RTM commit succeeded. | EventSel=C9H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| RTM_RETIRED.START | Number of times we entered an RTM region does not count nested transactions. | EventSel=C9H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| SQ_MISC.SPLIT_LOCK | This event counts the number of split locks in the super queue. | EventSel=F4H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TLB_FLUSH.DTLB_THREAD | This event counts the number of DTLB flush attempts of the thread-specific entries. | EventSel=BDH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TLB_FLUSH.STLB_ANY | This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on). | EventSel=BDH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_EXEC.MISC1 | Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort. | EventSel=5DH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_EXEC.MISC2 | Unfriendly TSX abort triggered by a vzeroupper instruction. | EventSel=5DH UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_EXEC.MISC3 | Unfriendly TSX abort triggered by a nest count that is too deep. | EventSel=5DH UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_EXEC.MISC4 | RTM region detected inside HLE. | EventSel=5DH UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_EXEC.MISC5 | Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region. | EventSel=5DH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_CAPACITY_WRITE | Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow. | EventSel=54H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_CONFLICT | Number of times a TSX line had a cache conflict. | EventSel=54H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH | Number of times a TSX Abort was triggered due to release/commit but data and address mismatch. | EventSel=54H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY | Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty. | EventSel=54H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT | Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer. | EventSel=54H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK | Number of times a TSX Abort was triggered due to a non-release/commit store to lock. | EventSel=54H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| TX_MEM.HLE_ELISION_BUFFER_FULL | Number of times we could not allocate Lock Buffer. | EventSel=54H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOP_DISPATCHES_CANCELLED.SIMD_PRF | This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information. | EventSel=A0H UMask=03H CMask=0 Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_DISPATCHED_PORT.PORT_0 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0. | EventSel=A1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_1 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1. | EventSel=A1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_2 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2. | EventSel=A1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_3 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3. | EventSel=A1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_4 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4. | EventSel=A1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_5 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5. | EventSel=A1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_6 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6. | EventSel=A1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_DISPATCHED_PORT.PORT_7 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7. | EventSel=A1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE | Number of uops executed from any thread. | EventSel=B1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_1 | Cycles at least 1 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_2 | Cycles at least 2 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_3 | Cycles at least 3 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_GE_4 | Cycles at least 4 micro-op is executed from any thread on physical core. | EventSel=B1H UMask=02H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CORE_CYCLES_NONE | Cycles with no micro-ops executed from any thread on physical core. | EventSel=B1H UMask=02H Invert=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC | Cycles where at least 1 uop was executed per-thread. | EventSel=B1H UMask=01H CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC | Cycles where at least 2 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC | Cycles where at least 3 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=03H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC | Cycles where at least 4 uops were executed per-thread. | EventSel=B1H UMask=01H CMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.STALL_CYCLES | This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. | EventSel=B1H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_EXECUTED.THREAD | Number of uops to be executed per-thread each cycle. | EventSel=B1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_0 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0. | EventSel=A1H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_0_CORE | Cycles per core when uops are executed in port 0. | EventSel=A1H UMask=01H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_1 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1. | EventSel=A1H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_1_CORE | Cycles per core when uops are executed in port 1. | EventSel=A1H UMask=02H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_2 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2. | EventSel=A1H UMask=04H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_2_CORE | Cycles per core when uops are dispatched to port 2. | EventSel=A1H UMask=04H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_3 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3. | EventSel=A1H UMask=08H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_3_CORE | Cycles per core when uops are dispatched to port 3. | EventSel=A1H UMask=08H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_4 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4. | EventSel=A1H UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_4_CORE | Cycles per core when uops are executed in port 4. | EventSel=A1H UMask=10H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_5 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5. | EventSel=A1H UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_5_CORE | Cycles per core when uops are executed in port 5. | EventSel=A1H UMask=20H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_6 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6. | EventSel=A1H UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_6_CORE | Cycles per core when uops are executed in port 6. | EventSel=A1H UMask=40H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_7 | This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7. | EventSel=A1H UMask=80H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_EXECUTED_PORT.PORT_7_CORE | Cycles per core when uops are dispatched to port 7. | EventSel=A1H UMask=80H AnyThread=1 Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.ANY | This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS). | EventSel=0EH UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.FLAGS_MERGE | Number of flags-merge uops being allocated. Such uops considered perf sensitive added by GSR u-arch. | EventSel=0EH UMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.SINGLE_MUL | Number of Multiply packed/scalar single precision uops allocated. | EventSel=0EH UMask=40H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.SLOW_LEA | Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. | EventSel=0EH UMask=20H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 |
| UOPS_ISSUED.STALL_CYCLES | This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread. | EventSel=0EH UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 |
| UOPS_RETIRED.ALL | This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight. | EventSel=C2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.ALL_PS | This is a precise version (that is, uses PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight. | EventSel=C2H UMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS | This event counts the number of retirement slots used. | EventSel=C2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3,4,5,6,7 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.RETIRE_SLOTS_PS | This is a precise version (that is, uses PEBS) of the event that counts the number of retirement slots used. | EventSel=C2H UMask=02H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.STALL_CYCLES | This event counts cycles without actually retired uops. | EventSel=C2H UMask=01H Invert=1 CMask=01H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UOPS_RETIRED.TOTAL_CYCLES | Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event. | EventSel=C2H UMask=01H Invert=1 CMask=10H Counter=0,1,2,3 CounterHTOff=0,1,2,3 PEBS:[PreciseEventingIP] |
| UNCORE | ||
| UNC_CLOCK.SOCKET | This 48-bit fixed counter counts the UCLK cycles. | MSR_UNC_PERF_FIXED_CTR Fixed |
| UNC_ARB_COH_TRK_REQUESTS.ALL | Number of entries allocated. Account for Any type: e.g. Snoop, Core aperture, etc. | EventSel=84H UMask=01H Counter=0,1 |
| UNC_ARB_TRK_OCCUPANCY.ALL | Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic. | EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST | Cycles with at least one request outstanding is waiting for data return from memory controller. Account for coherent and non-coherent requests initiated by IA Cores, Processor Graphics Unit, or LLC. | EventSel=80H UMask=01H Counter=0 |
| UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT | Each cycle count number of "valid" coherent Data Read entries that are in DirectData mode. Such entry is defined as valid when it is allocated till data sent to Core (first chunk, IDI0). Applicable for IA Cores' requests in normal case. | EventSel=80H UMask=02H Counter=0 |
| UNC_ARB_TRK_REQUESTS.ALL | Total number of Core outgoing entries allocated. Accounts for Coherent and non-coherent traffic. | EventSel=81H UMask=01H Counter=0,1 |
| UNC_ARB_TRK_REQUESTS.DRD_DIRECT | Number of Core coherent Data Read entries allocated in DirectData mode. | EventSel=81H UMask=02H Counter=0,1 |
| UNC_ARB_TRK_REQUESTS.WRITES | Number of Writes allocated - any write transactions: full/partials writes and evictions. | EventSel=81H UMask=20H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_ES | L3 Lookup any request that access cache and found line in E or S-state. | EventSel=34H UMask=86H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_I | L3 Lookup any request that access cache and found line in I-state. | EventSel=34H UMask=88H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_M | L3 Lookup any request that access cache and found line in M-state. | EventSel=34H UMask=81H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.ANY_MESI | L3 Lookup any request that access cache and found line in MESI-state. | EventSel=34H UMask=8FH Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_ES | L3 Lookup read request that access cache and found line in E or S-state. | EventSel=34H UMask=16H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_I | L3 Lookup read request that access cache and found line in I-state. | EventSel=34H UMask=18H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_M | L3 Lookup read request that access cache and found line in M-state. | EventSel=34H UMask=11H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.READ_MESI | L3 Lookup read request that access cache and found line in any MESI-state. | EventSel=34H UMask=1FH Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_ES | L3 Lookup write request that access cache and found line in E or S-state. | EventSel=34H UMask=26H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_M | L3 Lookup write request that access cache and found line in M-state. | EventSel=34H UMask=21H Counter=0,1 |
| UNC_CBO_CACHE_LOOKUP.WRITE_MESI | L3 Lookup write request that access cache and found line in MESI-state. | EventSel=34H UMask=2FH Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.HIT_XCORE | A cross-core snoop initiated by this Cbox due to processor core memory request which hits a non-modified line in some processor core. | EventSel=22H UMask=44H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.HITM_XCORE | A cross-core snoop initiated by this Cbox due to processor core memory request which hits a modified line in some processor core. | EventSel=22H UMask=48H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.MISS_EVICTION | A cross-core snoop resulted from L3 Eviction which misses in some processor core. | EventSel=22H UMask=81H Counter=0,1 |
| UNC_CBO_XSNP_RESPONSE.MISS_XCORE | A cross-core snoop initiated by this Cbox due to processor core memory request which misses in some processor core. | EventSel=22H UMask=41H Counter=0,1 |
| OFFCORE | ||
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=ANY_RESPONSE | Counts demand data reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NONE | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_MISS | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_HITM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_HIT.ANY_SNOOP | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_NONE | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_MISS | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000001H |
| OFFCORE_RESPONSE:request=DEMAND_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts demand data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000001H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=ANY_RESPONSE | Counts all demand data writes (RFOs) have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NONE | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_MISS | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_HITM | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.SNOOP_NON_DRAM | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_HIT.ANY_SNOOP | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_NONE | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_MISS | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000002H |
| OFFCORE_RESPONSE:request=DEMAND_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all demand data writes (RFOs) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000002H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=ANY_RESPONSE | Counts all demand code reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NONE | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_MISS | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_HITM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_HIT.ANY_SNOOP | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_NONE | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_MISS | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000004H |
| OFFCORE_RESPONSE:request=DEMAND_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all demand code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000004H |
| OFFCORE_RESPONSE:request=COREWB: response=ANY_RESPONSE | Counts writebacks (modified to exclusive) have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NONE | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_MISS | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_HITM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020008H |
| OFFCORE_RESPONSE:request=COREWB: response=SUPPLIER_NONE.ANY_SNOOP | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NONE | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NOT_NEEDED | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_MISS | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_HITM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.SNOOP_NON_DRAM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_HIT.ANY_SNOOP | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_NONE | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_NOT_NEEDED | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_MISS | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000008H |
| OFFCORE_RESPONSE:request=COREWB: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts writebacks (modified to exclusive) | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000008H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=ANY_RESPONSE | Counts prefetch (that bring data to L2) data reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NONE | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_MISS | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_HITM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_HIT.ANY_SNOOP | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_NONE | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_MISS | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000010H |
| OFFCORE_RESPONSE:request=PF_L2_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to L2) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000010H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=ANY_RESPONSE | Counts all prefetch (that bring data to L2) RFOs have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NONE | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_MISS | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_HITM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_HIT.ANY_SNOOP | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_NONE | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_MISS | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000020H |
| OFFCORE_RESPONSE:request=PF_L2_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to L2) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000020H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=ANY_RESPONSE | Counts all prefetch (that bring data to LLC only) code reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_HIT.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000040H |
| OFFCORE_RESPONSE:request=PF_L2_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000040H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=ANY_RESPONSE | Counts all prefetch (that bring data to LLC only) data reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_HIT.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000080H |
| OFFCORE_RESPONSE:request=PF_L3_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000080H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=ANY_RESPONSE | Counts all prefetch (that bring data to LLC only) RFOs have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_HIT.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_NONE | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_MISS | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000100H |
| OFFCORE_RESPONSE:request=PF_L3_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch (that bring data to LLC only) RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000100H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=ANY_RESPONSE | Counts prefetch (that bring data to LLC only) code reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NONE | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_MISS | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_HITM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_HIT.ANY_SNOOP | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_NONE | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_MISS | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000200H |
| OFFCORE_RESPONSE:request=PF_L3_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts prefetch (that bring data to LLC only) code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000200H |
| OFFCORE_RESPONSE:request=OTHER: response=ANY_RESPONSE | Counts any other requests have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=18000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NONE | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_MISS | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_HITM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000028000H |
| OFFCORE_RESPONSE:request=OTHER: response=SUPPLIER_NONE.ANY_SNOOP | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80028000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NONE | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NOT_NEEDED | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_MISS | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_HITM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.SNOOP_NON_DRAM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_HIT.ANY_SNOOP | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C8000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_NONE | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_NOT_NEEDED | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_MISS | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C008000H |
| OFFCORE_RESPONSE:request=OTHER: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts any other requests | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C008000H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=ANY_RESPONSE | Counts all prefetch data reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NONE | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_MISS | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_HITM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_HIT.ANY_SNOOP | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_NONE | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_MISS | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000090H |
| OFFCORE_RESPONSE:request=ALL_PF_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000090H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=ANY_RESPONSE | Counts prefetch RFOs have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NONE | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_MISS | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_HITM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=SUPPLIER_NONE.ANY_SNOOP | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NONE | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NOT_NEEDED | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_MISS | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_HITM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.SNOOP_NON_DRAM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_HIT.ANY_SNOOP | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_NONE | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_NOT_NEEDED | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_MISS | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000120H |
| OFFCORE_RESPONSE:request=ALL_PF_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000120H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=ANY_RESPONSE | Counts all prefetch code reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NONE | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_MISS | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_HITM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_HIT.ANY_SNOOP | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_NONE | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_MISS | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000240H |
| OFFCORE_RESPONSE:request=ALL_PF_CODE_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all prefetch code reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000240H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=ANY_RESPONSE | Counts all demand & prefetch data reads have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NONE | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_MISS | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_HITM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=SUPPLIER_NONE.ANY_SNOOP | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NONE | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_MISS | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_HITM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.SNOOP_NON_DRAM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_HIT.ANY_SNOOP | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_NONE | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_MISS | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000091H |
| OFFCORE_RESPONSE:request=ALL_DATA_RD: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all demand & prefetch data reads | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000091H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=ANY_RESPONSE | Counts all demand & prefetch RFOs have any response type. | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NONE | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=80020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NOT_NEEDED | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=100020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_MISS | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=200020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_HIT_NO_FWD | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=400020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_HITM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1000020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.SNOOP_NON_DRAM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2000020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=SUPPLIER_NONE.ANY_SNOOP | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F80020122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NONE | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=803C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NOT_NEEDED | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1003C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_MISS | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2003C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_HIT_NO_FWD | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=4003C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_HITM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=10003C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.SNOOP_NON_DRAM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=20003C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_HIT.ANY_SNOOP | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F803C0122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NONE | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=84000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=104000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_MISS | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=204000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=404000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_HITM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=1004000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.SNOOP_NON_DRAM | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=2004000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS_LOCAL_DRAM.ANY_SNOOP | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=3F84000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_NONE | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=BC000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_NOT_NEEDED | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=13C000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_MISS | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=23C000122H |
| OFFCORE_RESPONSE:request=ALL_RFO: response=L3_MISS.SNOOP_HIT_NO_FWD | Counts all demand & prefetch RFOs | EventSel={B7H,BBH} UMask=01H MSR_OFFCORE_RSPx{1A6H,1A7H}=43C000122H |